Package structure and manufacturing method thereof

Abstract

The application provides a packaging structure and a manufacturing method thereof. The method comprises the following steps: providing a semiconductor wafer, wherein the semiconductor wafer comprises a plurality of first semiconductor chips; for each first semiconductor chip, at least one second semiconductor chip corresponding to the first semiconductor chip is provided with a notch or an opening to expose a light coupling area, so that the proportion of the sum of the areas of all the second semiconductor chips corresponding to the first semiconductor chip and the area of the first surface of the first semiconductor chip is increased, the effective utilization areas of the first semiconductor chip and the second semiconductor chip are improved, and the pollution of the organic material in the plastic encapsulation layer to the interface of the light coupling area is avoided.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging, and in particular to a packaging structure and its manufacturing method. Background Technology

[0002] With the continuous development of semiconductor technology, packaging structures with high integration density are becoming increasingly important. For example, 3D packaging structures can enable the stacking of chips together.

[0003] Currently, existing silicon photonic chips, specifically electronic integrated circuit chips (EIC chips) and photonic integrated circuit chips (PIC chips), employ different wafer fabrication processes. They utilize chip-level interconnects (such as wire bonding or flip-chip interconnects) to connect the EIC chips and PIC chips, forming a three-dimensional interconnect structure.

[0004] To shorten signal transmission paths and achieve sufficiently good electrical performance, the use of 3D stacking interconnects to replace traditional wire bonding for photonic integrated circuit (PIC) chips and electronic integrated circuit (EIC) chips is becoming increasingly popular. However, when fiber optic structures are coupled to PIC chips via surface coupling with grating couplers (GC), space must be reserved for coupling. Furthermore, the coupling surface must be free of organic matter that could obstruct light transmission. This prevents the placement of EIC chips in the optical coupling area and its width extension, resulting in wasted area and a reduced area ratio for both EIC and PIC chips. Consequently, the area utilization rate of both types of chips is low. Summary of the Invention

[0005] In order to overcome the shortcomings of the prior art, the present invention aims to provide a packaging structure and its manufacturing method, which can realize 3D chip stacking packaging and improve the area utilization of electronic integrated circuit chips (EIC chips) and photonic integrated circuit chips (PIC chips).

[0006] The objective of this invention is achieved through the following technical solution:

[0007] According to one aspect of the present invention, a method for manufacturing an encapsulation structure is provided, the method comprising:

[0008] A semiconductor wafer is provided, the semiconductor wafer comprising a plurality of first semiconductor chips, each first semiconductor chip having opposing first and second surfaces, the first surface having an optical coupling region and a non-optical coupling region surrounding the optical coupling region, the optical coupling region having an optical coupling interface disposed therein;

[0009] For each of the first semiconductor chips, at least one second semiconductor chip corresponding to the first semiconductor chip is provided, and the at least one second semiconductor chip is fixed on the non-optically coupled region of the first surface of the first semiconductor chip;

[0010] Before fixing at least one second semiconductor chip corresponding to each first semiconductor chip onto the first semiconductor chip, a first side of the at least one second semiconductor chip is cut, and a notch is formed along the first side towards the interior of the corresponding second semiconductor chip after cutting, the length of the notch being less than the length of the first side.

[0011] Specifically, for each of the second semiconductor chips having the notch, the edge of the notch of the second semiconductor chip is arranged around the optical coupling region to expose the optical coupling region.

[0012] Optionally, for each first semiconductor chip, the first side of a second semiconductor chip corresponding to the first semiconductor chip is cut, and after cutting, a notch is formed that is recessed along the first side toward the interior of the second semiconductor chip. The area where the notch is located is in the middle or end of the first side of the second semiconductor chip, and the shape of the notch is adapted to the shape of the optical coupling region.

[0013] Optionally, for each of the first semiconductor chips, the first side edges of the two second semiconductor chips corresponding to the first semiconductor chip are cut, and a first notch and a second notch are formed respectively along the first side edge towards the interior of the two corresponding semiconductor chips after cutting. The regions where the first notch and the second notch are located are respectively located at the ends of the first side edges of the two corresponding second semiconductor chips. One of the second semiconductor chips with the first notch and the other of the second semiconductor chips with the second notch are fixed around the optical coupling area by splicing, and the shape of the total notch formed by the first notch and the second notch after splicing is adapted to the shape of the optical coupling area.

[0014] Furthermore, for each of the second semiconductor chips having the notch, the first side of the second semiconductor chip extends in its length direction or width direction to a side edge close to the first semiconductor chip.

[0015] Furthermore, for each of the first semiconductor chips, the area occupied by the first surface of the first semiconductor chip is defined as S1, and the sum of the areas occupied by all the second semiconductor chips corresponding to the first semiconductor chip is defined as S2, wherein the ratio between S2 and S1 is greater than 80%.

[0016] Furthermore, the semiconductor wafer includes: a first carrier substrate, which is temporarily bonded to the second surface of the plurality of first semiconductor chips for temporarily supporting the semiconductor wafer.

[0017] Furthermore, after fixing at least one second semiconductor chip corresponding to each first semiconductor chip onto the first semiconductor chip, the method further includes: bonding the side surface of each second semiconductor chip away from the corresponding first semiconductor chip to a temporary bonding film, and then debonding the first carrier substrate.

[0018] Furthermore, the method further includes: after debonding the first carrier substrate, cutting the semiconductor wafer in a direction from the second surface to the first surface for each of the regions corresponding to the first semiconductor chip on the semiconductor wafer; and removing the temporary bonding film to obtain a plurality of separate chip packaging components, wherein each chip packaging component includes a first semiconductor chip and at least one corresponding second semiconductor chip.

[0019] Optionally, the temporary bonding film includes a photosensitive material, which is removed by light irradiation.

[0020] Furthermore, the method further includes: after obtaining multiple separate chip packaging components, mounting each chip packaging component onto a corresponding packaging substrate, and then mounting a light guide structure or laser chip onto the optical coupling interface of the first semiconductor chip.

[0021] According to another aspect of the present invention, a method for manufacturing an encapsulation structure is provided, the method comprising:

[0022] A semiconductor wafer is provided, the semiconductor wafer comprising a plurality of first semiconductor chips, each first semiconductor chip having opposing first and second surfaces, the first surface having an optical coupling region and a non-optical coupling region surrounding the optical coupling region, the optical coupling region having an optical coupling interface disposed therein;

[0023] For each first semiconductor chip, at least one second semiconductor chip corresponding to the first semiconductor chip is provided, and the at least one second semiconductor chip is fixed on the first surface of the first semiconductor chip; wherein, the at least one second semiconductor chip is provided with a virtual area, the virtual area being a region without circuitry; for each second semiconductor chip having the virtual area, one side edge of the virtual area coincides with the first side edge of the second semiconductor chip; and the virtual area of ​​the at least one second semiconductor chip is correspondingly covered over the optical coupling area;

[0024] A molding layer is fabricated, and the molding layer is exposed on the side surface of each of the second semiconductor chips facing away from the first semiconductor chip;

[0025] For each of the first semiconductor chips, the virtual area on the at least one second semiconductor chip covering the optical coupling region is removed to form an opening exposing the optical coupling region.

[0026] Optionally, for each of the first semiconductor chips, a virtual region is provided on a second semiconductor chip corresponding to the first semiconductor chip, one edge of the virtual region being located in the middle or end of the first side of the second semiconductor chip, and the shape of the virtual region being adapted to the shape of the optical coupling region.

[0027] Optionally, for each of the first semiconductor chips, a first virtual region and a second virtual region are respectively provided on two second semiconductor chips corresponding to the first semiconductor chip. One side edge of the first virtual region and one side edge of the second virtual region are respectively located at the ends of the first side edges of the two second semiconductor chips. One of the second semiconductor chips with the first virtual region and another of the second semiconductor chips with the second virtual region are spliced ​​together to cover the optical coupling region. The shape of the total virtual region formed by the splicing of the first virtual region and the second virtual region is adapted to the shape of the optical coupling region.

[0028] Furthermore, for each of the second semiconductor chips having the virtual region, the first side of the second semiconductor chip extends in its length direction or width direction to a side edge close to the first semiconductor chip.

[0029] Furthermore, for each of the first semiconductor chips, the area occupied by the first surface of the first semiconductor chip is defined as S1, and the sum of the areas occupied by all the second semiconductor chips corresponding to the first semiconductor chip is defined as S2, wherein the ratio between S2 and S1 is greater than 80%.

[0030] Furthermore, the method for removing the virtual area on the at least one second semiconductor chip covering the optical coupling region for each of the first semiconductor chips includes: cutting the location of the virtual area on the at least one second semiconductor chip by laser cutting or plasma cutting to remove the virtual area.

[0031] Furthermore, the semiconductor wafer includes: a first carrier substrate, which is temporarily bonded to the second surface of the plurality of first semiconductor chips for temporarily supporting the semiconductor wafer.

[0032] Furthermore, after removing the virtual region on the at least one second semiconductor chip covering the optical coupling region for each of the first semiconductor chips, the method further includes: bonding the side surface of each second semiconductor chip away from the corresponding first semiconductor chip to a temporary bonding film, and then debonding the first carrier substrate.

[0033] Furthermore, the method further includes: after debonding the first carrier substrate, cutting the semiconductor wafer in a direction from the second surface to the first surface for each of the regions corresponding to the first semiconductor chip on the semiconductor wafer; and removing the temporary bonding film to obtain a plurality of separate chip packaging components, wherein each chip packaging component includes a first semiconductor chip and at least one corresponding second semiconductor chip.

[0034] Furthermore, the method further includes: after obtaining multiple separate chip packaging components, mounting each chip packaging component onto a corresponding packaging substrate, and then mounting a light guide structure or laser chip onto the optical coupling interface of the first semiconductor chip.

[0035] According to another aspect of the present invention, a packaging structure is also provided, comprising:

[0036] A first semiconductor chip has a first surface and a second surface opposite to each other. An optical coupling region and a non-optical coupling region surrounding the optical coupling region are provided on the first surface. An optical coupling interface is provided within the optical coupling region.

[0037] At least one second semiconductor chip, the at least one second semiconductor chip being fixed on the non-optically coupled region of the first surface;

[0038] The first side of the at least one second semiconductor chip is provided with a notch that is recessed toward the interior of the corresponding second semiconductor chip, and for each second semiconductor chip with the notch, the edge of the notch surrounds the optical coupling region to expose the optical coupling region.

[0039] Optionally, for each of the first semiconductor chips, a notch is provided on the first side of a second semiconductor chip corresponding to the first semiconductor chip. The area where the notch is located is in the middle or at the end of the first side of the second semiconductor chip, wherein the shape of the notch is adapted to the shape of the optical coupling region.

[0040] Optionally, for each of the first semiconductor chips, a first notch and a second notch are respectively formed on the first side of two second semiconductor chips corresponding to the first semiconductor chip. The regions where the first notch and the second notch are located are respectively located at the ends of the first side of the two second semiconductor chips. The second semiconductor chip with the first notch and the other second semiconductor chip with the second notch are fixed around the optical coupling area by splicing. The shape of the total notch formed by the splicing of the first notch and the second notch is adapted to the shape of the optical coupling area.

[0041] Furthermore, for each of the second semiconductor chips having the notch, the first side of the second semiconductor chip extends in its length direction or width direction to a side edge close to the first semiconductor chip.

[0042] Furthermore, for each of the first semiconductor chips, the area occupied by the first surface of the first semiconductor chip is defined as S1, and the sum of the areas occupied by all the second semiconductor chips corresponding to the first semiconductor chip is defined as S2, wherein the ratio between S2 and S1 is greater than 80%.

[0043] According to another aspect of the present invention, a packaging structure is also provided, comprising:

[0044] A first semiconductor chip has a first surface and a second surface opposite to each other. An optical coupling region and a non-optical coupling region surrounding the optical coupling region are provided on the first surface. An optical coupling interface is provided within the optical coupling region.

[0045] At least one second semiconductor chip is fixed on the non-optically coupled region of the first surface, and an opening is provided in the optically coupled region to penetrate the at least one second semiconductor chip. For each second semiconductor chip having the opening, one side edge of the opening coincides with the first side edge of the second semiconductor chip.

[0046] A molding compound is located on the first surface and on the side of the at least one second semiconductor chip, and the opening is not filled or covered by the molding compound.

[0047] Furthermore, for each of the second semiconductor chips having the opening, the first side of the second semiconductor chip extends in its length direction or width direction to a side edge close to the first semiconductor chip.

[0048] Furthermore, for each of the first semiconductor chips, the area occupied by the first surface of the first semiconductor chip is defined as S1, and the sum of the areas occupied by all the second semiconductor chips corresponding to the first semiconductor chip is defined as S2, wherein the ratio between S2 and S1 is greater than 80%.

[0049] The packaging structure and manufacturing method provided in this invention, since for each first semiconductor chip, at least one second semiconductor chip corresponding to the first semiconductor chip has a notch or opening to expose the optical coupling region, increases the ratio of the sum of the areas occupied by all the second semiconductor chips corresponding to the first semiconductor chip to the area occupied by the first surface of the first semiconductor chip compared with common technologies. At the same time, it is also beneficial to improve the effective utilization area of ​​the first semiconductor chip and the second semiconductor chip respectively, and avoids the problem of contamination of the optical coupling region interface by the organic materials in the molding layer. Attached Figure Description

[0050] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other implementation methods can be obtained based on these drawings without creative effort.

[0051] Figure 1 This is a flowchart of a method for manufacturing an encapsulation structure according to Embodiment 1 of the present invention.

[0052] Figures 2A-2C This is a schematic diagram of the manufacturing process of a packaging structure according to Embodiment 1 of the present invention.

[0053] Figures 3A-3EThis is a schematic diagram of the manufacturing process of another packaging structure provided in Embodiment 1 of the present invention.

[0054] Figure 4 This is a schematic diagram of the planar structure of a first semiconductor chip provided according to an embodiment of the present invention.

[0055] Figure 5 This is a schematic diagram of the structure of a second semiconductor chip with a notch before and after cutting, according to Embodiment 1 of the present invention.

[0056] Figure 6 This is a schematic diagram of a 3D stacked structure of a first semiconductor chip and a corresponding second semiconductor chip with a notch, according to Embodiment 1 of the present invention.

[0057] Figure 7 This is a schematic diagram of a 3D stacked structure of a first semiconductor chip and two corresponding second semiconductor chips with notches, according to Embodiment 1 of the present invention.

[0058] Figure 8 This is a schematic diagram of a chip-level packaging structure provided according to Embodiment 1 of the present invention.

[0059] Figure 9 This is a schematic diagram of the connection between the chip-level packaging structure and the packaging substrate provided in Embodiment 1 of the present invention.

[0060] Figure 10 This is a flowchart of a method for manufacturing a packaging structure according to Embodiment 2 of the present invention.

[0061] Figure 11 This is a schematic diagram of a 3D stacked structure of a first semiconductor chip and a corresponding second semiconductor chip with a virtual region according to Embodiment 2 of the present invention.

[0062] Figure 12 This is a schematic diagram of a 3D stacked structure of a first semiconductor chip and two corresponding second semiconductor chips with virtual regions according to Embodiment 2 of the present invention.

[0063] Figures 13A-13D This is a schematic diagram of the manufacturing process of a packaging structure according to Embodiment 2 of the present invention.

[0064] Figures 14A-14F This is a schematic diagram of the manufacturing process of another packaging structure provided in Embodiment 2 of the present invention.

[0065] Figure 15 This is a schematic diagram of a chip-level packaging structure provided according to Embodiment 2 of the present invention.

[0066] Figure 16This is a schematic diagram of the connection between the chip-level packaging structure and the packaging substrate provided in Embodiment 2 of the present invention. Detailed Implementation

[0067] The above description is merely an overview of the technical solution of the present invention. In order to better understand the technical means of the present invention and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described in detail below with reference to the accompanying drawings.

[0068] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection, an electrical connection, or a connection that allows for communication; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. The term "chip" in this document can include a bare chip. When referring to method steps, the sequence of steps illustrated herein represents an exemplary scheme but does not imply a limitation on the sequence. Those skilled in the art can understand the specific meaning of the above terms in this invention according to the specific circumstances.

[0069] In view of the technical problems mentioned in the background art, the purpose of this invention is to provide a new packaging structure and its manufacturing method, which aims to increase the area utilization of the electronic integrated circuit chip (EIC chip) and the photonic integrated circuit chip (PIC chip) by changing the layout of the electronic integrated circuit chip (EIC chip) without affecting the optical coupling between the optical fiber structure and the photonic integrated circuit chip (PIC chip) through the surface coupling method.

[0070] To make the objectives, features and advantages of the present invention more apparent and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0071] Example 1

[0072] Figure 1 This is a flowchart of a method for manufacturing a packaging structure according to Embodiment 1 of the present invention. The method for manufacturing the packaging structure includes:

[0073] S11, a semiconductor wafer is provided, the semiconductor wafer including a plurality of first semiconductor chips, each first semiconductor chip having a first surface and a second surface opposite to each other, an optical coupling region and a non-optical coupling region surrounding the optical coupling region are disposed on the first surface, and an optical coupling interface is disposed within the optical coupling region;

[0074] S12, for each of the first semiconductor chips, at least one second semiconductor chip corresponding to the first semiconductor chip is provided, and the at least one second semiconductor chip is fixed on the non-optically coupled area of ​​the first surface of the first semiconductor chip;

[0075] S13, before fixing at least one second semiconductor chip corresponding to each first semiconductor chip onto the first semiconductor chip, the first side of the at least one second semiconductor chip is cut, and after cutting, a notch is formed along the first side towards the interior of the corresponding second semiconductor chip, the length of the notch being less than the length of the first side.

[0076] Specifically, for each of the second semiconductor chips having the notch, the edge of the notch of the second semiconductor chip is arranged around the optical coupling region to expose the optical coupling region.

[0077] Figures 2A-2C This is a schematic diagram of the manufacturing process of a packaging structure according to Embodiment 1 of the present invention. Figures 3A-3E This is a schematic diagram of the manufacturing process of another packaging structure provided by an embodiment of the present invention. Figure 4 This is a schematic diagram of the planar structure of a first semiconductor chip provided according to an embodiment of the present invention. Figure 5 This is a schematic diagram of the structure of a second semiconductor chip with a notch before and after cutting, according to Embodiment 1 of the present invention. Figure 6 This is a schematic diagram of a 3D stacked structure of a first semiconductor chip and a corresponding second semiconductor chip with a notch, according to Embodiment 1 of the present invention. Figure 7 This is a schematic diagram of a 3D stacked structure of a first semiconductor chip and two corresponding second semiconductor chips with notches, according to Embodiment 1 of the present invention. Figure 8 This is a schematic diagram of a chip-level packaging structure provided according to Embodiment 1 of the present invention.

[0078] The following will combine Figures 2A-2C , Figures 3A-3E , Figures 4-8 The embodiments of the present invention will be described in detail below.

[0079] In an embodiment of the present invention, the first semiconductor chip 102 is, exemplarily, a photonic integrated circuit chip (PIC chip), wherein the photonic integrated circuit chip uses photons as information carriers to process information and transmit data, and may be a silicon-based photonic integrated circuit chip. The second semiconductor chip 103 is an electronic integrated circuit chip (EIC chip), wherein the electronic integrated circuit chip uses electrons as information carriers to process information and transmit data, such as a silicon-based electronic integrated circuit chip, a germanium-based electronic integrated circuit chip, or a compound semiconductor electronic integrated circuit chip. The integration of the photonic integrated circuit chip and the electronic integrated circuit chip can be achieved by stacking the first semiconductor chip 102 and the second semiconductor chip 103.

[0080] For example, please refer to Figure 2A As shown, a semiconductor wafer 100 is first provided, the semiconductor wafer 100 including a plurality of first semiconductor chips 102, each of the first semiconductor chips 102 having opposing first surfaces 102a and second surfaces 102b.

[0081] like Figure 4 As shown, exemplarily, the first semiconductor chip 102 has an optical coupling region 1024 and a non-optical coupling region 1025 surrounding the optical coupling region 1024 on its first surface 102a. An optical coupling interface 104 is provided within the optical coupling region 1024. Light provided by an external light source can be input into the optical coupling interface 104 through a fiber array (FA), for example, by coupling into the first semiconductor chip 102 through a grating coupler within the optical coupling interface 104. It should be noted that in other embodiments, other optical interconnect interfaces or devices for transmitting optical signals can also be correspondingly provided within the optical coupling interface 104.

[0082] like Figures 2B-2CAs shown, for each first semiconductor chip 102, at least one second semiconductor chip 103 corresponding to the first semiconductor chip 102 is provided, and the at least one second semiconductor chip 103 is fixed to the non-optically coupled region 1025 of the first surface 102a of the first semiconductor chip 102. For example, it can be fixed by means of thermal compress bonding (TCB), reflow soldering, laser bonding, direct metal bonding, or hybrid metal-oxide bonding. Exemplarily, in this embodiment of the invention, the second semiconductor chip 103 is soldered to the first semiconductor chip 102 by flip-chip bonding. Optionally, an underfill is filled in the gap between each second semiconductor chip 103 and the first surface 102a to further reinforce each second semiconductor chip 103.

[0083] Among them, such as Figure 5 As shown, before fixing at least one second semiconductor chip 103 corresponding to each first semiconductor chip 102 onto the first semiconductor chip 102, the first side 1031 of the at least one second semiconductor chip 103 is cut, and a notch 400 is formed along the first side 1031 toward the interior of the corresponding second semiconductor chip 103 after cutting. The length of the notch 400 is less than the length of the first side 1031. Specifically, for the part that needs to be cut, laser cutting or plasma cutting can be used for cutting. If necessary, a wafer thinning process can be performed on the second semiconductor chip 103 before wafer-level cutting, and then the normal wafer dicing positions are cut according to the conventional wafer cutting process, as well as the part that needs to be cut.

[0084] This embodiment of the invention illustrates the formation of a second semiconductor chip 103 above the first semiconductor chip 102. In actual use, there can be more than one second semiconductor chip 103, such as two, three, four, or more, which can be flexibly selected according to actual needs. Furthermore, small pieces of bare silicon wafers (wafers without integrated or any photonic or electronic devices) can be added to the edge of the semiconductor wafer 100 to fix the area of ​​the edge of the semiconductor wafer 100 not occupied by the second semiconductor chip 103, thereby ensuring consistent stress at various locations above the semiconductor wafer.

[0085] For example, such as Figure 6As shown, in some embodiments, for each first semiconductor chip 102, the first side 1031 of a second semiconductor chip 103 corresponding to that first semiconductor chip 102 is cut, and after cutting, a notch 400 is formed that is recessed along the first side 1031 toward the interior of the second semiconductor chip 103. The area where the notch 400 is located is in the middle or end of the first side 1031 of the second semiconductor chip 103, and the shape of the notch 400 is adapted to the shape of the optical coupling region 1024 on the first semiconductor chip 102. Therefore, the size and shape of the notch 400 of the corresponding second semiconductor chip 103 can be designed according to the shape of the non-optical coupling region 1025 of each first semiconductor chip 102, so as to make full use of the surface area of ​​the first semiconductor chip 102 and increase the utilization area of ​​all second semiconductor chips 103 corresponding to the first semiconductor chip 102.

[0086] For example, such as Figure 7 As shown, in some other embodiments, for each first semiconductor chip 102, the first side 1031 of each of the two second semiconductor chips 103 corresponding to that first semiconductor chip 102 is cut, and after cutting, a first notch 410 and a second notch 420 are formed along the first side 1031 toward the interior of the corresponding two semiconductor chips 103. The regions where the first notch 410 and the second notch 420 are located are respectively at the ends of the first side 1031 of the corresponding two second semiconductor chips 103. One of the second semiconductor chips 103 with the first notch 410 and the other with the second notch 420 are fixed around the optical coupling region 1024 in a splicing manner, and the shape of the total notch formed by the first notch 410 and the second notch 420 after splicing is adapted to the shape of the optical coupling region 1024. It should be understood that in this embodiment, when multiple second semiconductor chips 103 are spliced, there may be gaps between some of the second semiconductor chips 103 and their adjacent second semiconductor chips 103. Therefore, the size and shape of each notch of the corresponding plurality of second semiconductor chips 103 can be designed according to the shape of the non-optical coupling region 1025 of each first semiconductor chip 102, so as to make full use of the surface area of ​​the first semiconductor chip 102 and increase the utilization area of ​​all the second semiconductor chips 103 corresponding to the first semiconductor chip 102.

[0087] Furthermore, for each of the second semiconductor chips 103 with a notch, the first side 1031 of the second semiconductor chip 103 extends in its length or width direction to a side edge close to the first semiconductor chip 102, thereby increasing the area utilization of at least one second semiconductor chip 103 located above the optical coupling region 1024.

[0088] Furthermore, for each of the first semiconductor chips 102, the area occupied by the first surface 102a of the first semiconductor chip 102 is defined as S1, and the sum of the areas occupied by all the second semiconductor chips 103 corresponding to the first semiconductor chip 102 is defined as S2, wherein the ratio between S2 and S1 is greater than 80%, so that the first surface 102a of the first semiconductor chip 102 can be fixed by as many second semiconductor chips 103 as possible. This is because during the packaging process of optoelectronic chips, it may be necessary to thin the first semiconductor chip (PIC chip) 102. However, traditional thinning processes can easily cause the first semiconductor chip (PIC chip) 102 to warp, resulting in misalignment or even failure of the connection between the first semiconductor chip (PIC chip) 102 and the second semiconductor chip (EIC) 103. By setting the area of ​​the non-optically coupled region 1025 of the first surface 102a of the first semiconductor chip (PIC chip) 102 where the second semiconductor chip (EIC chip) 103 is not fixed to it to be greater than 80% of the area occupied by the first surface of the first semiconductor chip 102, for example, 80% to 90%, the warping problem of the thinned first semiconductor chip 102 can be prevented. Therefore, when the semiconductor wafer 100 is used as the lower carrier, a wafer-level 3D chip stacking packaging process can be used to mount the stacked second semiconductor chips 103 onto the corresponding first semiconductor chips 102, and then perform overall cutting, avoiding the stress problem during the cutting of unencapsulated semiconductor wafers, thereby realizing unencapsulated wafer-level 3D chip stacking packaging. At the same time, the effective utilization area of ​​the corresponding first semiconductor chip 102 and second semiconductor chip 103 is also improved.

[0089] Optionally, in some embodiments, to avoid the problem of warping easily in the thinned first semiconductor chip 102, which could lead to misalignment or failure of the connection point between the second semiconductor chip 103 and the first semiconductor chip 102, such as... Figure 3A As shown, the semiconductor wafer 100 further includes a first carrier substrate 200, which is temporarily bonded to the second surface 102b of the plurality of first semiconductor chips 102 by bonding adhesive 201 for temporarily supporting the semiconductor wafer 100.

[0090] Next, as Figure 3BAs shown, for each first semiconductor chip 102, at least one second semiconductor chip 103 corresponding to that first semiconductor chip 102 is provided, and the at least one second semiconductor chip 103 is fixed to the non-optically coupled region 1025 of the first surface 102a of the first semiconductor chip 102, for example, by soldering or other methods. In this embodiment of the invention, the second semiconductor chip 103 is soldered to the first semiconductor chip 102 by flip-chip soldering. Optionally, underfill is filled in the gap between each second semiconductor chip 103 and the first surface 102a to further reinforce each second semiconductor chip 103.

[0091] Furthermore, such as Figure 3C As shown, after fixing at least one second semiconductor chip 103 corresponding to each first semiconductor chip 102 onto the first semiconductor chip 102, the method includes: bonding the side surface of each second semiconductor chip 103 away from the corresponding first semiconductor chip 102 to a temporary bonding film 500. Specifically, an adhesive may be provided on the surface of the temporary bonding film 500 that is about to be bonded to the second semiconductor chip 103, and the adhesive is used to bond the side surface of each second semiconductor chip 103 away from the corresponding first semiconductor chip 102 to the temporary bonding film 500.

[0092] like Figure 3D As shown, after bonding the side surface of each second semiconductor chip 103 facing away from the corresponding first semiconductor chip 102 to the temporary bonding film 500, the first carrier substrate 200 is debonded. And after debonding the first carrier substrate 200, the semiconductor wafer 100 is cut along the direction from the second surface 102b to the first surface 102a, targeting the region boundary corresponding to each first semiconductor chip 102 on the semiconductor wafer 100.

[0093] like Figure 3E As shown, after the semiconductor wafer 100 is diced, the temporary bonding film 500 is removed to obtain multiple separate chip packaging assemblies, wherein each chip packaging assembly includes a first semiconductor chip and at least one corresponding second semiconductor chip. Specifically, as... Figure 8 As shown, each of the chip package components 1000 includes a first semiconductor chip 102 and at least one corresponding second semiconductor chip 103. It should be understood that... Figure 8The embodiment shown only illustrates that a second semiconductor chip 103 is formed above the first semiconductor chip 102. In actual use, there can be more than one second semiconductor chip 103, such as 2, 3, 4 or more, which can be flexibly selected according to actual needs.

[0094] For example, such as Figure 3E As shown, the temporary bonding film 500 can be made of a photosensitive material and can be removed by light irradiation. Specifically, the temporary bonding film 500 can be decomposed by laser or ultraviolet light irradiation and then disappear automatically without peeling, making the manufacturing process simple.

[0095] In traditional 3D chip packaging solutions for photonic computing, one or more electronic integrated circuit (IC) chips and one photonic IC chip are typically stacked on a substrate. Since both the IC and photonic IC chips are usually made of silicon substrates, while the substrate is generally made of glass or organic materials, deformation occurs when the photonic IC chip is soldered onto the substrate (the heating during soldering causes deformation of the assembled assembly, leading to unevenness in the soldered area of ​​the upper IC chip). However, to meet the requirements of 3D chip packaging, the photonic IC chips commonly used in the industry are generally quite thin, and the solder joints used in the IC chip soldering process are typically very thin, usually only tens of micrometers. Therefore, the solder joints between the IC and photonic IC chips cannot tolerate this deformation of the basic assembly, often resulting in solder joint breakage or detachment on the IC chip, leading to short circuits or open circuits in the entire semiconductor device. Therefore, in traditional 3D chip stacking packaging, problems such as excessive warpage and low yield are prone to occur during the multi-layer chip stacking process. Furthermore, during the chip stacking and cutting process without plastic encapsulation, there is also a risk of ultra-thin semiconductor wafers breaking due to cutting stress, which can lead to the problem of ultra-thin semiconductor wafers being broken.

[0096] In this embodiment of the invention, since at least one second semiconductor chip corresponding to each first semiconductor chip has a notch to expose the optical coupling region, compared with common technologies, the ratio of the sum of the areas occupied by all the second semiconductor chips corresponding to the first semiconductor chip to the area occupied by the first surface of the first semiconductor chip is increased (for example, in common technologies, the sum of the areas occupied by all the second semiconductor chips corresponding to the first semiconductor chip accounts for less than 70% of the area occupied by the first surface of the first semiconductor chip). This not only enables plastic-free 3D chip stacking packaging, avoiding contamination of the optical coupling region interface by organic materials in the plastic layer, thus ensuring the coupling efficiency of the optical fiber structure using surface coupling in the optical coupling region, but also helps to improve the effective utilization area of ​​the first semiconductor chip and the second semiconductor chip respectively.

[0097] Furthermore, by adopting the technical solution provided in the embodiments of the present invention, the problem of solder joint breakage or desoldering caused by the warping of the first semiconductor chip during the heating process of soldering the second semiconductor chip to the first semiconductor chip can also be avoided, as well as the problem of ultra-thin semiconductor wafer breakage caused during the cutting of unencapsulated wafer-level 3D chips can be prevented.

[0098] Figure 9 This is a schematic diagram of the connection between the chip-level packaging structure and the packaging substrate provided in Embodiment 1 of the present invention.

[0099] like Figure 9 As shown, the method for manufacturing the packaging structure further includes: after obtaining a plurality of separate chip packaging components 1000, mounting each chip packaging component 1000 onto a corresponding packaging substrate 700.

[0100] Furthermore, after at least one chip packaging assembly 1000 having a second conductive bump 1023 is joined to an electrical connection point on the packaging substrate 700, the light guide structure 600 or the laser chip is mounted onto the optical coupling interface 104.

[0101] For example, the light guide structure 600 is a fiber array (FA). Optionally, the light guide structure 600 can be a prism that guides a laser beam to the optical coupling interface 104 by laser integration. Specifically, the laser beam emitted by the laser chip passes through a lens and is incident on the prism, which couples the laser beam into the first semiconductor chip 102 through the optical coupling interface 104.

[0102] Optionally, the laser chip can be directly mounted above the optical coupling interface 104, so that the laser beam emitted by the laser chip is aligned with the optical coupling interface 104, and the laser beam can be directly coupled to the first semiconductor chip 102. Mounting the laser chip above the optical coupling interface 104 can greatly simplify the device structure and improve integration.

[0103] Example 2

[0104] Figure 10 This is a flowchart of a method for manufacturing a packaging structure according to Embodiment 2 of the present invention. The method for manufacturing the packaging structure includes:

[0105] S21, a semiconductor wafer is provided, the semiconductor wafer including a plurality of first semiconductor chips, each first semiconductor chip having a first surface and a second surface opposite to each other, an optical coupling region and a non-optical coupling region surrounding the optical coupling region are disposed on the first surface, and an optical coupling interface is disposed within the optical coupling region;

[0106] S22, for each of the first semiconductor chips, at least one second semiconductor chip corresponding to the first semiconductor chip is provided, and the at least one second semiconductor chip is fixed on the first surface of the first semiconductor chip; wherein, the at least one second semiconductor chip is provided with a virtual area, the virtual area being a region without circuitry; for each second semiconductor chip having the virtual area, one side edge of the virtual area coincides with the first side edge of the second semiconductor chip; and the virtual area of ​​the at least one second semiconductor chip is correspondingly covered over the optical coupling area;

[0107] S23, fabricate a molding layer and expose the molding layer on the side surface of each second semiconductor chip facing away from the first semiconductor chip;

[0108] S24, for each of the first semiconductor chips, remove the virtual area on the at least one second semiconductor chip covering the optical coupling region to form an opening exposing the optical coupling region.

[0109] Figure 11 This is a schematic diagram of a 3D stacked structure of a first semiconductor chip and a corresponding second semiconductor chip with a virtual region according to Embodiment 2 of the present invention. Figure 12 This is a schematic diagram of a 3D stacked structure of a first semiconductor chip and two corresponding second semiconductor chips with virtual regions according to Embodiment 2 of the present invention. Figures 13A-13D This is a schematic diagram of the manufacturing process of a packaging structure according to Embodiment 2 of the present invention. Figures 14A-14FThis is a schematic diagram of the manufacturing process of another packaging structure provided in Embodiment 2 of the present invention. Figure 15 This is a schematic diagram of a chip-level packaging structure provided according to Embodiment 2 of the present invention.

[0110] The following will combine Figures 11-12 , Figures 13A-13D , Figures 14A-14F , Figure 15 The embodiments of the present invention will be described in detail below.

[0111] The difference between this embodiment and the manufacturing method provided in Example 1 is that the manufacturing method in this embodiment involves a molding process. This process involves covering the corresponding optical coupling region 1024 with a second semiconductor chip 103 having a virtual region. The shape of this virtual region is adapted to the shape of the optical coupling region 1024, ensuring that the virtual region precisely covers the optical coupling region 1024. After the molding layer is fabricated, the virtual region is cut to expose the optical coupling region, resulting in better overall stability. Furthermore, during the molding process, because the virtual region precisely covers the optical coupling region 1024, the organic material in the molding layer will not contaminate the interface of the optical coupling region.

[0112] For example, such as Figure 11 As shown, in some embodiments, for each first semiconductor chip 102, a virtual region 800 is provided on a corresponding second semiconductor chip 103. One edge of the virtual region 800 is located in the middle or end of the first side 1031 of the second semiconductor chip 103, and the shape of the virtual region 800 is adapted to the shape of the optical coupling region on the first semiconductor chip 102. Therefore, the size and shape of the virtual region 800 of the corresponding second semiconductor chip 103 can be designed according to the shape of the non-optically coupled region 1025 of each first semiconductor chip 102, so as to make full use of the surface area of ​​the first semiconductor chip 102 and increase the utilization area of ​​all second semiconductor chips 103 corresponding to the first semiconductor chip 102.

[0113] For example, such as Figure 12As shown, in some other embodiments, for each first semiconductor chip 102, a first virtual region 810 and a second virtual region 820 are respectively provided on two second semiconductor chips 103 corresponding to the first semiconductor chip 102. One side edge of the first virtual region 810 and one side edge of the second virtual region 820 are respectively located at the ends of the first side edges 1031 of the two second semiconductor chips 103. One second semiconductor chip 103 with the first virtual region 810 and another second semiconductor chip 103 with the second virtual region 820 are spliced ​​together and covered above the optical coupling region 1024. The shape of the total virtual region formed by the splicing of the first virtual region 810 and the second virtual region 820 is adapted to the shape of the optical coupling region on the first semiconductor chip 102.

[0114] Furthermore, for each of the second semiconductor chips 103 having a virtual region, the first side 1031 of the second semiconductor chip 103 extends in its length or width direction to a side edge close to the first semiconductor chip 102, thereby increasing the area utilization of at least one second semiconductor chip 103 located above the optical coupling region 1024.

[0115] Furthermore, for each of the first semiconductor chips 102, the area occupied by the first surface 102a of the first semiconductor chip 102 is defined as S1, and the sum of the areas occupied by all the second semiconductor chips 103 corresponding to the first semiconductor chip 102 is defined as S2, wherein the ratio between S2 and S1 is greater than 80%. For example, 80% to 90% can prevent warping of the thinned first semiconductor chip 102. Thus, when the semiconductor wafer 100 is used as the lower carrier, a wafer-level 3D chip stacking packaging process can be used to mount the stacked second semiconductor chips 103 onto the corresponding first semiconductor chips 102, and then perform overall dicing. At the same time, the effective utilization area of ​​the corresponding first semiconductor chip 102 and second semiconductor chip 103 is also improved accordingly.

[0116] For example, in this embodiment, such as Figure 13A As shown, a semiconductor wafer 100 is first provided, the semiconductor wafer 100 including a plurality of first semiconductor chips 102, each of the first semiconductor chips 102 having opposing first surfaces 102a and second surfaces 102b.

[0117] Continue to refer to the appendix Figure 4As shown, exemplarily, the first surface 102a of the first semiconductor chip 102 is provided with an optical coupling region 1024 and a non-optical coupling region 1025 surrounding the optical coupling region 1024. An optical coupling interface 104 is provided in the optical coupling region 1024. Light provided by an external light source can be input into the optical coupling interface 104 through a fiber array (FA), for example, by coupling into the first semiconductor chip 102 through a grating coupler in the optical coupling interface 104.

[0118] like Figure 13B As shown, for each first semiconductor chip 102, at least one second semiconductor chip 103 corresponding to the first semiconductor chip 102 is provided, and the at least one second semiconductor chip 103 is fixed on the non-optical coupling region 1025 of the first surface 102a of the first semiconductor chip 102. For example, it can be fixed by means of thermal compress bonding (TCB), reflow soldering, laser bonding, direct metal bonding, or hybrid metal-oxide bonding.

[0119] In this embodiment, at least one second semiconductor chip 103 is provided with a virtual region 800, which is a region without circuitry; for each second semiconductor chip having the virtual region 800, one side edge of the virtual region 800 coincides with the first side edge 1031 of the second semiconductor chip 103; and the virtual region 800 of the at least one second semiconductor chip 103 is correspondingly covered above the optical coupling region 1024.

[0120] Specifically, during the design phase of the wafer used to fabricate multiple second semiconductor chips 103, a dummy region 800 can be set in the area corresponding to the optical coupling region of the first semiconductor chip 102. No valid circuit elements are placed in the area of ​​the dummy region 800; this is commonly referred to in the industry as a dummy region. Generally, multiple dummy regions can be designed on the second semiconductor chip 103 according to the needs of the product application.

[0121] It should be understood that in this embodiment, after the wafer used to fabricate multiple second semiconductor chips 103 undergoes processes such as bump fabrication and wafer testing, and after an NCF (non-conductive adhesive) film is attached to the wafer (if the subsequent 3D stacking interconnection process between the second semiconductor chip 103 and the first semiconductor chip 102 adopts a bumpless bonding method such as direct metal bonding or metal-oxide hybrid bonding, then the above-mentioned bump fabrication and NCF film attachment processes can be omitted), that is, the normal wafer dicing process is completed according to conventional wafer dicing processes to obtain multiple second semiconductor chips 103.

[0122] For example, such as Figure 13C As shown, after stacking at least one second semiconductor chip 103 on the corresponding first semiconductor chip 102, a molding compound 106 is fabricated to improve the overall packaging strength. For each first semiconductor chip 102, the molding compound 106 encapsulates the at least one second semiconductor chip 103 and covers the remaining first surface 102a.

[0123] Next, as Figure 13D As shown, for each of the first semiconductor chips 102, the molding compound 106 located on the at least one second semiconductor chip 103 is removed, so that the molding compound 106 exposes the side surface of each second semiconductor chip 103 facing away from the first semiconductor chip 102. Optionally, while exposing the side surface of each second semiconductor chip 103 facing away from the first semiconductor chip 102, each second semiconductor chip 103 can also be thinned, thereby facilitating heat dissipation of each second semiconductor chip 103.

[0124] Continue to refer to the appendix Figure 13D As shown, after exposing the side surface of each second semiconductor chip 103 facing away from the first semiconductor chip 102, for each first semiconductor chip 102, the virtual area 800 on the at least one second semiconductor chip 103 covering the optical coupling region 1024 is removed. For example, the location of the virtual area 800 of the at least one second semiconductor chip 103 is cut by laser cutting or plasma cutting to remove the virtual area 800, thereby forming an opening that exposes the optical coupling region 1024.

[0125] Optionally, in some embodiments, to avoid the problem of warping easily in the thinned first semiconductor chip 102, which could lead to misalignment or failure of the connection point between the second semiconductor chip 103 and the first semiconductor chip 102, such as... Figure 14A As shown, the semiconductor wafer 100 further includes a first carrier substrate 200, which is temporarily bonded to the second surface 102b of the plurality of first semiconductor chips 102 by bonding adhesive 201 for temporarily supporting the semiconductor wafer 100.

[0126] like Figure 14BAs shown, for each first semiconductor chip 102, at least one second semiconductor chip 103 corresponding to that first semiconductor chip 102 is provided, and the at least one second semiconductor chip 103 is fixed on the non-optically coupled region 1025 of the first surface 102a of the first semiconductor chip 102. Optionally, an underfill or optical coupling adhesive (which can simultaneously enhance the light transmittance properties of the optical coupling region interface) is filled in the gap between each second semiconductor chip 103 and the first surface 102a to further reinforce each second semiconductor chip 103.

[0127] Furthermore, such as Figure 14C As shown, after fixing at least one second semiconductor chip 103 corresponding to each first semiconductor chip 102 onto the first semiconductor chip 102, the method includes: fabricating a molding compound 106 located on a first surface 102a of the first semiconductor chip 102 and covering the at least one second semiconductor chip 103.

[0128] Next, as Figure 14D As shown, for each of the first semiconductor chips 102, the molding compound 106 located on the at least one second semiconductor chip 103 is removed, so that the molding compound 106 exposes the side surface of each second semiconductor chip 103 facing away from the first semiconductor chip 102. Optionally, while exposing the side surface of each second semiconductor chip 103 facing away from the first semiconductor chip 102, each second semiconductor chip 103 can also be thinned, thereby facilitating heat dissipation of each second semiconductor chip 103.

[0129] Continue to refer to the appendix Figure 14D As shown, after exposing the side surface of each second semiconductor chip 103 facing away from the first semiconductor chip 102, for each first semiconductor chip 102, the virtual area 800 on the at least one second semiconductor chip 103 covering the optical coupling region 1024 is removed. For example, the location of the virtual area 800 of the at least one second semiconductor chip 103 is cut by laser cutting or plasma cutting to remove the virtual area 800, thereby forming an opening that exposes the optical coupling region 1024.

[0130] Furthermore, such as Figure 14EAs shown, after removing the virtual region 800 on the at least one second semiconductor chip 103 covering the optical coupling region 1024 for each first semiconductor chip 102, the method further includes: bonding the side surface of each second semiconductor chip 103 away from the corresponding first semiconductor chip 102 to a temporary bonding film 500.

[0131] like Figure 14F As shown, after bonding the side surface of each second semiconductor chip 103 facing away from the corresponding first semiconductor chip 102 to the temporary bonding film 500, the first carrier substrate 200 is debonded. And after debonding the first carrier substrate 200, the semiconductor wafer 100 is cut along the direction from the second surface 102b to the first surface 102a, targeting the region boundary corresponding to each first semiconductor chip 102 on the semiconductor wafer 100.

[0132] After the semiconductor wafer 100 is diced, the temporary bonding film 500 is removed to obtain multiple separate chip packaging assemblies, wherein each chip packaging assembly includes a first semiconductor chip and at least one corresponding second semiconductor chip. Specifically, as shown... Figure 15 As shown, each of the chip package components 1000 includes a first semiconductor chip 102 and at least one corresponding second semiconductor chip 103. It should be understood that... Figure 15 The embodiment shown only illustrates that a second semiconductor chip 103 is formed above the first semiconductor chip 102. In actual use, there can be more than one second semiconductor chip 103, such as 2, 3, 4 or more, which can be flexibly selected according to actual needs.

[0133] Figure 16 This is a schematic diagram of the connection between the chip-level packaging structure and the packaging substrate provided in Embodiment 2 of the present invention.

[0134] like Figure 16 As shown, the method for manufacturing the packaging structure further includes: after obtaining a plurality of separate chip packaging components 1000, mounting each chip packaging component 1000 onto a corresponding packaging substrate 700, and then mounting the light guide structure 600 or the laser chip onto the optical coupling interface 104 of the first semiconductor chip 102.

[0135] According to another aspect of the present invention, a packaging structure is also provided.

[0136] Specifically, in combination Figure 4 and Figure 8As shown, the packaging structure includes: a first semiconductor chip 102 having opposing first and second surfaces, an optical coupling region 1024 and a non-optical coupling region 1025 surrounding the optical coupling region 1024 on the first surface, and an optical coupling interface 104 disposed within the optical coupling region 1024; at least one second semiconductor chip 103 fixed to the non-optical coupling region 1025 on the first surface; wherein, a first side 1031 of the at least one second semiconductor chip 103 is provided with a notch recessed toward the interior of the corresponding second semiconductor chip 103, and for each second semiconductor chip 103 having a notch, the edge of the notch of the second semiconductor chip 103 surrounds the optical coupling region 1024 to expose the optical coupling region 1024.

[0137] For example, combined Figure 6 As shown, in some embodiments, for each first semiconductor chip 102, a notch 400 is provided on the first side 1031 of a second semiconductor chip 103 corresponding to the first semiconductor chip 102. The area where the notch 400 is located is in the middle or end of the first side 1031 of the second semiconductor chip 103, wherein the shape of the notch 400 is adapted to the shape of the optical coupling region 1024.

[0138] For example, combined Figure 8 As shown, in some other embodiments, for each first semiconductor chip 102, a first notch 410 and a second notch 420 are respectively provided on the first side 1031 of two second semiconductor chips 103 corresponding to the first semiconductor chip 102. The regions where the first notch 410 and the second notch 420 are located are respectively located at the ends of the first side 1031 of the two second semiconductor chips 103. The second semiconductor chip 103 with the first notch 410 and the other second semiconductor chip 103 with the second notch 420 are fixed around the optical coupling region 1024 in a splicing manner, and the shape of the total notch formed by the first notch 410 and the second notch 420 after splicing is adapted to the shape of the optical coupling region 1024.

[0139] Furthermore, for each of the second semiconductor chips 103 having the notch, the first side 1031 of the second semiconductor chip 103 extends in its length or width direction to a side edge close to the first semiconductor chip 102, thereby increasing the area utilization of at least one second semiconductor chip 103 located above the optical coupling region 1024.

[0140] Furthermore, for each of the first semiconductor chips 102, the area occupied by the first surface 102a of the first semiconductor chip 102 is defined as S1, and the sum of the areas occupied by all the second semiconductor chips 103 corresponding to the first semiconductor chip 102 is defined as S2, wherein the ratio between S2 and S1 is greater than 80%. For example, 80% to 90% can prevent warping of the thinned first semiconductor chip 102. Simultaneously, the effective utilization area of ​​the corresponding first semiconductor chip 102 and second semiconductor chip 103 is also correspondingly improved.

[0141] According to another aspect of the present invention, a packaging structure is also provided.

[0142] Specifically, in combination Figure 4 and Figure 15 As shown, the packaging structure includes: a first semiconductor chip 102, the first semiconductor chip 102 having opposing first and second surfaces, an optical coupling region 1024 and a non-optical coupling region 1025 surrounding the optical coupling region 1024 are provided on the first surface, and an optical coupling interface 104 is provided in the optical coupling region 1024; at least one second semiconductor chip 103, the at least one second semiconductor chip 103 is fixed on the non-optical coupling region of the first surface, and an opening penetrating the at least one second semiconductor chip 103 is provided in the optical coupling region 1024, and for each second semiconductor chip 103 having the opening, one side edge of the opening coincides with the first side edge 1031 of the second semiconductor chip 103; and a molding compound 106, the molding compound 106 being located on the first surface and covering the side edge of the at least one second semiconductor chip 103, the opening not being filled or covered by the molding compound 106.

[0143] Furthermore, for each of the second semiconductor chips 103 having the opening, the first side 1031 of the second semiconductor chip 103 extends in its length or width direction to a side edge close to the first semiconductor chip 102, thereby increasing the area utilization of at least one second semiconductor chip 103 located above the optical coupling region 1024.

[0144] Furthermore, for each of the first semiconductor chips 102, the area occupied by the first surface 102a of the first semiconductor chip 102 is defined as S1, and the sum of the areas occupied by all the second semiconductor chips 103 corresponding to the first semiconductor chip 102 is defined as S2, wherein the ratio between S2 and S1 is greater than 80%. For example, 80% to 90% can prevent warping of the thinned first semiconductor chip 102. Simultaneously, the effective utilization area of ​​the corresponding first semiconductor chip 102 and second semiconductor chip 103 is also correspondingly improved.

[0145] As can be seen from the above, the packaging structure and manufacturing method provided by the embodiments of the present invention, since for each first semiconductor chip, at least one second semiconductor chip corresponding to the first semiconductor chip has a notch or opening to expose the optical coupling region, thus, compared with common technologies, increases the ratio of the sum of the areas occupied by all second semiconductor chips corresponding to the first semiconductor chip to the area occupied by the first surface of the first semiconductor chip. At the same time, it is also beneficial to improve the effective utilization area of ​​the first semiconductor chip and the second semiconductor chip respectively, and also avoids the problem of contamination of the optical coupling region interface by organic materials in the molding layer.

[0146] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of the present invention. All equivalent variations and modifications made in accordance with the shape, structure, features and spirit described in the claims of the present invention should be included within the scope of the claims of the present invention.

Claims

1. A method for manufacturing an encapsulation structure, characterized in that, The method includes: A semiconductor wafer is provided, the semiconductor wafer comprising a plurality of first semiconductor chips, each first semiconductor chip having opposing first and second surfaces, the first surface having an optical coupling region and a non-optical coupling region surrounding the optical coupling region, the optical coupling region having an optical coupling interface disposed therein; For each of the first semiconductor chips, at least one second semiconductor chip corresponding to the first semiconductor chip is provided, and the at least one second semiconductor chip is fixed on the non-optically coupled region of the first surface of the first semiconductor chip; Before fixing at least one second semiconductor chip corresponding to each first semiconductor chip onto the first semiconductor chip, a first side of the at least one second semiconductor chip is cut, and a notch is formed along the first side towards the interior of the corresponding second semiconductor chip after cutting, the length of the notch being less than the length of the first side. Specifically, for each of the second semiconductor chips having the notch, the edge of the notch of the second semiconductor chip is arranged around the optical coupling region to expose the optical coupling region.

2. The method for manufacturing the packaging structure as described in claim 1, characterized in that, For each first semiconductor chip, the first side of a second semiconductor chip corresponding to the first semiconductor chip is cut, and after cutting, a notch is formed that is recessed into the second semiconductor chip along the first side. The area where the notch is located is in the middle or end of the first side of the second semiconductor chip, and the shape of the notch is adapted to the shape of the optical coupling area.

3. The method for manufacturing the packaging structure as described in claim 1, characterized in that, For each first semiconductor chip, the first side of each of the two second semiconductor chips corresponding to the first semiconductor chip is cut, and a first notch and a second notch are formed respectively along the first side towards the interior of the two corresponding semiconductor chips after cutting. The regions where the first notch and the second notch are located are respectively located at the ends of the first side of the two corresponding second semiconductor chips. One of the second semiconductor chips with the first notch and the other of the second semiconductor chips with the second notch are fixed around the optical coupling area by splicing, and the shape of the total notch formed by the splicing of the first notch and the second notch is adapted to the shape of the optical coupling area.

4. The method for manufacturing the packaging structure as described in any one of claims 1 to 3, characterized in that, For each of the second semiconductor chips having the notch, the first side of the second semiconductor chip extends in its length or width direction to a side edge close to the first semiconductor chip.

5. The method for manufacturing the packaging structure as described in claim 4, characterized in that, For each of the first semiconductor chips, the area occupied by the first surface of the first semiconductor chip is defined as S1, and the sum of the areas occupied by all the second semiconductor chips corresponding to the first semiconductor chip is defined as S2, wherein the ratio between S2 and S1 is greater than 80%.

6. The method for manufacturing the packaging structure as described in claim 1, characterized in that, The semiconductor wafer includes: A first carrier substrate is temporarily bonded to the second surface of the plurality of first semiconductor chips to temporarily support the semiconductor wafers.

7. The method for manufacturing the packaging structure as described in claim 6, characterized in that, After fixing at least one second semiconductor chip corresponding to each first semiconductor chip onto the first semiconductor chip, the method further includes: Each second semiconductor chip is bonded to a temporary bonding film on the side of its surface facing away from the corresponding first semiconductor chip, and then the first carrier substrate is debonded.

8. The method for manufacturing the packaging structure as described in claim 7, characterized in that, The method further includes: After debonding the first carrier substrate, the semiconductor wafer is cut along the direction from the second surface to the first surface, for each of the first semiconductor chips corresponding to the region boundary on the semiconductor wafer; and, The temporary bonding film is removed to obtain a plurality of separate chip package components, wherein each chip package component includes a first semiconductor chip and at least one corresponding second semiconductor chip.

9. The method for manufacturing the packaging structure as described in claim 8, characterized in that, The temporary bonding film includes a photosensitive material, which is removed by light irradiation.

10. The method for manufacturing the packaging structure as described in claim 8, characterized in that, The method further includes: After obtaining multiple separate chip packaging components, each chip packaging component is mounted onto a corresponding packaging substrate, and then a light guide structure or laser chip is mounted onto the optical coupling interface of the first semiconductor chip.

11. A method for manufacturing an encapsulation structure, characterized in that, The method includes: A semiconductor wafer is provided, the semiconductor wafer comprising a plurality of first semiconductor chips, each first semiconductor chip having opposing first and second surfaces, the first surface having an optical coupling region and a non-optical coupling region surrounding the optical coupling region, the optical coupling region having an optical coupling interface disposed therein; For each first semiconductor chip, at least one second semiconductor chip corresponding to the first semiconductor chip is provided, and the at least one second semiconductor chip is fixed on the first surface of the first semiconductor chip; wherein, the at least one second semiconductor chip is provided with a virtual area, the virtual area being a region without circuitry; for each second semiconductor chip having the virtual area, one side edge of the virtual area coincides with the first side edge of the second semiconductor chip; and the virtual area of ​​the at least one second semiconductor chip is correspondingly covered over the optical coupling area; A molding layer is fabricated, and the molding layer is exposed on the side surface of each of the second semiconductor chips facing away from the first semiconductor chip; For each of the first semiconductor chips, the virtual area on the at least one second semiconductor chip covering the optical coupling region is removed to form an opening exposing the optical coupling region.

12. The method for manufacturing the packaging structure as described in claim 11, characterized in that, For each of the first semiconductor chips, a virtual region is provided on a second semiconductor chip corresponding to the first semiconductor chip. One edge of the virtual region is located in the middle or end of the first side of the second semiconductor chip, and the shape of the virtual region is adapted to the shape of the optical coupling region.

13. The method for manufacturing the packaging structure as described in claim 11, characterized in that, For each of the first semiconductor chips, a first virtual region and a second virtual region are respectively provided on two second semiconductor chips corresponding to the first semiconductor chip. One side edge of the first virtual region and one side edge of the second virtual region are respectively located at the ends of the first side edges of the two second semiconductor chips. One of the second semiconductor chips with the first virtual region and another of the second semiconductor chips with the second virtual region are spliced ​​together to cover the optical coupling region. The shape of the total virtual region formed by the splicing of the first virtual region and the second virtual region is adapted to the shape of the optical coupling region.

14. The method for manufacturing the packaging structure according to any one of claims 11 to 13, characterized in that, For each of the second semiconductor chips having the virtual region, the first side of the second semiconductor chip extends along its length or width to a side edge close to the first semiconductor chip.

15. The method for manufacturing the packaging structure as described in claim 14, characterized in that... For each of the first semiconductor chips, the area occupied by the first surface of the first semiconductor chip is defined as S1, and the sum of the areas occupied by all the second semiconductor chips corresponding to the first semiconductor chip is defined as S2, wherein the ratio between S2 and S1 is greater than 80%.

16. The method for manufacturing the packaging structure as described in claim 11, characterized in that, The method for removing the virtual region on the at least one second semiconductor chip covering the optical coupling region for each of the first semiconductor chips includes: The virtual region of the at least one second semiconductor chip is cut at the location of the virtual region using laser cutting or plasma cutting to remove the virtual region.

17. The method for manufacturing the packaging structure as described in claim 11, characterized in that, The semiconductor wafer includes: A first carrier substrate is temporarily bonded to the second surface of the plurality of first semiconductor chips to temporarily support the semiconductor wafers.

18. The method for manufacturing the packaging structure as described in claim 17, characterized in that, After removing the virtual region on the at least one second semiconductor chip covering the optical coupling region for each of the first semiconductor chips, the method further includes: Each second semiconductor chip is bonded to a temporary bonding film on the side of its surface facing away from the corresponding first semiconductor chip, and then the first carrier substrate is debonded.

19. The method for manufacturing the packaging structure as described in claim 18, characterized in that, The method further includes: After debonding the first carrier substrate, the semiconductor wafer is cut along the direction from the second surface to the first surface, for each of the first semiconductor chips corresponding to the region boundary on the semiconductor wafer; and, The temporary bonding film is removed to obtain a plurality of separate chip package components, wherein each chip package component includes a first semiconductor chip and at least one corresponding second semiconductor chip.

20. The method for manufacturing the packaging structure as described in claim 19, characterized in that, The method further includes: After obtaining multiple separate chip packaging components, each chip packaging component is mounted onto a corresponding packaging substrate, and then a light guide structure or laser chip is mounted onto the optical coupling interface of the first semiconductor chip.

21. A packaging structure, characterized in that, include: A first semiconductor chip has a first surface and a second surface opposite to each other. An optical coupling region and a non-optical coupling region surrounding the optical coupling region are provided on the first surface. An optical coupling interface is provided within the optical coupling region. At least one second semiconductor chip, the at least one second semiconductor chip being fixed on the non-optically coupled region of the first surface; The first side of the at least one second semiconductor chip is provided with a notch that is recessed toward the interior of the corresponding second semiconductor chip, and for each second semiconductor chip with the notch, the edge of the notch surrounds the optical coupling region to expose the optical coupling region.

22. The packaging structure as described in claim 21, characterized in that, For each of the first semiconductor chips, a notch is provided on the first side of a second semiconductor chip corresponding to the first semiconductor chip. The area where the notch is located is in the middle or at the end of the first side of the second semiconductor chip, wherein the shape of the notch is adapted to the shape of the optical coupling region.

23. The packaging structure as described in claim 21, characterized in that, For each of the first semiconductor chips, a first notch and a second notch are respectively formed on the first side of the two second semiconductor chips corresponding to the first semiconductor chip. The regions where the first notch and the second notch are located are respectively located at the ends of the first side of the two second semiconductor chips. The second semiconductor chip with the first notch and the other second semiconductor chip with the second notch are fixed around the optical coupling area by splicing. The shape of the total notch formed by the splicing of the first notch and the second notch is adapted to the shape of the optical coupling area.

24. The packaging structure according to any one of claims 21 to 23, characterized in that, For each of the second semiconductor chips having the notch, the first side of the second semiconductor chip extends in its length or width direction to a side edge close to the first semiconductor chip.

25. The packaging structure as described in claim 24, characterized in that, For each of the first semiconductor chips, the area occupied by the first surface of the first semiconductor chip is defined as S1, and the sum of the areas occupied by all the second semiconductor chips corresponding to the first semiconductor chip is defined as S2, wherein the ratio between S2 and S1 is greater than 80%.

26. A packaging structure, characterized in that, include: A first semiconductor chip has a first surface and a second surface opposite to each other. An optical coupling region and a non-optical coupling region surrounding the optical coupling region are provided on the first surface. An optical coupling interface is provided within the optical coupling region. At least one second semiconductor chip is fixed on the non-optically coupled region of the first surface, and an opening is provided in the optically coupled region to penetrate the at least one second semiconductor chip. For each second semiconductor chip having the opening, one side edge of the opening coincides with the first side edge of the second semiconductor chip. A molding compound is located on the first surface and on the side of the at least one second semiconductor chip, and the opening is not filled or covered by the molding compound.

27. The packaging structure as described in claim 26, characterized in that, For each of the second semiconductor chips having the opening, the first side of the second semiconductor chip extends along its length or width to a side edge close to the first semiconductor chip.

28. The packaging structure as described in claim 27, characterized in that, For each of the first semiconductor chips, the area occupied by the first surface of the first semiconductor chip is defined as S1, and the sum of the areas occupied by all the second semiconductor chips corresponding to the first semiconductor chip is defined as S2, wherein the ratio between S2 and S1 is greater than 80%.

Images