An integrated inverter and its manufacturing method
By setting up a multi-layer conductive structure and gate structure on the substrate, combined with a P-type doping layer, high-integration integration of enhanced and depletion transistors is achieved, solving the problems of device complexity and cost in the prior art, and improving the overall performance of the device.
Patent Information
- Application Number
- CN202211066704.X
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-08-30
- Publication Date
- 2025-08-19
- Estimated Expiration
- 2042-08-30
AI Technical Summary
The prior art is difficult to effectively integrate enhanced and depletion transistors, resulting in increased device complexity and cost, and it is difficult to achieve more functions and device integration in a single chip.
By providing first and second regions with different thicknesses on the substrate, and growing a multi-layer conductive structure layer and gate structure thereon, forming a heterojunction, and combining the P-type doping layer to improve the integration and polarization strength of the device, effective integration of enhanced and depletion transistors is achieved.
Achieve high-integration transistor integration, improves the integrity and saturation current density of the device, reduces the on-resistance, and improves the voltage withstandness and stability of the device.
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Figure CN116031258B_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of semiconductor technology, and in particular to an integrated inverter and a method for preparing the integrated inverter. Background Art
[0002] Gallium nitride (GaN), as a third-generation wide-bandgap semiconductor material, has high electron mobility, high thermal conductivity, and high breakdown field strength, and has a wide range of application scenarios and advantages. This makes GaN-based high electron mobility transistors (HEMTs) have high saturation electron velocity, faster switching speed, lower on-resistance, higher operating temperature, etc., and are widely used in fast charging, data centers, electric vehicles and other fields.
[0003] Currently, there are three ways to realize enhancement-mode GaN-based devices: P-GaN gate, groove gate, and cascode structure. Among them, cascode-based GaN HEMT is widely used in the market. This method of cascading GaN HEMT and Si MOSFET to form an enhancement-mode device reduces production cost and complexity, while also avoiding the complex design of gate drive circuits. At the same time, in existing technology devices, there is a trend to integrate more functions and more devices (such as transistors) into a single chip to create smaller, smarter, and more powerful systems. Therefore, as a key enabling technology for advanced logic, analog, and digital circuits, the combination and effective integration of enhancement-mode and depletion-mode transistors has become an urgent problem to be solved. Summary of the Invention
[0004] Therefore, the technical problem to be solved by the present invention is to provide an integrated inverter and a preparation method thereof, so as to realize the combination and effective integration of enhancement mode and depletion mode transistors.
[0005] To this end, in a first aspect, the present invention provides an integrated inverter, comprising:
[0006] A substrate having a first region and a second region; the thickness of the substrate in the first region is greater than the thickness in the second region;
[0007] A first gate, a first drain and a first source are provided on the substrate in the first region, the first gate is located between the first drain and the first source, and a first gate dielectric layer is provided between the first gate and the substrate;
[0008] a buffer structure layer, disposed on the substrate in the second region;
[0009] The first conductive structure layer and the second conductive structure layer are sequentially arranged on the buffer structure layer, and the first conductive structure layer and the second conductive structure layer each have a first sub-region and a second sub-region spaced apart, and a heterojunction is formed between the first conductive structure layer and the second conductive structure layer in the first sub-region;
[0010] A second gate, a second drain and a second source are provided on the second conductive structure layer of the first sub-region, and the second gate is located between the second drain and the second source;
[0011] a third conductive structure layer, disposed on the second conductive structure layer in the second sub-region;
[0012] A third gate, a third drain and a third source are provided on the third conductive structure layer, the third gate is located between the third drain and the third source, and a second gate dielectric layer is provided between the third gate and the third conductive structure layer;
[0013] The first source and the second gate, as well as the first drain and the second source are electrically connected. The first gate and the third gate are electrically connected to form an input end of the integrated inverter. The second drain and the third source are electrically connected to form an output end of the integrated inverter. The third drain is a driving power connection end of the integrated inverter.
[0014] Furthermore, the integrated inverter further comprises:
[0015] The fourth conductive structure layer is arranged between the third drain and the third conductive structure layer, and between the third source and the third conductive structure layer; the third conductive structure layer and the fourth conductive structure layer are both P-type doped layers, and the P-type doping concentration in the fourth conductive structure layer is higher than the P-type doping concentration in the third conductive structure layer.
[0016] Furthermore, the second conductive structure layer is an AlGaN layer, the third conductive structure layer is a P-AlGaN layer, and the fourth conductive structure layer is a P + -AlGaN layer.
[0017] Furthermore, the first conductive structure layer is a C-doped GaN layer.
[0018] Furthermore, the buffer structure layer includes a transition layer and a buffer layer, the transition layer is arranged on the substrate of the second region, and the buffer layer is arranged on the transition layer; the buffer layer is a GaN layer.
[0019] Furthermore, a first spacing groove is provided between the substrate in the first region and the buffer structure layer in the second region, and a second spacing groove is provided between the first conductive structure layer and the second conductive structure layer.
[0020] In a second aspect, the present invention provides a method for preparing an integrated inverter, comprising the following steps:
[0021] S1: Obtain a substrate; the substrate has a first region and a second region, and the thickness of the substrate in the first region is greater than the thickness of the substrate in the second region; the substrate is obtained by thinning a portion corresponding to the second region on an initial substrate;
[0022] S2: growing a buffer structure layer on the substrate in the second region;
[0023] S3: sequentially growing a first conductive structure layer and a second conductive structure layer on the buffer structure layer; the first conductive structure layer and the second conductive structure layer both have a first sub-region and a second sub-region spaced apart, and a heterojunction is formed between the first conductive structure layer and the second conductive structure layer in the first sub-region;
[0024] S4: growing a third conductive structure layer on the second conductive structure layer in the second sub-region;
[0025] S5: growing a fourth conductive structure layer at a position corresponding to the source electrode and a position corresponding to the drain electrode on the third conductive structure layer;
[0026] S6: growing a first drain electrode and a first source electrode on the substrate in the first region;
[0027] S7: growing a second gate, a second drain, and a second source on the second conductive structure layer in the first sub-region;
[0028] S8: growing a third source electrode and a third drain electrode on the fourth conductive structure layer;
[0029] S9: sequentially growing a first gate dielectric layer and a first gate at positions corresponding to the gate on the substrate in the first region, and sequentially growing a second gate dielectric layer and a third gate at positions corresponding to the gate on the third conductive structure layer.
[0030] Furthermore, a first spacing groove is provided between the buffer structure layer and the substrate of the first region; and a second spacing groove is formed by etching the first conductive structure layer and the second conductive structure layer between the first sub-region and the second sub-region.
[0031] Furthermore, step S9 specifically includes the following steps:
[0032] S91: growing an oxide dielectric layer on the surface of the device prepared in step S8;
[0033] S92: growing a first gate at a position corresponding to the gate on the oxide dielectric layer in the first region, and growing a third gate at a position corresponding to the gate on the oxide dielectric layer in the second sub-region;
[0034] S93: Etching the oxide dielectric layer on the first drain, the first source, the second gate, the second drain, the second source, the third drain and the third source; the oxide dielectric layer under the first gate is the first gate dielectric layer, and the oxide dielectric layer under the third gate is the second gate dielectric layer.
[0035] The technical solution provided by the present invention has the following advantages:
[0036] 1. The integrated inverter provided by the present invention realizes the effective integration of the first enhancement-mode MOS transistor (device corresponding to the first region), the depletion-mode HEMT (device corresponding to the first sub-region), and the second enhancement-mode MOS transistor (device corresponding to the second sub-region) on the same substrate, thereby improving the integration and integrity of the device.
[0037] 2. The integrated inverter provided by the present invention, by providing a fourth conductive structure layer under the third drain and the third source, while forming an ohmic contact with the third drain and the third source, by providing the fourth conductive structure layer as a P-type doped layer like the third conductive structure layer, and the P-type doping concentration of the fourth conductive structure layer is higher than the P-type doping concentration in the third conductive structure layer, can improve the polarization strength of the second enhancement-mode MOS transistor (the device corresponding to the second sub-region, which is specifically a P-channel enhancement-mode MOS transistor in this case), thereby reducing the activation energy of the P-type impurities therein, increasing the hole concentration, and thereby increasing the saturation current density of the integrated inverter and reducing the on-resistance.
[0038] 3. The integrated inverter provided by the present invention is configured such that the second conductive structure layer is an AlGaN layer, the third conductive structure layer is a P-AlGaN layer, and the fourth conductive structure layer is a P + -AlGaN layer, which can give full play to the performance of AlGaN to improve the voltage resistance of the device and enable the second enhancement mode MOS tube (the device corresponding to the second sub-region, which is specifically a P-type GaN-based enhancement MOS tube) to form a P + -AlGaN / P-ALGaN / AlGaN structure, further improving the hole density of the second enhancement-mode MOS transistor, thereby improving the saturation current density of the integrated inverter.
[0039] 4. The integrated inverter provided by the present invention sets the first conductive structure layer as a C-doped GaN layer, so that a large number of C atoms introduced therein become acceptor impurities, thereby achieving self-compensation and further realizing the role of a high-resistance layer. It can reduce the influence of impurity scattering in the buffer layer below it on the two-dimensional electron gas mobility, and reduce the influence of impurity defects in the buffer layer on the electrical performance of the integrated inverter.
[0040] 5. The method for preparing an integrated inverter provided by the present invention realizes the preparation of a highly integrated integrated inverter with relatively simple steps. BRIEF DESCRIPTION OF THE DRAWINGS
[0041] In order to more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the specific embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.
[0042] Figure 1 Schematic diagram of the integrated inverter provided in Example 1 of the present invention;
[0043] Figure 2 A schematic structural diagram of an integrated inverter provided in Example 1 of the present invention;
[0044] Figure 3 A flow chart of a method for preparing an integrated inverter provided in Example 2 of the present invention;
[0045] Figure 4A This is a schematic structural diagram of the device prepared in step S8;
[0046] Figure 4B Schematic diagram of the structure of the device prepared by S91;
[0047] Figure 4C Schematic diagram of the structure of the device prepared by S92;
[0048] Figure 4D Schematic diagram of the structure of the device prepared by S93;
[0049] Description of reference numerals:
[0050] 1-substrate; 2G-first gate; 2D-first drain; 2S-first source; 3-first gate dielectric layer; 4-buffer structure layer; 4a-transition layer; 4b-buffer layer; 5-first conductive structure layer; 6-second conductive structure layer; 7G-second gate; 7D-second drain; 7S-second source; 8-third conductive structure layer; 9G-third gate; 9D-third drain; 9S-third source; 10-second gate dielectric layer; 11-fourth conductive structure layer; 12-first spacing groove; 13-second spacing groove; 14-oxide dielectric layer; 16-nitride passivation layer; 17-extension electrode. DETAILED DESCRIPTION
[0051] The technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention without making any creative efforts shall fall within the scope of protection of the present invention.
[0052] In the description of the present invention, it should be noted that the terms "upper" and "lower" and other terms indicating orientations or positional relationships are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate and simplify the description of the present invention. They are not intended to indicate or imply that the devices or components referred to must have, be constructed, or operate in a specific orientation, and therefore should not be construed as limitations on the present invention. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.
[0053] Example 1
[0054] This embodiment provides an integrated inverter, the principle diagram of which is shown in FIG. Figure 1 As shown. Figure 2 As shown, the integrated inverter includes: a substrate 1, a buffer structure layer 4, a first conductive structure layer 5, a second conductive structure layer 6, a third conductive structure layer 8, a first gate dielectric layer 3, a second gate dielectric layer 10, a first gate 2G, a first drain 2D, a first source 2S, a second gate 7G, a second drain 7D, a second source 7S, a third gate 9G, a third drain 9D and a third source 9S.
[0055] Among them, such as Figure 2 As shown, substrate 1 has a first region and a second region, and the thickness of substrate 1 in the first region is greater than that in the second region. Specifically, substrate 1 can be a Si substrate or a SiC substrate, etc., and can be obtained by etching and thinning the corresponding portion of the second region after obtaining an initial substrate. For example, the thickness of substrate 1 in the second region can be 400 μm.
[0056] Among them, such as Figure 2 As shown, the first gate dielectric layer 3 is arranged at the gate corresponding position on the substrate 1 in the first region (that is, between the first source 2S and the first drain 2D), the first gate 2G is arranged on the first gate dielectric layer 3, and the first source 2S and the first drain 2D are arranged on the substrate 1 in the first region.
[0057] Specifically, a first source 2S and a first drain 2D can be first grown on the substrate 1 in the first region. Then, an oxide dielectric layer or a nitride dielectric layer (hereinafter described using the oxide dielectric layer as an example) can be grown on the entire surface of the device in the first region. Then, a first gate 2G can be grown at a position corresponding to the gate on the oxide dielectric layer. Finally, the oxide dielectric layer on the surface electrically connected to the first source 2S and the first drain 2D can be etched and removed to complete the growth of the first gate dielectric layer 3 and the first gate 2G. In this case, the first gate dielectric layer 3 is not only located below the first gate 2G, but also extends to all surfaces of the device in the first region (the first enhancement-mode MOS transistor) except for the surface electrically connected to the first source 2S and the first drain 2D, which can improve device stability to a certain extent. Specifically, the first gate dielectric layer 3 can be an Al2O3 layer, an HfO2 layer, or a SiN layer, etc.
[0058] Among them, such as Figure 2 As shown, the buffer structure layer 4 is provided on the substrate 1 in the second region. Specifically, the buffer structure layer 4 may include one or more substructure layers to better balance the stress within the device and improve the film quality of the conductive structure layer within the device. Figure 2 As shown, the buffer structure layer 4 may include a transition layer 4a and a buffer layer 4b. The transition layer 4a is disposed on the substrate 1 in the second region, and the buffer layer 4b is disposed on the transition layer 4a. For example, if the devices in the second region (the depletion-mode HEMT corresponding to the first sub-region and the second enhancement-mode MOS transistor corresponding to the second sub-region) are both GaN devices, the transition layer 4a may be an AlN layer, and the buffer layer 4b may be a GaN layer. For example, the thickness of the AlN layer may be 42 nm, and the thickness of the GaN layer may be 250 nm.
[0059] Specifically, in order to achieve an effective spacing between the devices in the first region and the devices in the second region, as shown in FIG. Figure 2 As shown, when the buffer structure layer 4 is epitaxially grown, a first spacing groove 12 may be left between the buffer structure layer 4 and the substrate 1 in the first region.
[0060] Among them, such as Figure 2As shown, the first conductive structure layer 5 and the second conductive structure layer 6 are sequentially arranged on the buffer structure layer 4, and the first conductive structure layer 5 and the second conductive structure layer 6 have a first sub-region and a second sub-region separated therefrom, and a heterojunction is formed between the first conductive structure layer 5 and the second conductive structure layer 6 in the first sub-region. Specifically, the gap between the first sub-region and the second sub-region can be formed by first epitaxially growing the first conductive structure layer 5 and the second conductive structure layer 6 on the buffer structure layer 4 as a whole, and then etching the middle of the first conductive structure layer 5 and the second conductive structure layer 6 to form a second separation groove 13. Specifically, still taking the example that the devices in the first sub-region and the devices in the second sub-region are both GaN devices, the first conductive structure layer 5 can be set to a GaN layer and the second conductive structure layer 6 can be set to an AlGaN layer.
[0061] Specifically, to prevent the impact of impurity scattering in the buffer structure layer 4 on the two-dimensional electron gas mobility, thereby affecting the electrical performance of the device, the first conductive structure layer 5 can also be set as a C-doped GaN layer. The large number of C atoms introduced into the first conductive structure layer 5 become acceptor impurities, achieving self-compensation, thereby achieving the function of a high-resistance layer and reducing the impact of impurity scattering in the buffer structure layer 4 below on the two-dimensional electron gas mobility. By way of example, the thickness of the C-doped GaN layer can be set to 1.8μm, and the thickness of the AlGaN layer can be set to 21nm.
[0062] Among them, such as Figure 2 As shown, the second gate 7G, the second drain 7D and the second source 7S are all arranged on the second conductive structure layer 6 of the first sub-region, and the second gate 7G is located between the second drain 7D and the second source 7S.
[0063] Among them, such as Figure 2 As shown, the third conductive structure layer 8 is disposed on the second conductive structure layer 6 of the second sub-region. Specifically, taking the example of the devices in the first sub-region and the devices in the second sub-region being both GaN devices, the third conductive structure layer 8 can be configured as an intentionally doped AlGaN layer, such as a Mg-doped P-AlGaN layer. Accordingly, in this case, the device in the second sub-region is a P-channel device. Exemplarily, the thickness of the P-AlGaN layer can be set to 50 nm.
[0064] Among them, such as Figure 2 As shown, the second gate dielectric layer 10 is arranged at the gate corresponding position on the third conductive structure layer 8 (that is, between the third source 9S and the third drain 9D), the third gate 9G is arranged on the second gate dielectric layer 10, the third source 9S and the third drain 9D are arranged on the third conductive structure layer 8, and the third gate 9G is located between the third source 9S and the third drain 9D.
[0065] Similarly, a third source 9S and a third drain 9D can be first grown on the third conductive structure layer 8, and then an oxide dielectric layer or a nitride dielectric layer can be grown on the entire surface of the device in the second sub-region (the oxide dielectric layer is used as an example in the following description). Then, a third gate 9G can be grown at a position corresponding to the gate on the oxide dielectric layer, and finally the oxide dielectric layer 14 on the electrical connection surface of the third source 9S and the third drain 9D can be etched and removed to complete the growth of the second gate dielectric layer 10 and the third gate 9G. In this case, the second gate dielectric layer 10 is not only located below the third gate 9G, but also extends to all surfaces of the device in the second sub-region (the second enhancement-mode MOS transistor) except for the electrical connection surface of the third source 9S and the third drain 9D, which can improve the stability of the device to a certain extent. Specifically, the second gate dielectric layer 10 can be an Al2O3 layer, an HfO2 layer, or a SiN layer.
[0066] Specifically, the first gate dielectric layer 3 and the second gate dielectric layer 10 can be structural layers of the same material, and the first gate dielectric layer 3 and the second gate dielectric layer 10 can be grown simultaneously. At this time, after the growth of the first source 2S, the first drain 2D, the second source 7S, the second drain 7D, the second gate 7G, the third source 9S and the third drain 9D are completed, an oxide dielectric layer or a nitride dielectric layer can be grown on the surface of the entire device (the following description is based on the oxide dielectric layer as an example), and then the first gate 2G and the third gate 9G are grown at the corresponding positions of the gates in the first region and the second sub-region, respectively, and finally the first source 2S is etched. , the oxide dielectric layer on the electrically connected surfaces of the first drain 2D, the second source 7S, the second drain 7D, the second gate 7G, the third source 9S and the third drain 9D, and the growth of the first gate dielectric layer 3, the first gate 2G, the second gate dielectric layer 10 and the third gate 9G are completed. At this time, all surfaces of the integrated inverter except the electrically connected surfaces of the first source 2S, the first drain 2D, the second source 7S, the second drain 7D, the second gate 7G, the third source 9S and the third drain 9D (including the walls of the first isolation groove 12 and the second isolation groove 13) have the oxide dielectric layer, which can improve the stability of the device to a certain extent.
[0067] Among them, such as Figure 2 As shown, the first source 2S and the second gate 7G, as well as the first drain 2D and the second source 7S are electrically connected, the first gate 2G and the third gate 9G are electrically connected to form the input end of the integrated inverter, the second drain 7D and the third source 9S are electrically connected to form the output end of the integrated inverter; the third drain 9D is the driving power connection end of the integrated inverter, and the first source 2S is the ground end. Specifically, as Figure 2 As shown, the electrical connection between the electrodes can be achieved through metal wire interconnection.
[0068] The integrated inverter in this embodiment realizes the effective integration of the first enhancement-mode MOS transistor (device corresponding to the first region), the depletion-mode HEMT (device corresponding to the first sub-region), and the second enhancement-mode MOS transistor (device corresponding to the second sub-region) on the same substrate, thereby improving the integration and integrity of the device.
[0069] As another implementation of this embodiment, Figure 2 As shown, when the third conductive structure layer 8 is a P-type doped layer, a fourth conductive structure layer 11 may be further provided between the third drain 9D and the third conductive structure layer 8, and between the third source 9S and the third conductive structure layer 8, and the fourth conductive structure layer 11 is also provided as a P-type doped layer, and its P-type doping concentration is higher than the P-type doping concentration in the third conductive structure layer 8. Specifically, when the third conductive structure layer 8 is a P-AlGaN layer, the fourth conductive structure layer 11 is a P-AlGaN layer. + -AlGaN layer, at this time, P is formed in the second enhancement mode MOS tube + -AlGaN / P-ALGaN / AlGaN structure, further improves the hole density of the second enhancement mode MOS tube, thereby improving the saturation current density of the integrated inverter. + -The thickness of the AlGaN layer is 40 nm.
[0070] Specifically, a protective dielectric layer (such as SiO2) can be first deposited and grown on the third conductive structure layer 8, and then photoresist is spin-coated on the surface of the protective dielectric layer. The visible area is exposed and developed using a photolithography process, and then the protective dielectric layer is etched to remove the protective dielectric layer except for the position corresponding to the gate. The photoresist on the surface of the remaining protective dielectric layer is then removed, and the fourth conductive structure layer 11 is grown in the area without the protective dielectric layer. Finally, BOE is used to remove the remaining protective dielectric layer to achieve the growth of the fourth conductive structure layer 11.
[0071] As another implementation of this embodiment, Figure 2 As shown, a nitride passivation layer 16 can also be deposited on the entire device surface of the integrated inverter in the above embodiment to enhance electrical isolation between electrodes and improve device reliability. Of course, in this case, to ensure electrical connection of the integrated inverter, it is necessary to open holes in the nitride passivation layer 16 above the electrical connection surfaces of each electrode. Metal can also be sputtered in these holes to form extended electrodes 17 for subsequent metal line interconnection.
[0072] Example 2
[0073] This embodiment provides a method for preparing an integrated inverter, which is the method for preparing the integrated inverter in the above embodiment 1. Therefore, its specific content can be understood by referring to the content in the above embodiment 1, and will not be repeated in this embodiment. Figure 3As shown, the method includes the following steps:
[0074] S1: Obtain substrate 1.
[0075] Specifically, the substrate 1 has a first region and a second region, and the thickness of the substrate 1 in the first region is greater than the thickness in the second region. Specifically, the substrate 1 is obtained by thinning a portion corresponding to the second region on an initial substrate.
[0076] S2: growing a buffer structure layer 4 on the substrate 1 in the second region. Specifically, a first spacing groove 12 is provided between the buffer structure layer 4 and the substrate 1 in the first region, and as described in embodiment 1, the buffer structure layer may include a transition layer 4a and a buffer layer 4b.
[0077] S3: A first conductive structure layer 5 and a second conductive structure layer 6 are sequentially grown on the buffer structure layer 4. Specifically, the first conductive structure layer 5 and the second conductive structure layer 6 each have a first sub-region and a second sub-region separated therefrom, and a heterojunction is formed between the first conductive structure layer 5 and the second conductive structure layer 6 in the first sub-region. Specifically, the first conductive structure layer 5 and the second conductive structure layer 6 are etched between the first sub-region and the second sub-region to form a second separation groove 13.
[0078] S4: growing a third conductive structure layer 8 on the second conductive structure layer 6 in the second sub-region.
[0079] S5: growing a fourth conductive structure layer 11 at a position corresponding to the source electrode and a position corresponding to the drain electrode on the third conductive structure layer 8 .
[0080] S6: growing a first drain electrode 2D and a first source electrode 2S on the substrate 1 in the first region.
[0081] S7: growing a second gate 7G, a second drain 7D and a second source 7S on the second conductive structure layer 6 in the first sub-region.
[0082] S8 : growing a third source electrode 9S and a third drain electrode 9D on the fourth conductive structure layer 11 .
[0083] S9: A first gate dielectric layer 3 and a first gate 2G are sequentially grown at positions corresponding to the gate on the substrate 1 in the first region, and a second gate dielectric layer 10 and a third gate 9G are sequentially grown at positions corresponding to the gate on the third conductive structure layer 8.
[0084] In another implementation of this embodiment, step S9 specifically includes the following steps:
[0085] S91: growing an oxide dielectric layer 14 on the surface of the device prepared in step S8. Specifically, the structure of the device prepared in step S8 is as follows: Figure 4A As shown, the structure of the device prepared in step S91 is as follows Figure 4B shown.
[0086] S92: A first gate 2G is grown at a gate-corresponding position on the oxide dielectric layer 14 in the first region, and a third gate 9G is grown at a gate-corresponding position on the oxide dielectric layer 14 in the second sub-region. Specifically, the structure of the device obtained by step S92 is as follows: Figure 4C shown.
[0087] S93: Etching the oxide dielectric layer 14 on the first drain 2D, the first source 2S, the second gate 7G, the second drain 7D, the second source 7S, the third drain 9D, and the third source 9S; the oxide dielectric layer 14 under the first gate 2G is the first gate dielectric layer 3, and the oxide dielectric layer 14 under the third gate 9G is the second gate dielectric layer 10. Specifically, the structure of the device prepared by step S93 is as follows: Figure 4D shown.
[0088] The method for preparing the integrated inverter in this embodiment realizes the preparation of a highly integrated integrated inverter with relatively simple steps.
[0089] Obviously, the above embodiments are merely examples for clarity of explanation and are not intended to limit the implementation methods. Those skilled in the art will readily appreciate that other variations or modifications based on the above descriptions are possible. It is not necessary and impossible to enumerate all implementation methods here. Obvious variations or modifications arising therefrom remain within the scope of protection of the present invention.
Claims
1. An integrated inverter, characterized in that: include: A substrate having a first region and a second region; the thickness of the substrate in the first region is greater than the thickness in the second region; A first gate, a first drain, and a first source are provided on the substrate in the first region, the first gate is located between the first drain and the first source, and a first gate dielectric layer is provided between the first gate and the substrate; a buffer structure layer, disposed on the substrate in the second region; A first conductive structure layer and a second conductive structure layer are sequentially arranged on the buffer structure layer, and the first conductive structure layer and the second conductive structure layer each have a first sub-region and a second sub-region spaced apart, and a heterojunction is formed between the first conductive structure layer and the second conductive structure layer in the first sub-region; A second gate, a second drain, and a second source are provided on the second conductive structure layer of the first sub-region, and the second gate is located between the second drain and the second source; a third conductive structure layer, disposed on the second conductive structure layer in the second sub-region; a third gate, a third drain, and a third source, which are arranged on the third conductive structure layer, the third gate is located between the third drain and the third source, and a second gate dielectric layer is arranged between the third gate and the third conductive structure layer; The first source and the second gate, as well as the first drain and the second source are electrically connected, the first gate and the third gate are electrically connected to form an input end of the integrated inverter, the second drain and the third source are electrically connected to form an output end of the integrated inverter; and the third drain is a driving power connection end of the integrated inverter.
2. The integrated inverter according to claim 1, wherein: Also includes: a fourth conductive structure layer, disposed between the third drain electrode and the third conductive structure layer, and between the third source electrode and the third conductive structure layer; The third conductive structure layer and the fourth conductive structure layer are both P-type doping layers, and the P-type doping concentration in the fourth conductive structure layer is higher than the P-type doping concentration in the third conductive structure layer.
3. The integrated inverter according to claim 2, wherein: The second conductive structure layer is an AlGaN layer, the third conductive structure layer is a P-AlGaN layer, and the fourth conductive structure layer is a P + -AlGaN layer.
4. The integrated inverter according to claim 3, wherein: The first conductive structure layer is a C-doped GaN layer.
5. The integrated inverter according to claim 4, wherein: The buffer structure layer includes a transition layer and a buffer layer. The transition layer is arranged on the substrate in the second region, and the buffer layer is arranged on the transition layer. The buffer layer is a GaN layer.
6. The integrated inverter according to any one of claims 1 to 5, characterized in that: A first spacing groove is provided between the substrate in the first region and the buffer structure layer in the second region, and a second spacing groove is provided between the first sub-region and the second sub-region of the first conductive structure layer and the second conductive structure layer.
7. A method for preparing an integrated inverter, characterized in that: The steps include: S1: Obtain a substrate; the substrate has a first region and a second region, and the thickness of the substrate in the first region is greater than the thickness in the second region; the substrate is obtained by thinning a portion corresponding to the second region on an initial substrate; S2: growing a buffer structure layer on the substrate in the second region; S3: sequentially growing a first conductive structure layer and a second conductive structure layer on the buffer structure layer; the first conductive structure layer and the second conductive structure layer both have a first sub-region and a second sub-region spaced apart, and a heterojunction is formed between the first conductive structure layer and the second conductive structure layer in the first sub-region; S4: growing a third conductive structure layer on the second conductive structure layer in the second sub-region; S5: growing a fourth conductive structure layer at a position corresponding to the source electrode and a position corresponding to the drain electrode on the third conductive structure layer; S6: growing a first drain electrode and a first source electrode on the substrate in the first region; S7: growing a second gate, a second drain, and a second source on the second conductive structure layer in the first sub-region; S8: growing a third source electrode and a third drain electrode on the fourth conductive structure layer; S9: sequentially growing a first gate dielectric layer and a first gate at positions corresponding to the gate on the substrate in the first region, and sequentially growing a second gate dielectric layer and a third gate at positions corresponding to the gate on the third conductive structure layer.
8. The method for preparing an integrated inverter according to claim 7, wherein: A first spacing groove is provided between the buffer structure layer and the substrate of the first region; and a second spacing groove is formed by etching the first conductive structure layer and the second conductive structure layer between the first sub-region and the second sub-region.
9. The method for preparing an integrated inverter according to claim 8, wherein step S9 specifically comprises the following steps: S91: growing an oxide dielectric layer on the surface of the device prepared in step S8; S92: growing the first gate at a gate-corresponding position on the oxide dielectric layer in the first region, and growing the third gate at a gate-corresponding position on the oxide dielectric layer in the second sub-region; S93: etching the oxide dielectric layer on the first drain, the first source, the second gate, the second drain, the second source, the third drain, and the third source; The oxide dielectric layer under the first gate is the first gate dielectric layer, and the oxide dielectric layer under the third gate is the second gate dielectric layer.