A low-power negative voltage charge pump circuit based on CMOS technology

Abstract

The present invention relates to a low-power negative voltage charge pump circuit based on CMOS technology, belonging to the field of radio frequency integrated circuit design. The circuit includes a clock buffer, a frequency divider, a charge pump, and a counter. The charge pump includes a first charge pump and a second charge pump, which operate at different frequencies, and the first charge pump or the second charge pump is selected for operation through the counter; the clock buffer is respectively connected to the frequency divider and the first charge pump; the frequency divider is respectively connected to the counter and the second charge pump; the counter is connected to the first charge pump, and at the same time, the output end of the counter is connected to its input end to form a feedback loop; the charge pump is connected to the circuit load. The present invention realizes the low power consumption of the charge pump by maintaining the operating frequency of the circuit at a low frequency state.

Description

Technical Field

[0001] The present invention belongs to the field of radio frequency integrated circuit design, and relates to a low-power negative voltage charge pump circuit based on CMOS technology. Background Art

[0002] At present, the construction of 5G mobile communication infrastructure is in a state of rapid development. The popularity of 5G mobile phone users and 5G communication facilities has been greatly improved. However, with the emergence of a large number of 5G users, great challenges have been posed to the stability and experience of using 5G communication technology. In a 5G communication system, a radio frequency switch is an important device used to connect any one or several of multiple radio frequency signals through control logic to achieve switching between different signal paths, including switching between reception and transmission, and switching between different frequency bands, etc., in order to achieve the purpose of sharing antennas and saving the cost of terminal products. The charge pump circuit was initially applied to the DC-DC DC voltage conversion module. Due to its advantages such as simple structure, small size, and low noise, it is currently widely used in radio frequency circuit switches, mainly used to generate a negative voltage source lower than ground to control the operation of the radio frequency switch. Therefore, the performance of the charge pump directly affects the performance of the radio frequency switch.

[0003] The charge pump utilizes the characteristic that a capacitor can store charge. By changing the potential of the electrode plate to create a potential difference, the charge stored in the capacitor is moved in a certain direction to achieve an output of a high voltage higher than VDD. In addition, in order to obtain an accurate target voltage, a negative feedback voltage stabilizing circuit is required to perform negative feedback regulation on the output voltage of the charge pump. In existing charge pumps, there are few charge pump design schemes that pay attention to the power consumption of the charge pump itself. When a charge pump fabricated using CMOS technology performs radio frequency switch channel switching, there will be turn-off and turn-on actions of MOS transistors, and certain power consumption will occur when the MOS transistors are turned off or on. Moreover, the higher the clock frequency, the greater the loss, which is not conducive to the application of the charge pump in radio frequency switches. Summary of the Invention

[0004] In view of this, the purpose of the present invention is to provide a low-power charge pump circuit to reduce the power consumption of the charge pump circuit itself.

[0005] To achieve the above purpose, the present invention provides the following technical solutions:

[0006] A low-power negative voltage charge pump circuit based on CMOS technology, including a clock buffer, a frequency divider, a charge pump, and a counter. The charge pump is a dual-pump design, including a first charge pump and a second charge pump. The first charge pump and the second charge pump operate at different frequencies, and the counter is used to select the first charge pump or the second charge pump to operate. The clock buffer is connected to the frequency divider and the first charge pump respectively. The frequency divider is connected to the counter and the second charge pump respectively. The counter is connected to the first charge pump, and at the same time, the output end of the counter is connected to its input end to form a feedback loop. The charge pump is connected to the circuit load to provide a stable negative voltage.

[0007] Optionally, the clock buffer includes inverters I 1 , I 3 , I 4 , I 5 , I 7 , and I 8 , as well as nor gates I 2 , and I 6 ;

[0008] Among them, the input end of inverter I 1 receives a pulse signal, and the output end is respectively connected to the input end of inverter I 5 and the input end of nor gate I 2 ; the output end of nor gate I 2 is connected to the input end of inverter I 3 , the output end of inverter I 3 is connected to the input end of inverter I 4 , the output end of inverter I 4 is respectively connected to the input end of nor gate I 6 , the frequency divider, and the first charge pump;

[0009] The output end of inverter I 5 is connected to the input end of nor gate I 6 , the output end of nor gate I 6 is connected to the input end of inverter I 7 , the output end of inverter I 7 is connected to the input end of inverter I 8 , the output end of inverter I 8 is respectively connected to the input end of nor gate I 2 and the first charge pump.

[0010] Optionally, the frequency divider includes a nand gate and D flip-flops D1 to D3;

[0011] Among them, D flip-flops D1 to D3 are cascaded in sequence. The clock signal input ends of D1 to D3 are all connected to a clock buffer to access the CLK signal, and the reverse output ends are all floating. The input end of D flip-flop D1 is connected to the output end of a NAND gate. The output ends of D flip-flops D2 and D3 are respectively connected to the input ends of the NAND gate. The output end of D flip-flop D3 is also respectively connected to the counter and the second charge pump.

[0012] Optionally, the first charge pump and the second charge pump have the same structure. The specific circuit structure includes PMOS transistors M 1 and M 3 , NMOS transistors M 2 and M 4 , charge and discharge capacitors C 1 and C 2 , and a filter capacitor C L ;

[0013] The drains of PMOS transistors M 1 and M 3 are both grounded. The gates of PMOS transistors M 1 are respectively connected to the gate of NMOS transistor M 2 , the source of PMOS transistor M 3 , the drain of NMOS transistor M 4 , and the first end of capacitor C 2 . The sources of PMOS transistors M 1 are respectively connected to the drain of NMOS transistor M 2 , the gate of PMOS transistor M 3 , the gate of NMOS transistor M 4 , and the first end of capacitor C 1 . The sources of NMOS transistors M 2 and M 4 are both grounded. The second ends of capacitors C 1 and C 2 are respectively connected to the clock buffer.

[0014] Specifically, in the first charge pump, the second end of capacitor C 1 is connected to the output end of inverter I 4 in the clock buffer, and the second end of capacitor C 2 is connected to the output end of inverter I 8 . In the second charge pump, the second end of capacitor C 1 is connected to the output end of D flip-flop D3 in the frequency divider, and there is an inverter connection between the second end of capacitor C 2 and the output end of D flip-flop D3.

[0015] Furthermore, the control method of this circuit is:

[0016] S1. After the pulse signal of the pre-stage is processed by the clock buffer, two non-overlapping signals with the same period and opposite phases are generated;

[0017] S2. For the two signals generated by the clock buffer, one directly acts on the first charge pump, and the other acts on the second charge pump after being processed by the frequency divider to obtain a periodic signal with a period of 1 MHz;

[0018] S3. Under normal conditions of the circuit, the second charge pump is in the working state, and the first charge pump is in the standby state; when there is a channel switch in the RF switch, the trigger signal is input to the counter, and the counter outputs an enable signal to make the first charge pump start to work. After the channel switching is completed, the counter reaches the counting upper limit value, and the first charge pump is turned off, and the second charge pump starts to work.

[0019] The beneficial effects of the present invention are as follows: The present invention adopts a dual charge pump design, and makes the two charge pumps work at different frequencies. At the same time, the pulse signal is frequency-divided by the frequency divider. When the charge pump circuit is working normally, one of the charge pumps works at a low frequency state while the other charge pump is in the standby state, which can greatly reduce the circuit loss when the MOS transistor is turned off or on, thereby realizing the reduction of the power consumption of the charge pump.

[0020] Other advantages, objectives and features of the present invention will be described to some extent in the subsequent description, and to some extent, will be obvious to those skilled in the art based on the study of the following text, or can be taught from the practice of the present invention. The objectives and other advantages of the present invention can be realized and obtained through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be described in detail preferably with reference to the accompanying drawings, where:

[0022] Figure 1 is the structural block diagram of the low-power charge pump circuit of the present invention;

[0023] Figure 2 is the circuit structure diagram of the clock buffer;

[0024] Figure 3 is the circuit structure diagram of the frequency divider;

[0025] Figure 4 is the circuit structure diagram of the charge pump module;

[0026] Figure 5 is the working schematic diagram of the charge pump;

[0027] Figure 6 is the simulation diagram of the output voltage of the charge pump. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0028] The following describes the embodiments of the present invention through specific examples. Those skilled in the art can easily understand the other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the drawings provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner. Without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0029] Among them, the drawings are only for illustrative purposes, showing only schematic diagrams, not physical diagrams, and should not be construed as a limitation to the present invention; in order to better illustrate the embodiments of the present invention, some components in the drawings will be omitted, enlarged or reduced, which does not represent the size of the actual product; for those skilled in the art, it is understandable that some well-known structures and their descriptions in the drawings may be omitted.

[0030] In the drawings of the embodiments of the present invention, the same or similar reference numerals correspond to the same or similar components; in the description of the present invention, it should be understood that if there are terms such as "upper", "lower", "left", "right", "front", "rear", etc. indicating the orientation or positional relationship, they are based on the orientation or positional relationship shown in the drawings. This is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, the terms describing the positional relationship in the drawings are only for illustrative purposes and should not be construed as a limitation to the present invention. For those of ordinary skill in the art, the specific meanings of the above terms can be understood according to specific circumstances.

[0031] The present invention provides a low-power charge pump circuit based on CMOS technology, and its overall structure is as Figure 1 shown, including a clock buffer, a frequency divider, a charge pump (CP), and a counter.

[0032] Among them, the charge pump mainly adopts a dual charge pump optimized structure design, and achieves the effect of low power consumption by selecting the charge pump to operate at a low frequency. The two charge pump structures are the same, and its structure is as Figure 4 shown, including PMOS transistors M 1 and M 3 , NMOS transistors M 2 and M 4 , charge and discharge capacitors C 1 and C 2 , and a filter capacitor C L . Among them, PMOS transistors M 1 and M3 The drains of all are grounded; the PMOS transistor M 1 The gates of are respectively connected to the gates of the NMOS transistors M 2 The source of the PMOS transistor M 3 The drain of the NMOS transistor M 4 And the first terminal of the capacitor C 2 Are connected. The source of the PMOS transistor M 1 The sources of are respectively connected to the drains of the NMOS transistors M 2 The gates of the PMOS transistors M 3 The gates of the NMOS transistors M 4 And the first terminal of the capacitor C 1 Are connected; the sources of the NMOS transistors M 2 And M 4 Are used as the output terminals of the charge pump and are respectively connected to the first terminal of the capacitor C L The first terminal of the capacitor C L The second terminal of the capacitor C is grounded, and the second terminal of the capacitor C 1 The second terminal of the capacitor C and the second terminal of the capacitor C 2 The second terminals of all are connected to the clock signal. In the first charge pump, the second terminal of the capacitor C 1 The second terminal of the capacitor C is connected to the output terminal of the inverter I 4 In the clock buffer, and the second terminal of the capacitor C 2 The second terminal of the capacitor C is connected to the output terminal of the inverter I 8 In the clock buffer. In the second charge pump, the second terminal of the capacitor C 1 The second terminal of the capacitor C is connected to the output terminal of the D flip-flop D3 in the frequency divider, and the second terminal of the capacitor C 2 The second terminal of the capacitor C and the output terminal of the D flip-flop D3 are connected through an inverter.

[0033] The working principle of the charge pump is as Figure 5 Shown. Assuming that the initial voltage of each node in the circuit is 0V, when the first high-level clock comes, the current flow direction is marked, and the capacitor C 1 Starts to charge, and the state of the capacitor C 2 Remains unchanged. After C 1 Is fully charged to VDD, the clock jumps to the low level. At this time, the current flow direction changes. Because the voltage drop across the capacitor C 1 Cannot change suddenly, the voltage of node 1 becomes -VDD and is output to the load circuit. At this time, the capacitor C 2 Starts to charge. When the second high-level clock comes, the voltage of node 2 becomes -VDD, and the capacitor C 1 Recharges. The capacitors C 1 And C 2 Charge and discharge in this cycle to establish a stable negative voltage signal.

[0034] In the present invention, the frequency divider is a five-frequency divider, which divides the 5 MHz pulse of the clock buffer into a 1 MHz pulse signal and outputs it to the second charge pump. The frequency divider is composed of three D flip-flops connected in parallel with a NAND gate, as Figure 3 shown. It adopts a synchronous working mode, and the principle is as follows: two signals A and B with different phases are generated by the pulse swallowing counting principle, and then the NAND gate performs a logical operation on these two signals with different phases and CLK to obtain a five-frequency signal with a duty cycle of 40% to achieve five-frequency division. Since the counter only counts according to the rising edge of the clock pulse, the duty cycle has little influence on the circuit.

[0035] The signal of the clock buffer is divided into two paths after passing through an inverter. One path passes through a NOR gate and then two inverters, and the other path passes through an inverter and then a NOR gate and an inverter, as Figure 2 shown. The two separated signals have the same period and opposite phases.

[0036] The counter is an important part of the entire charge pump circuit. Its working process is as follows: in the entire front-end circuit of the RF switch, when channel switching is required, the counter starts counting, and at the same time, the first charge pump starts working to ensure fast channel switching. When the counter reaches the counting upper limit, the channel switching is basically completed, the first charge pump is turned off, and the second charge pump starts to work normally.

[0037] The charge pump of the present invention works according to the following steps:

[0038] S1. The pulse signal of the previous stage is processed by the clock buffer and output through two paths to generate two non-overlapping signals with the same period and opposite phases to reduce the dead zone. At the same time, this signal can also improve the load capacity of the circuit and reduce the interference and influence of the output glitch on the circuit.

[0039] S2. One path of the signal output by the clock buffer directly acts on the first charge pump, and the other path obtains a 1 MHz periodic signal through the frequency divider and acts on the second charge pump.

[0040] S3. During normal operation, only the second charge pump works, and the first charge pump is in a standby state. The power consumption of the entire negative voltage charge pump is very low. When there is a channel switch in the switch, the counter is triggered to make the first charge pump start working. At this time, the driving ability of the negative voltage charge pump is very strong to ensure channel switching. When the channel switching is basically completed, the counter reaches the counting upper limit value, the first charge pump is turned off, and the second charge pump starts to work.

[0041] From Figure 6From the simulation results, it can be seen that when the set voltage is 2.5V and the frequency is 5MHz, the charge pump can reach a stable output voltage of -2.47V within 40us, and at the same time, the voltage ripple is extremely small, that is, the time order of channel switching is also in the order of us. Therefore, most of the circuit is in the state where the second charge pump operates at 1MHz. Compared with the operating state of 5MHz, it can reduce a large amount of power consumption.

[0042] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit them. Although the present invention has been described in detail with reference to the preferred embodiments, those of ordinary skill in the art should understand that the technical solutions of the present invention can be modified or equivalently replaced without departing from the spirit and scope of the present technical solution, and they should all be covered within the scope of the claims of the present invention.

Claims

1. A low-power negative voltage charge pump circuit based on CMOS process, characterized in that: it includes a clock buffer, a frequency divider, a charge pump and a counter; the charge pump includes a first charge pump and a second charge pump, the first charge pump and the second charge pump work at different frequencies, and the counter is used to select the first charge pump or the second charge pump to work; the clock buffer is respectively connected to the frequency divider and the first charge pump; the frequency divider is respectively connected to the counter and the second charge pump; the counter is connected to the first charge pump and the second charge pump, and at the same time the output end of the counter is connected to its input end to form a feedback loop; the charge pump is connected to the circuit load; The first charge pump and the second charge pump have the same structure; the first charge pump or the second charge pump includes PMOS transistors M 1 and M 3 , NMOS transistors M 2 and M 4 , charge and discharge capacitors C 1 and C 2 and filtering capacitor C L ; PMOS transistor M 1 and M 3 have their drains grounded; the gates of PMOS transistor M 1 are respectively connected to the gate of NMOS transistor M 2 , the source of PMOS transistor M 3 , the drain of NMOS transistor M 4 and the first terminal of capacitor C 2 ; the source of PMOS transistor M 1 is respectively connected to the drain of NMOS transistor M 2 , the gate of PMOS transistor M 3 , the gate of NMOS transistor M 4 and the first terminal of capacitor C 1 ; the sources of NMOS transistors M 2 and M 4 are both grounded; the second terminals of capacitors C 1 and C 2 are respectively connected to clock signals.

2. The low-power negative voltage charge pump circuit according to claim 1, characterized in that: The clock buffer includes inverters I 1 , I 3 , I 4 , I 5 , I 7 , and I 8 , as well as NOR gates I 2 , and I 6 ; wherein Inverter I 1 The input terminal of 5 is connected to the pulse signal, and the output terminal is respectively connected to the input terminal of Inverter I 2 and the input terminal of NOR gate I 2 ; the output terminal of NOR gate I 3 is connected to the input terminal of Inverter I 3 ; the output terminal of Inverter I 4 is connected to the input terminal of Inverter I 4 ; the output terminal of Inverter I 6 is respectively connected to the input terminal of NOR gate I , the frequency divider and the first charge pump; Inverter I 5 's output terminal is connected to the NOR gate I 6 's input terminal, NOR gate I 6 's output terminal is connected to the inverter I 7 's input terminal, inverter I 7 's output terminal is connected to the inverter I 8 's input terminal, inverter I 8 's output terminals are respectively connected to the NOR gate I 2 's input terminal and the first charge pump.

3. The low-power negative voltage charge pump circuit according to claim 1, characterized in that: the frequency divider includes NAND gates and D flip-flops D1 to D3; wherein D flip-flops D1 to D3 are cascaded in sequence, the clock signal input ends of D1 to D3 are all connected to the clock buffer to access the CLK signal, and the reverse output ends are all floating; the input end of D flip-flop D1 is connected to the output end of the NAND gate; the output ends of D flip-flops D2 and D3 are respectively connected to the input ends of the NAND gate; the output end of D flip-flop D3 is also respectively connected to the counter and the second charge pump.

4. The low-power negative voltage charge pump circuit according to any one of claims 1 to 3, characterized in that: the control method of this circuit is: S1. After the pulse signal of the previous stage is processed by the clock buffer, two non-overlapping signals with the same period and opposite phases are generated; S2. For the two signals generated by the clock buffer, one directly acts on the first charge pump, and the other acts on the second charge pump after being processed by the frequency divider to obtain a periodic signal with a period of 1 MHz; S3. In the normal state of this circuit, the second charge pump is in the working state and the first charge pump is in the standby state; when there is a channel switch, the counter is triggered to make the first charge pump start to work. After the channel switch is completed, the counter reaches the counting upper limit value, and the first charge pump is turned off, and the second charge pump starts to work.

Images