Semiconductor structure and method for manufacturing semiconductor structure

Abstract

The present disclosure relates to the field of semiconductor technology, and proposes a semiconductor structure and a method for manufacturing the semiconductor structure. The semiconductor structure includes: a substrate; an isolation structure, the isolation structure is formed in the substrate; a word line, a part of the word line is located in the isolation structure; a conductive part, the conductive part is located at the bottom of the isolation structure, and is used to repel electrons. By making the conductive part located at the bottom of the isolation structure, when the word line is turned on, the conductive part at the bottom of the isolation structure will repel surface electrons, thereby blocking the leakage path, thereby avoiding leakage problems in the semiconductor structure and improving the performance of the semiconductor structure.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for manufacturing the semiconductor structure. Background Art

[0002] As the size of DRAM (Dynamic Random Access Memory) continues to shrink, the size of transistors in the storage area is also shrinking, which brings about serious leakage current problems and affects device performance. Summary of the invention

[0003] The present disclosure provides a semiconductor structure and a method for manufacturing the semiconductor structure to improve the performance of the semiconductor structure.

[0004] According to a first aspect of the present disclosure, there is provided a semiconductor structure, comprising:

[0005] substrate;

[0006] An isolation structure, the isolation structure is formed in the substrate;

[0007] a word line, a portion of the word line being located within the isolation structure;

[0008] The conductive part is located at the bottom of the isolation structure.

[0009] In one embodiment of the present disclosure, the conductive portion contacts the substrate.

[0010] In one embodiment of the present disclosure, the voltages of the conductive portion and the substrate are both negative voltages.

[0011] In one embodiment of the present disclosure, the conductive portion includes:

[0012] A first conductive layer, a portion of which is located within the isolation structure.

[0013] In one embodiment of the present disclosure, the first conductive layer is in contact with the substrate;

[0014] Wherein, the material of the first conductive layer includes polysilicon.

[0015] In one embodiment of the present disclosure, the conductive portion further includes:

[0016] The second conductive layer is in contact with the substrate, and the first conductive layer is located on an upper surface of the second conductive layer.

[0017] In one embodiment of the present disclosure, the material of the first conductive layer includes a metal material, and the material of the second conductive layer includes a metal silicide.

[0018] In one embodiment of the present disclosure, the word lines are buried word lines.

[0019] In one embodiment of the present disclosure, the isolation structure is a shallow trench isolation structure.

[0020] In one embodiment of the present disclosure, the semiconductor structure further includes:

[0021] a first contact plug;

[0022] A second contact plug, wherein the first contact plug and the second contact plug are respectively located at two sides of the word line;

[0023] Wherein, the first contact plug and the second contact plug are both capacitor contact plugs.

[0024] In one embodiment of the present disclosure, the conductive portion is located below the word line and is insulated from the word line.

[0025] In one embodiment of the present disclosure, a height of the conductive portion is smaller than a distance between the conductive portion and the word line.

[0026] According to a second aspect of the present disclosure, a method for manufacturing a semiconductor structure is provided, comprising:

[0027] providing a substrate;

[0028] forming a trench in the substrate;

[0029] An isolation structure is formed in the trench, and a conductive portion is formed at the bottom of the isolation structure;

[0030] forming a word line trench on the isolation structure;

[0031] A word line is formed in the word line trench.

[0032] In one embodiment of the present disclosure, forming a conductive portion includes:

[0033] forming a first conductive layer in the groove, the first conductive layer serving as a conductive portion;

[0034] Wherein, a first insulating layer is formed between the first conductive layer and the sidewall of the trench.

[0035] In one embodiment of the present disclosure, polysilicon is deposited in the trench to form a first conductive layer.

[0036] In one embodiment of the present disclosure, forming a conductive portion includes:

[0037] forming a second conductive layer on the substrate through the trench;

[0038] forming a first conductive layer on the upper surface of the second conductive layer, wherein the first conductive layer and the second conductive layer serve as conductive portions;

[0039] Wherein, the first conductive layer is formed in the trench, and a first insulating layer is formed between the first conductive layer and the sidewall of the trench.

[0040] In one embodiment of the present disclosure, a first metal material is deposited in a substrate and heat-treated to form a metal silicide, and the metal silicide serves as a second conductive layer;

[0041] A second metal material is formed on the metal silicide, and the second metal material serves as a first conductive layer.

[0042] In one embodiment of the present disclosure, before forming the first conductive layer, a third metal material is formed on a wall surface of the first insulating layer;

[0043] Wherein, the first conductive layer is formed in the third metal material.

[0044] In one embodiment of the present disclosure, the substrate has a plurality of active regions, and the isolation structure is disposed between the plurality of active regions;

[0045] A word line trench is also formed on the active region, and a portion of the word line is formed in the word line trench of the active region;

[0046] Before forming the word line, a second insulating layer is formed on the first conductive layer to insulate and isolate the word line from the first conductive layer.

[0047] The semiconductor structure of the embodiment of the present disclosure includes a substrate, an isolation structure, a word line and a conductive part. By locating the conductive part at the bottom of the isolation structure, when the word line is turned on, the conductive part at the bottom of the isolation structure repels surface electrons, thereby blocking the leakage path, thereby avoiding leakage problems in the semiconductor structure and improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Various objects, features and advantages of the present disclosure will become more apparent by considering the following detailed description of preferred embodiments of the present disclosure in conjunction with the accompanying drawings. The accompanying drawings are merely exemplary illustrations of the present disclosure and are not necessarily drawn to scale. In the accompanying drawings, the same reference numerals always refer to the same or similar parts. Among them:

[0049] Figure 1 is a schematic structural diagram of a semiconductor structure according to an exemplary embodiment;

[0050] Figure 2 yes Figure 1 A schematic diagram of the enlarged structure at A in the middle;

[0051] Figure 3 is a schematic structural diagram of a semiconductor structure according to another exemplary embodiment;

[0052] Figure 4 yes Figure 3 A schematic diagram of the enlarged structure at B in the middle;

[0053] Figure 5 is a schematic flow chart of a method for manufacturing a semiconductor structure according to an exemplary embodiment;

[0054] Figure 6 is a top view of a method for manufacturing a semiconductor structure according to an exemplary embodiment showing a trench formed;

[0055] Figure 7 is a schematic cross-sectional structure diagram of a method for manufacturing a semiconductor structure according to an exemplary embodiment to form a trench;

[0056] Figure 8 is a top view of a method for manufacturing a semiconductor structure according to an exemplary embodiment showing how a first insulating layer is formed;

[0057] Fig. 9 is a schematic cross-sectional structural diagram of forming a first insulating layer in a method for manufacturing a semiconductor structure according to an exemplary embodiment;

[0058] Fig.10 is a top view of a method for manufacturing a semiconductor structure according to an exemplary embodiment showing an opening;

[0059] Fig.11 is a schematic cross-sectional structural diagram of a method for manufacturing a semiconductor structure according to an exemplary embodiment to form an opening;

[0060] Fig. 12A is a schematic cross-sectional structure diagram of forming polysilicon in a method for manufacturing a semiconductor structure according to an exemplary embodiment;

[0061] Fig. 12B is a schematic cross-sectional structure diagram of a first metal material formed by a method for manufacturing a semiconductor structure according to an exemplary embodiment;

[0062] Fig.13 is a schematic cross-sectional structural diagram of forming a second conductive layer in a method for manufacturing a semiconductor structure according to an exemplary embodiment;

[0063] Fig.14 is a schematic cross-sectional structure diagram of forming a third metal material in a method for manufacturing a semiconductor structure according to an exemplary embodiment;

[0064] Fig.15 is a schematic cross-sectional structure diagram of forming a second metal material according to a method for manufacturing a semiconductor structure shown in an exemplary embodiment;

[0065] Fig.16is a schematic cross-sectional structural diagram of forming a first conductive layer in a method for manufacturing a semiconductor structure according to an exemplary embodiment;

[0066] Fig.17 is a schematic cross-sectional structural diagram of forming a second insulating layer in a method for manufacturing a semiconductor structure according to an exemplary embodiment;

[0067] Fig.18 The cross-sectional structure diagram of a method for manufacturing a semiconductor structure according to an exemplary embodiment is shown to form a word line.

[0068] The following are the descriptions of the reference numerals:

[0069] 10. substrate; 11. groove; 12. insulating layer; 13. active area; 20. isolation structure; 21. word line groove; 211. fourth insulating layer; 22. first insulating layer; 221. opening; 24. second insulating layer; 30. word line; 31. isolation layer; 32. conductive layer; 33. third insulating layer; 34. barrier layer; 40. conductive portion; 41. first conductive layer; 411. polysilicon; 412. second metal material; 42. second conductive layer; 421. first metal material; 422. third metal material; 4221. recess; 50. first contact plug; 51. second contact plug; 52. third contact plug. DETAILED DESCRIPTION

[0070] Typical embodiments that embody the features and advantages of the present disclosure will be described in detail in the following description. It should be understood that the present disclosure can have various changes in different embodiments without departing from the scope of the present disclosure, and the descriptions and drawings therein are essentially for illustrative purposes rather than for limiting the present disclosure.

[0071] In the following description of different exemplary embodiments of the present disclosure, reference is made to the accompanying drawings, which form a part of the present disclosure and in which different exemplary structures, systems and steps that can implement multiple aspects of the present disclosure are shown by way of example. It should be understood that other specific schemes of components, structures, exemplary devices, systems and steps can be used, and structural and functional modifications can be made without departing from the scope of the present disclosure. Moreover, although the terms "above", "between", "within", etc. may be used in this specification to describe different exemplary features and elements of the present disclosure, these terms are used herein only for convenience, such as according to the direction of the examples in the accompanying drawings. Nothing in this specification should be construed as requiring a specific three-dimensional orientation of the structure to fall within the scope of the present disclosure.

[0072] An embodiment of the present disclosure provides a semiconductor structure. Figures 1 to 4The semiconductor structure includes: a substrate 10; an isolation structure 20, the isolation structure 20 is formed in the substrate 10; a word line 30, a part of the word line 30 is located in the isolation structure 20; and a conductive part 40, the conductive part 40 is located at the bottom of the isolation structure 20, and is used to repel electrons.

[0073] A semiconductor structure of an embodiment of the present disclosure includes a substrate 10, an isolation structure 20, a word line 30 and a conductive portion 40. The conductive portion 40 is located at the bottom of the isolation structure 20, so that when the word line 30 is turned on, the conductive portion 40 at the bottom of the isolation structure 20 repels surface electrons, thereby blocking the leakage path, thereby avoiding leakage problems in the semiconductor structure and improving the performance of the semiconductor structure.

[0074] It should be noted that when the word line 30 is turned on, the electric field attracts electrons on the surface of the word line 30 and the isolation structure 20. In the related art, the isolation structure 20 is made deep enough to avoid the conduction of electrons on both sides of the isolation structure 20. In this embodiment, by forming a conductive portion 40 at the bottom of the isolation structure 20, the conductive portion 40 will repel electrons close to it, thereby blocking the conduction of electrons on both sides of the isolation structure 20. Therefore, the isolation structure 20 in this embodiment can appropriately reduce the depth dimension. Of course, when the depth dimension of the isolation structure 20 is large enough, combined with the conductive portion 40 at the bottom of the isolation structure 20, the ability to block the leakage path can be further improved.

[0075] In one embodiment, the substrate 10 may be a p-type silicon substrate, an n-type silicon substrate, a silicon germanium substrate, or the like.

[0076] In one embodiment, the conductive portion 40 contacts the substrate 10 , so that the conductive portion 40 is electrically connected to the substrate 10 . When the word line 30 is turned on, the conductive portion 40 can repel nearby electrons, thereby blocking the leakage path.

[0077] In one embodiment, the voltages of the conductive portion 40 and the substrate 10 are both negative voltages, and the electrons adsorbed on the surface of the word line 30 and the isolation structure 20 are negative electrons, so that the conductive portion 40 and the substrate 10 can repel nearby electrons, thereby avoiding electron conduction on both sides of the isolation structure 20 and achieving the effect of blocking the leakage path.

[0078] In one embodiment, Figure 2 As shown, the conductive part 40 includes: a first conductive layer 41, part of which is located in the isolation structure 20 and is electrically connected to the substrate 10, so that the voltage of the conductive part 40 can be a negative voltage, thereby repelling nearby negative electrons, avoiding electron conduction on both sides of the isolation structure 20, and achieving the effect of blocking the leakage path.

[0079] In one embodiment, Figure 1 and Figure 2As shown, the first conductive layer 41 is in contact with the substrate 10, that is, the conductive part 40 may only include the first conductive layer 41, and the first conductive layer 41 may be directly formed on the substrate 10, so that the first conductive layer 41 is in contact with the substrate 10, thereby ensuring that the voltages of the conductive part 40 and the substrate 10 are both negative voltages, which can repel nearby negative electrons, avoid the conduction of electrons on both sides of the isolation structure 20, and achieve the effect of blocking the leakage path. In this embodiment, the material of the first conductive layer 41 includes polycrystalline silicon. Directly forming polycrystalline silicon on the substrate 10 can facilitate the formation of polycrystalline silicon on the substrate 10 while ensuring that the voltages of the conductive part 40 and the substrate 10 are both negative voltages. The height of the first conductive layer 41 can be 20nm-30nm. In some embodiments, it is not excluded that the first conductive layer 41 can be a metal material, for example, tungsten (W), tungsten nitride (WN), titanium (Ti), titanium nitride (TiN), molybdenum (Mo), cobalt (Co), nickel (Ni), copper (Cu) or aluminum (Al), etc.

[0080] It should be noted that the bottom end of the first conductive layer 41 may be flush with the bottom end of the isolation structure 20, so that the first conductive layer 41 may be directly formed in the trench 11 of the substrate 10. Alternatively, the bottom end of the first conductive layer 41 may be lower than the bottom end of the isolation structure 20, that is, a groove is formed on the bottom wall of the trench 11, so that the bottom of the first conductive layer 41 is formed, so that the bottom of the first conductive layer 41 is located in the substrate 10.

[0081] In one embodiment, the conductive part 40 further includes: a second conductive layer 42, the second conductive layer 42 is in contact with the substrate 10, and the first conductive layer 41 is located on the upper surface of the second conductive layer 42, so that the first conductive layer 41 is in contact with the second conductive layer 42. Figure 3 and Figure 4 As shown, the conductive part 40 includes a first conductive layer 41 and a second conductive layer 42. The second conductive layer 42 is located in the substrate 10 to achieve electrical connection with the substrate 10, and the first conductive layer 41 is electrically connected to the substrate 10 through the second conductive layer 42, so that the voltage of the conductive part 40 and the substrate 10 are both negative voltages, which can repel nearby negative electrons, avoid electron conduction on both sides of the isolation structure 20, and achieve the effect of blocking the leakage path.

[0082] In one embodiment, the bottom of the first conductive layer 41 is located inside the second conductive layer 42 , thereby improving the conduction stability between the first conductive layer 41 and the second conductive layer 42 .

[0083] In one embodiment, a bottom end of the first conductive layer 41 is connected to a top end of the second conductive layer 42 .

[0084] In one embodiment, the material of the first conductive layer 41 includes a metal material, and the material of the second conductive layer 42 includes a metal silicide, so that the first conductive layer 41 is electrically connected to the substrate 10, and the second conductive layer 42 can be formed in the substrate 10. The height of the first conductive layer 41 can be 20nm-30nm, and the height of the second conductive layer 42 can be 10nm-20nm.

[0085] In some embodiments, the metal material may include, but is not limited to, tungsten (W), tungsten nitride (WN), titanium (Ti), titanium nitride (TiN), molybdenum (Mo), cobalt (Co), nickel (Ni), copper (Cu), or aluminum (Al), etc. The metal silicide may include, but is not limited to, at least one of nickel silicide, platinum silicide, and cobalt silicide.

[0086] In one embodiment, the isolation structure 20 is a shallow trench isolation structure. By forming a conductive portion 40 in the shallow trench isolation structure, the isolation capability of the shallow trench isolation structure can be improved, leakage problems can be avoided, and the depth of the shallow trench isolation structure can be appropriately reduced.

[0087] In one embodiment, Figure 1 As shown, the semiconductor structure also includes: a first contact plug 50; a second contact plug 51, the first contact plug 50 and the second contact plug 51 are respectively located on both sides of the word line 30; wherein the first contact plug 50 and the second contact plug 51 are both capacitor contact plugs, so that the first contact plug 50 and the second contact plug 51 are used to connect two capacitor structures, and when the word line 30 is opened, the first contact plug 50 and the second contact plug 51 will be connected with the electrons on both sides of the isolation structure 20, therefore, when the electrons on both sides of the isolation structure 20 are connected, it will cause the first contact plug 50 and the second contact plug 51 to be connected, so there will be a leakage problem between the two capacitor structures, and in this embodiment, by forming a conductive part 40 at the bottom of the isolation structure 20, the conductive part 40 will repel electrons close to it, thereby blocking the electron conduction on both sides of the isolation structure 20, thereby preventing leakage problems between the two capacitor structures.

[0088] It should be noted that if Figure 1 and Figure 3 As shown, the semiconductor structure may further include a third contact plug 52 . The first contact plug 50 , the second contact plug 51 and the third contact plug 52 may all be multiple, which is not limited here and can be determined according to actual needs.

[0089] In one embodiment, the conductive portion 40 is located below the word line 30 and is insulated from the word line 30 , so that when the word line 30 is turned on, the conductive portion 40 repels electrons approaching it, thereby blocking electron conduction on both sides of the isolation structure 20 .

[0090] In one embodiment, the height of the conductive portion 40 is smaller than the distance between the conductive portion 40 and the word line 30 , that is, the size of the conductive portion 40 can be minimized while ensuring the ability of the conductive portion 40 to block the leakage path.

[0091] In one embodiment, Figure 1 and Figure 3 As shown, an isolation layer 31 is formed inside the isolation structure 20, and the isolation layer 31 is located above the word line 30. The isolation layer 31 can protect the word line 30. In one embodiment, the isolation layer 31 can include nitride or silicon oxide.

[0092] In one embodiment, Figure 1 and Figure 3 As shown, an insulating layer 12 is formed on the upper surface of the substrate 10 to cover the upper surface of the substrate 10, and the isolation structure 20 in the substrate 10 forms an integral body, so that the upper surface of the substrate 10 is covered with an insulating material forming the isolation structure 20, and the insulating layer 12 covers the insulating material. The insulating layer 12 may include nitride or silicon oxide.

[0093] In one embodiment, the word line 30 is a buried word line, and the material of the word line 30 includes one or any combination of conductive materials such as tungsten, titanium, nickel, aluminum, platinum, titanium nitride, etc. In some embodiments, an isolation layer 31 is further formed in the word line groove 21, and the isolation layer 31 is located above the word line 30. The isolation layer 31 can protect the word line 30. After the isolation layer 31 is formed, the isolation layer 31 can be planarized by dry etching or chemical mechanical polishing (CMP).

[0094] In one embodiment, an isolation structure 20 is formed in the substrate 10, the isolation structure 20 isolates a plurality of active regions 13, and the word lines 30 are located in the isolation structure 20 and the active regions 13. In some embodiments, a conductive portion 40 may be disposed under each word line 30 located in the isolation structure 20. In some embodiments, a conductive portion 40 may not be disposed under one or more word lines 30 of the plurality of word lines 30 located in the isolation structure 20. When two capacitor contact plugs (such as a first contact plug 50 and a second contact plug 51) are formed on both sides of the isolation structure 20, a conductive portion 40 is formed under the word line 30 in the corresponding isolation structure 20, so as to avoid leakage problems between the two capacitor structures.

[0095] In one embodiment, the word line 30 may include a plurality of protruding structures, and the plurality of protruding structures may be respectively located in the isolation structure 20 and the active region 13. The heights of the protruding structures may be consistent or inconsistent.

[0096] An embodiment of the present disclosure also provides a method for manufacturing a semiconductor structure. Figure 5 As shown, the method for manufacturing a semiconductor structure includes:

[0097] S101, providing a substrate 10;

[0098] S103, forming a groove 11 in the substrate 10;

[0099] S105, forming an isolation structure 20 in the trench 11, and forming a conductive portion 40 for repelling electrons at the bottom of the isolation structure 20;

[0100] S107, forming a word line trench 21 on the isolation structure 20;

[0101] S109 , forming a word line 30 in the word line trench 21 .

[0102] The manufacturing method of a semiconductor structure according to an embodiment of the present disclosure forms a trench 11 in a substrate 10, forms an isolation structure 20 in the trench 11, and forms a conductive portion 40 at the bottom of the isolation structure 20, and forms a word line 30 in the word line trench 21 of the isolation structure 20. The formation of the conductive portion 40 at the bottom of the isolation structure 20 can repel surface electrons, thereby blocking the leakage path, thereby avoiding leakage problems in the semiconductor structure and improving the performance of the semiconductor structure.

[0103] In one embodiment, Figure 6 and Figure 7 As shown, a trench 11 is formed in a provided substrate 10, so that a plurality of active regions 13 are isolated in the trench 11. The trench 11 can be formed by using a shallow trench isolation technology.

[0104] In one embodiment, an insulating layer 12 is formed on the upper surface of the substrate 10. When forming the groove 11, the insulating layer 12 can be covered by a mask structure, and a pattern corresponding to the groove 11 can be formed on the insulating layer 12, so that a through hole can be formed on the insulating layer 12 by an etching process, and a groove can be formed in the substrate 10 to form the groove 11. Figure 6 and Figure 7 shown.

[0105] In one embodiment, part of the conductive portion 40 is formed before the isolation structure 20 and is formed in the groove 11 to contact the substrate 10, thereby ensuring that the voltages of the conductive portion 40 and the substrate 10 are both negative voltages, so that the conductive portion 40 and the substrate 10 repel nearby electrons, avoiding electron conduction on both sides of the isolation structure 20, and achieving the effect of blocking the leakage path.

[0106] It should be noted that, considering that the conductive portion 40 is formed at the bottom of the isolation structure 20 , the conductive portion 40 needs to be formed before the isolation structure 20 is completely formed, so that the conductive portion 40 can be formed at the bottom of the isolation structure 20 .

[0107] In one embodiment, a first conductive layer 41 is formed in the trench 11, and the first conductive layer 41 serves as the conductive portion 40. Specifically, after the trench 11 is formed, the first conductive layer 41 may be formed at the bottom of the trench 11, and the first conductive layer 41 may fill the bottom of the trench 11, and then the first conductive layer 41 is etched to expose the bottom sidewall of the trench 11, and then the isolation structure 20 is filled in the trench 11 to bury the first conductive layer 41. Optionally, a portion of the isolation structure 20 is filled in the trench 11, and an opening is formed in the isolation structure to expose the substrate 10, and the first conductive layer 41 is formed in the opening, and then another portion of the isolation structure 20 is filled in the trench 11 to bury the first conductive layer 41.

[0108] In one embodiment, a second conductive layer 42 is formed in the substrate 10, a first conductive layer 41 is formed on the second conductive layer 42, a portion of the first conductive layer 41 is formed in the trench 11, and the first conductive layer 41 and the second conductive layer 42 serve as the conductive portion 40. Specifically, a groove may be formed in the substrate 10 through the trench 11, and the second conductive layer 42 is formed in the groove, and then the first conductive layer 41 is formed at the bottom of the trench 11, and the first conductive layer 41 may fill the bottom of the trench 11, and then the first conductive layer 41 is etched to expose the bottom sidewall of the trench 11, and then the isolation structure 20 is filled in the trench 11 to bury the first conductive layer 41. Optionally, a groove may be formed in the substrate 10 through the trench 11, and the second conductive layer 42 is formed in the groove, a portion of the isolation structure 20 is filled in the trench 11, and an opening is formed in the isolation structure to expose the second conductive layer 42, and the first conductive layer 41 is formed in the opening, and then the other portion of the isolation structure 20 is filled in the trench 11 to bury the first conductive layer 41. Optionally, a metal material is deposited in the substrate 10 through the trench 11 and annealed to form the second conductive layer 42 , and then the first conductive layer 41 can be formed in the above two ways.

[0109] It should be noted that the metal material is deposited in the substrate 10 formed with the groove 11, so that the metal material reacts with the silicon in the substrate 10 to form the second conductive layer 42. The metal material can be deposited by adopting a physical vapor deposition process, a chemical vapor deposition process or an atomic layer deposition process, and the metal material can include one or more of metals such as nickel, platinum, and cobalt. In some embodiments, after the metal material is deposited in the substrate 10, an annealing treatment is performed to form the second conductive layer 42. The annealing treatment can be performed by high-temperature advancement of a furnace tube or by an annealing method in related technologies such as rapid thermal annealing.

[0110] In one embodiment, forming the conductive part 40 includes: forming a first conductive layer 41 in the groove 11, and the first conductive layer 41 serves as the conductive part 40; wherein a first insulating layer 22 is formed between the first conductive layer 41 and the side wall of the groove 11, so as to ensure the insulation between the first conductive layer 41 and the side wall of the groove 11, thereby ensuring that the conductive part 40 can repel surface electrons and avoiding the problem of a large volume of the first conductive layer 41.

[0111] In some embodiments, a first insulating layer 22 is formed in the trench 11, and the first insulating layer 22 fills the trench 11 and covers the insulating layer 12. Figure 8 and Fig. 9 The first insulating layer 22 may be made of nitride or silicon oxide. The first insulating layer 22 may be formed by a physical vapor deposition process, a chemical vapor deposition process, or an atomic layer deposition process.

[0112] An opening 221 is formed in the first insulating layer 22, and the opening 221 exposes the substrate 10, that is, the sidewall of the opening 221 is covered with the first insulating layer 22. Fig.10 and Fig.11 In some embodiments, the first insulating layer 22 above the insulating layer 12 may be partially retained, such as Fig.10 In some embodiments, the first insulating layer 22 above the insulating layer 12 may be removed. Fig.11 As shown, the opening 221 can be formed by etching. The opening 221 is a part of the groove 11.

[0113] In one embodiment, polysilicon 411 is deposited in the trench 11 to form a first conductive layer 41 , that is, the polysilicon 411 serves as a conductive portion 40 for repelling nearby electrons.

[0114] In some embodiments, polysilicon 411 is deposited in the opening 221, and the polysilicon 411 fills the opening 221 and covers the insulating layer 12. Fig. 12A The polysilicon 411 on the insulating layer 12 and part of the polysilicon 411 in the opening 221 are removed by etching process, so that the remaining height of the polysilicon 411 is 20nm-30nm, so that the remaining polysilicon 411 serves as the conductive part 40.

[0115] In one embodiment, forming the conductive part 40 includes: forming a second conductive layer 42 on the substrate 10 through the groove 11; forming a first conductive layer 41 on the upper surface of the second conductive layer 42, and the first conductive layer 41 and the second conductive layer 42 serve as the conductive part 40; wherein the first conductive layer 41 is formed in the groove 11, and a first insulating layer 22 is formed between the first conductive layer 41 and the side wall of the groove 11; the first conductive layer 41 is electrically connected to the substrate 10 through the second conductive layer 42, so that the voltage of the conductive part 40 and the substrate 10 are both negative voltages, which can repel nearby negative electrons, avoid electron conduction on both sides of the isolation structure 20, and achieve the effect of blocking the leakage path.

[0116] In one embodiment, a first metal material 421 is deposited in the substrate 10 and heat-treated to form a metal silicide, which serves as the second conductive layer 42; a second metal material 412 is formed on the metal silicide, which serves as the first conductive layer 41. The first conductive layer 41 and the second conductive layer 42 are respectively formed of the first metal material 421 and the second metal material 412, and are connected to each other, thereby repelling nearby electrons, preventing the conduction of electrons on both sides of the isolation structure 20, and achieving the effect of blocking the leakage path.

[0117] In some embodiments, after forming the opening 221 in the first insulating layer 22, a first metal material 421 is deposited in the opening 221, the first metal material 421 fills the opening 221 and covers the insulating layer 12, and after heat treatment, the first metal material 421 reacts with the substrate 10 to form a metal silicide, and the metal silicide serves as the second conductive layer 42, such as Fig. 12B The heat treatment temperature may be 340°C-450°C.

[0118] The first metal material 421 and a portion of the metal silicide in contact with the substrate 10 are removed by wet etching to expose the second conductive layer 42. Fig.13 As shown, the height of the metal silicide can be 10 nm-20 nm, that is, the height of the second conductive layer 42 can be 10 nm-20 nm.

[0119] In one embodiment, before forming the first conductive layer 41 , a third metal material 422 is formed on the wall surface of the first insulating layer 22 ; wherein the first conductive layer 41 is formed in the third metal material 422 , and the third metal material 422 protects the first conductive layer 41 .

[0120] The third metal material 422 is deposited in the opening 221. The third metal material 422 fills the opening 221, covers the insulating layer 12, and contacts the second conductive layer 42. Fig.14As shown. The second metal material 412 may be tungsten. The third metal material 422 may be a metal nitride, for example, the third metal material 422 may be titanium nitride.

[0121] A groove 4221 is formed in the third metal material 422, and the second metal material 412 is deposited in the groove 4221. The second metal material 412 fills the groove 4221 and covers the upper surface of the third metal material 422. Fig.15 shown.

[0122] The second metal material 412 and the third metal material 422 are etched, so that a portion of the second metal material 412 and the third metal material 422 located in the opening 221 is retained, and the remaining second metal material 412 is used as the first conductive layer 41, and the first conductive layer 41 is located in the remaining third metal material 422, such as Fig.16 As shown, the remaining height of the second metal material 412 may be 20 nm to 30 nm.

[0123] In some embodiments, the conductive portion 40 may include a metal silicide formed by a first metal material 421 and the substrate 10 , a second metal material 412 , and a third metal material 422 .

[0124] In one embodiment, word line trenches 21 are formed on both the isolation structure 20 and the active region 13 , and the word lines 30 are formed in the word line trenches 21 of the isolation structure 20 and the active region 13 .

[0125] In one embodiment, after forming the conductive portion 40, an opening 221 is left exposed above the conductive portion 40. Fig.16 A second insulating layer 24 is formed in the opening 221, and the second insulating layer 24 fills the exposed opening 221 and covers the insulating layer 12, as shown. Fig.17 shown.

[0126] A plurality of word line trenches 21 are formed over the second insulating layer 24 and in the active region 13 , and word lines 30 are formed in the word line trenches 21 .

[0127] In one embodiment, after a portion of the second insulating layer 24 is removed, the opening 221 above the second insulating layer 24 is exposed, that is, the exposed opening 221 is used as the word line trench 21 in the isolation structure 20, and the word line trench 21 is also formed in the active area 13. The first insulating layer 22 and the second insulating layer 24 can serve as the isolation structure 20 described above.

[0128] The word line 30 may include a barrier layer 34, a conductive layer 32, and a third insulating layer 33. The barrier layer 34 covers the wall of the word line trench 21, the conductive layer 32 is located in the barrier layer 34, and the third insulating layer 33 covers the barrier layer 34 and the conductive layer 32. Fig.18shown.

[0129] After the barrier layer 34 is deposited and formed in the word line groove 21, the barrier layer 34 fills the word line groove 21, and the remaining barrier layer 34 is etched to cover the wall surface of the word line groove 21, and then the conductive layer 32 is filled in the barrier layer 34, and the conductive layer 32 is etched so that the upper surface of the conductive layer 32 is flush with the upper surface of the barrier layer 34, and finally the third insulating layer 33 is formed.

[0130] In one embodiment, the barrier layer 34 may include Ta, Ti, Ru, TaN, TiN, RuTa, RuTaN, W or Ir, etc. The barrier layer 34 may be any other material that prevents the conductive material layer from diffusing through. In one embodiment, the conductive layer 32 may be a metal material, for example, Cu, Al, W or an alloy thereof. In one embodiment, the third insulating layer 33 may be formed of a material including silicon oxide, silicon nitride or a combination thereof, for example, the third insulating layer 33 may be SiN, SiON or SiO2. 2 .

[0131] In one embodiment, after forming the word line trench 21, a fourth insulating layer 211 is formed on the sidewall of the word line trench 21, and the word line 30 is formed in the fourth insulating layer 211. The fourth insulating layer 211 may be formed of a material including silicon oxide, silicon nitride, or a combination thereof. For example, the fourth insulating layer 211 may be SIN, SION, or SIO. 2 .

[0132] It should be noted that when the first conductive layer 41 is used as the conductive portion 40, Fig. 12A After the polysilicon 411 shown, a second insulating layer 24 will be formed on the polysilicon 411, and subsequently word line grooves 21 will be formed on the isolation structure 20 and the active area 13. The word line 30 is formed in the word line grooves 21 of the isolation structure 20 and the active area 13. The specific structure and process can refer to the structure and process when the first conductive layer 41 and the second conductive layer 42 are used as the conductive part 40.

[0133] In one embodiment, the method for manufacturing a semiconductor structure further includes forming a first contact plug 50 and a second contact plug 51 on both sides of the word line 30, wherein the first contact plug 50 and the second contact plug 51 are both capacitor contact plugs, and the first contact plug 50 and the second contact plug 51 are used to connect two capacitor structures. When the word line 30 is opened, the first contact plug 50 and the second contact plug 51 will be connected to the electrons on both sides of the isolation structure 20. Therefore, when the electrons on both sides of the isolation structure 20 are connected, the first contact plug 50 and the second contact plug 51 will be connected, so there will be a leakage problem between the two capacitor structures. In this embodiment, by forming a conductive portion 40 at the bottom of the isolation structure 20, the conductive portion 40 will repel electrons close to it, thereby blocking the electron conduction on both sides of the isolation structure 20, thereby preventing leakage problems between the two capacitor structures.

[0134] The semiconductor structure formed by this method has a conductive portion 40 at the bottom of the isolation structure 20. The conductive portion 40 can repel electrons and reduce the leakage current problem of the semiconductor structure, thereby improving the performance of the semiconductor structure and is suitable for small-sized and high-performance DRAM devices.

[0135] It should be noted that the semiconductor structure in this embodiment can be obtained by the above-mentioned method for manufacturing the semiconductor structure, and other materials and structures of the semiconductor structure in this embodiment can refer to the above-mentioned method for manufacturing the semiconductor structure.

[0136] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. The present disclosure is intended to cover any variations, uses or adaptations of the present invention that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The specification and example embodiments are to be considered exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

[0137] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

Claims

1. A semiconductor structure, It is characterized in that include: substrate; an isolation structure formed in the substrate; a word line, a portion of the word line being located within the isolation structure; A conductive portion, the conductive portion being located at the bottom of the isolation structure; The conductive portion is in contact with the substrate; The conductive part includes a first conductive layer, and a portion of the first conductive layer is located in the isolation structure.

2. The semiconductor structure according to claim 1, It is characterized in that The voltages of the conductive part and the substrate are both negative voltages.

3. The semiconductor structure according to claim 1, It is characterized in that The first conductive layer is in contact with the substrate; wherein the material of the first conductive layer includes polysilicon.

4. The semiconductor structure according to claim 1, It is characterized in that The conductive part further includes: A second conductive layer is in contact with the substrate, and the first conductive layer is located on an upper surface of the second conductive layer.

5. The semiconductor structure according to claim 4, It is characterized in that The material of the first conductive layer includes a metal material, and the material of the second conductive layer includes a metal silicide.

6. The semiconductor structure according to claim 1, It is characterized in that The word line is a buried word line.

7. The semiconductor structure according to claim 1, It is characterized in that The isolation structure is a shallow trench isolation structure.

8. The semiconductor structure according to claim 1, It is characterized in that The semiconductor structure further comprises: a first contact plug; second contact plugs, the first contact plug and the second contact plug are respectively located at two sides of the word line; Wherein, both the first contact plug and the second contact plug are capacitor contact plugs.

9. The semiconductor structure according to claim 1, It is characterized in that The conductive portion is located below the word line and is insulated from the word line.

10. The semiconductor structure according to claim 9, It is characterized in that The height of the conductive portion is smaller than a distance between the conductive portion and the word line.

11. A method for manufacturing a semiconductor structure, It is characterized in that include: providing a substrate; forming a trench in the substrate; An isolation structure is formed in the trench, and a conductive portion is formed at the bottom of the isolation structure; forming a word line trench on the isolation structure; forming a word line in the word line trench; Forming the conductive portion includes: forming a second conductive layer on the substrate through the groove; forming a first conductive layer on the upper surface of the second conductive layer, wherein the first conductive layer and the second conductive layer serve as the conductive portion; The first conductive layer is formed in the trench, and a first insulating layer is formed between the first conductive layer and the sidewall of the trench.

12. The method for manufacturing a semiconductor structure according to claim 11, It is characterized in that Forming the conductive portion includes: forming a first conductive layer in the groove, wherein the first conductive layer serves as the conductive portion; Wherein, a first insulating layer is formed between the first conductive layer and the sidewall of the trench.

13. The method for manufacturing a semiconductor structure according to claim 12, It is characterized in that Polysilicon is deposited in the trench to form the first conductive layer.

14. The method for manufacturing a semiconductor structure according to claim 11, It is characterized in that Depositing a first metal material in the substrate and performing heat treatment to form a metal silicide, wherein the metal silicide serves as the second conductive layer; A second metal material is formed on the metal silicide, and the second metal material serves as the first conductive layer.

15. The method for manufacturing a semiconductor structure according to claim 11 or 14, It is characterized in that Before forming the first conductive layer, forming a third metal material on a wall surface of the first insulating layer; Wherein, the first conductive layer is formed in the third metal material.

16. The method for manufacturing a semiconductor structure according to any one of claims 12 to 14, It is characterized in that The substrate has a plurality of active regions, and the isolation structure is arranged between the plurality of active regions; The word line groove is also formed on the active area, and part of the word line is formed in the word line groove of the active area; Before forming the word line, a second insulating layer is formed on the first conductive layer to insulate and isolate the word line from the first conductive layer.

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