CPU Testing Method, System, Device, Storage Medium and Electronic Device

Abstract

An embodiment of the present application provides a CPU testing method, system, device, storage medium and electronic device. Among them, the method includes: the host computer determines a first parameter range and a second parameter range of the power supply chip of the CPU to be tested, where the first parameter range represents the first value range of the first parameter of the power supply chip, and the second parameter range represents the second value range of the second parameter of the power supply chip; determines N value pairs according to the first parameter range and the second parameter range, and stores the N value pairs in the target storage unit; the host computer sequentially obtains the value pairs in the N value pairs from the target storage unit, and tests the CPU to be tested according to the obtained value pairs to obtain N groups of results. Through the embodiment of the present application, the technical problem of low testing efficiency of the CPU in the related art is solved, and thus the effect of improving the testing efficiency of the CPU is achieved.

Description

Technical Field

[0001] The embodiments of the present application relate to the technical field of servers, and in particular, to a CPU testing method, system, device, storage medium, and electronic device. Background Art

[0002] During the daily use of server systems, customers often have different requirements for the performance and power consumption of servers according to different usage scenarios and needs. Since power is equal to voltage multiplied by current, the calculation of processor power is directly related to the current monitoring Imon signal, and performance is also somewhat related to power consumption.

[0003] Generally speaking, the greater the power consumption, the higher the performance. In the INTEL VRTT (Voltage Regulator Test Tool) test report, Imon has a certain SPEC standard range. The up and down deviation of the Imon curve of the CPU within the SPEC range has a greater impact on the performance and power consumption of the CPU. Traditionally, the Imon curve is manually changed within the SPEC range, and then the performance test of SPECCPU is carried out separately, and then the stress test of the performance tuning tool PTU (Performance Tuning Utility) is carried out separately.

[0004] However, the performance test of SPECCPU takes about 4 hours for one run, and the PTU CPU pressure test also requires at least half an hour of pressurization. Manually collecting power data is time-consuming, laborious, and inaccurate, and it is impossible to automatically record the corresponding relationship between power consumption, performance, and the Imon curve, resulting in low test efficiency of CPU performance and power consumption, and not meeting the current increasing requirements for performance and power consumption tuning tests.

[0005] Regarding the technical problem of low test efficiency of the CPU in the related art, no effective solution has been proposed yet. Summary of the Invention

[0006] The embodiments of the present application provide a CPU testing method, system, device, storage medium, and electronic device to at least solve the technical problem of low test efficiency of the CPU in the related art.

[0007] According to an embodiment of the present application, a CPU testing method is provided, including: the host computer determines a first parameter range and a second parameter range of the power supply chip of the CPU to be tested, where the first parameter range represents a first value range of a first parameter of the power supply chip, the second parameter range represents a second value range of a second parameter of the power supply chip, the first parameter represents a gain parameter for the power supply chip to adjust the current, and the second parameter represents a bias parameter for the power supply chip to adjust the current; the host computer determines N value pairs according to the first parameter range and the second parameter range, and stores the N value pairs in a target storage unit, where each of the N value pairs includes a value in the first value range of the first parameter and a value in the second value range of the second parameter, and N is a positive integer greater than or equal to 2; the host computer sequentially obtains the value pairs in the N value pairs from the target storage unit, and tests the CPU to be tested according to the obtained value pairs to obtain N groups of results.

[0008] In an exemplary embodiment, the host computer determines the first parameter range and the second parameter range of the power supply chip of the CPU to be tested, including: obtaining a first reference curve and a second reference curve, where the first reference curve is used to represent the upper limit of the current value allowed for the current value provided by the power supply chip monitored by the CPU to be tested when the actual output current value of the power supply chip is different values in a target current value range, and the second reference curve is used to represent the lower limit of the current value allowed for the current value provided by the power supply chip monitored by the CPU to be tested when the actual output current value of the power supply chip is different values in the target current value range; determining the first parameter range and the second parameter range according to the first reference curve and the second reference curve, where M value pairs composed of each value of the first parameter in the first parameter range and each value of the second parameter in the second parameter range satisfy a target preset condition, and the target preset condition includes: when the power supply chip supplies power to the CPU to be tested according to the value of the first parameter and the value of the second parameter in the i-th value pair, and when the actual output current value of the power supply chip is the i-th current value in the target current value range, the current value provided by the power supply chip monitored by the CPU to be tested is between the upper limit and the lower limit of the current value corresponding to the i-th current value, where M is a positive integer greater than or equal to 2, and i is a positive integer greater than or equal to 1 and less than or equal to M.

[0009] In an exemplary embodiment, the host computer determines a first parameter range and a second parameter range of a power supply chip of a CPU to be measured, including: obtaining a first reference curve and a second reference curve, where the first reference curve is used to represent the upper limit of the current value allowed for the current value provided by the power supply chip monitored by the CPU to be measured when the actual output current value of the power supply chip is different values in a target current value range, and the second reference curve is used to represent the lower limit of the current value allowed for the current value provided by the power supply chip monitored by the CPU to be measured when the actual output current value of the power supply chip is different values in the target current value range; obtaining a first initial value of the first parameter and a second initial value of the second parameter; determining the first parameter range according to the first reference curve, the second reference curve, and the second initial value, where P value pairs formed by each value of the first parameter in the first parameter range and the second initial value satisfy a target preset condition, and the target preset condition includes: when the power supply chip supplies power to the CPU to be measured according to the value of the first parameter and the value of the second parameter in the jth value pair, and when the actual output current value of the power supply chip is the jth current value in the target current value range, the current value provided by the power supply chip monitored by the CPU to be measured is between the upper limit and the lower limit of the current value corresponding to the jth current value, where P is a positive integer greater than or equal to 1; determining the second parameter range according to the first reference curve, the second reference curve, and the first initial value, where Q value pairs formed by the first initial value and each value of the second parameter in the second parameter range satisfy the target preset condition, where Q is a positive integer greater than or equal to 1.

[0010] In an exemplary embodiment, the host computer determines N value pairs according to the first parameter range and the second parameter range, including: obtaining R values of the first parameter from the first parameter range according to a first predetermined step size, and obtaining S values of the second parameter from the second parameter range according to a second predetermined step size, where R is a positive integer greater than or equal to 1, and S is a positive integer greater than or equal to 1; combining each value of the R values with each value of the S values to obtain the N value pairs, where N = R * S.

[0011] In an exemplary embodiment, the host computer sequentially obtains the value pairs in the N value pairs from the target storage unit, and tests the CPU under test according to the obtained value pairs to obtain N groups of results, including: the host computer sequentially obtains each of the N value pairs in the N value pairs from the target storage unit, and respectively performs a performance test and a stress test on the CPU under test to obtain N first test results and N second test results, where the first test result includes the performance score of the CPU under test, the second test result includes the power consumption value of the CPU under test, and each group of results in the N groups of results includes the first test result and the second test result obtained according to a corresponding value pair.

[0012] In an exemplary embodiment, after obtaining the N groups of results, the method further includes: respectively combining each of the N value pairs with the corresponding group of results in the N groups of results to form a group of test information of the CPU under test, obtaining N groups of test information, where each group of test information in the N groups of test information is used to represent the first test result and the second test result obtained when the first parameter and the second parameter are the values in each of the N value pairs; classifying the N groups of test information to obtain M types of energy consumption information, where each type of energy consumption information in the M types of energy consumption information includes one or more groups of test information, and the corresponding performance scores and / or power consumption values in different types of energy consumption information in the M types of energy consumption information belong to different value ranges; importing the M types of energy consumption information into the basic input / output system BIOS, where the M types of energy consumption information in the BIOS are set to be selectable.

[0013] In an exemplary embodiment, the host computer sequentially obtains the value pairs in the N value pairs from the target storage unit, and tests the CPU under test according to the obtained value pairs to obtain N groups of results, including: obtaining the kth group of results in the N groups of results by performing the following steps, where k is a positive integer greater than or equal to 1 and less than or equal to N: obtaining the kth value pair in the N value pairs from the target storage unit; writing the kth value pair into the power supply chip of the CPU under test, and instructing the power supply chip to supply power to the CPU under test according to the values of the first parameter and the second parameter corresponding to the kth value pair; performing a performance test and a stress test on the CPU under test when the power supply chip supplies power to the CPU under test according to the values of the first parameter and the second parameter corresponding to the kth value pair, to obtain the kth group of results, where the kth group of results includes the performance score of the CPU under test and the power consumption value of the CPU under test.

[0014] In an exemplary embodiment, after obtaining the N groups of results, the method further includes: adjusting the first parameter and / or the second parameter of the power supply chip of the CPU to be tested according to the N groups of results.

[0015] According to another embodiment of the present application, there is also provided a CPU test system, including: a host computer, configured to determine a first parameter range and a second parameter range of a power supply chip of a CPU to be tested, and determine N value pairs according to the first parameter range and the second parameter range, and store the N value pairs in a target storage unit, where the first parameter range represents a first value range of the first parameter of the power supply chip, the second parameter range represents a second value range of the second parameter of the power supply chip, the first parameter represents a gain parameter for adjusting the current of the power supply chip, the second parameter represents a bias parameter for adjusting the current of the power supply chip, each of the N value pairs includes a value in the first value range of the first parameter and a value in the second value range of the second parameter, and N is a positive integer greater than or equal to 2; a server, connected to the host computer, the server includes the CPU to be tested and the power supply chip, and is configured to sequentially obtain the value pairs in the N value pairs from the target storage unit, and test the CPU to be tested according to the obtained value pairs to obtain N groups of results.

[0016] In an exemplary embodiment, the system further includes: a test tool, connected to a power supply test board, the test tool is configured to test the power supply chip of the CPU to be tested to obtain a target curve, where the power supply chip is installed on the power supply test board, and the target curve is used to represent a curve between a first current value monitored by the CPU to be tested provided by the power supply chip and a second current value actually output by the power supply chip when the first parameter is equal to a first initial value and the second parameter is equal to a second initial value.

[0017] In an exemplary embodiment, the host computer includes: a debugging software unit, configured to set the first parameter of the power supply chip to the first initial value and set the second parameter of the power supply chip to the second initial value through a program burner, and instruct the test tool to obtain the target curve; or the debugging software unit is further configured to sequentially write each of the N value pairs into the power supply chip in the server through the program burner, and instruct the power supply chip to supply power to the CPU to be tested sequentially according to the values of the first parameter and the second parameter corresponding to each of the N value pairs.

[0018] In an exemplary embodiment, the system further includes: a power meter, connected to the server and the host computer, the power meter being configured to test a second test result of the CPU under test for each of the N value pairs to obtain N second test results, where the second test result includes a power consumption value of the CPU under test, and each of the N groups of results includes one of the second test results.

[0019] In an exemplary embodiment, the host computer includes: a virtual system unit, configured to test the CPU under test in the server through a target script to obtain the N groups of results.

[0020] In an exemplary embodiment, the virtual system unit includes: a first window, configured to perform a performance test on the CPU under test through a first test script to obtain N first test results, the first test result including a performance score of the CPU under test; a second window, configured to perform a stress test on the CPU under test through a second test script to obtain N second test results, the second test result including a power consumption value of the CPU under test; the target script includes the first test script and the second test script, and each of the N groups of results includes the first test result and the second test result obtained by the CPU under test under the same parameter pair.

[0021] In an exemplary embodiment, the host computer includes: a second storage unit, configured to store N groups of test information of the CPU under test, and each of the N groups of test information is used to represent the first test result and the second test result corresponding to the CPU under test under the test conditions of each of the N value pairs.

[0022] According to another embodiment of the present application, a CPU testing device is provided, including: a first determination module, configured to determine a first parameter range and a second parameter range of a power supply chip of a CPU to be tested, where the first parameter range represents a first value range of a first parameter of the power supply chip, the second parameter range represents a second value range of a second parameter of the power supply chip, the first parameter represents a gain parameter for the power supply chip to adjust current, and the second parameter represents a bias parameter for the power supply chip to adjust current; a second determination module, configured to determine N value pairs according to the first parameter range and the second parameter range, and store the N value pairs in a target storage unit, where each of the N value pairs includes a value in the first value range of the first parameter and a value in the second value range of the second parameter, and N is a positive integer greater than or equal to 2; a first acquisition module, configured to sequentially acquire the value pairs from the N value pairs in the target storage unit, and test the CPU to be tested according to the acquired value pairs to obtain N groups of results.

[0023] According to another embodiment of the present application, a computer-readable storage medium is further provided. A computer program is stored in the computer-readable storage medium, where the computer program is configured to execute the steps in any one of the above method embodiments when running.

[0024] According to another embodiment of the present application, an electronic device is further provided, including a memory and a processor. A computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0025] Through the embodiments of the present application, the host computer determines a first parameter range of the gain parameter for the power supply chip of the CPU to be tested to adjust current and a second parameter range of the bias parameter for the power supply chip to adjust current, determines N value pairs according to the first parameter range and the second parameter range, and stores the N value pairs in the target storage unit, where each of the N value pairs includes a value in the first value range of the first parameter and a value in the second value range of the second parameter. Then, the value pairs in the N value pairs are sequentially acquired from the target storage unit, and the CPU to be tested is tested according to the acquired value pairs to obtain N groups of results. The purpose of automatically acquiring each value pair from the N value pairs and sequentially testing the CPU to be tested to obtain N groups of results is achieved, avoiding the problem of low testing efficiency caused by manually changing the first parameter and the second parameter of the power supply chip and relying on manual acquisition of test data when the CPU is tested multiple times in the related art. Therefore, the technical problem of low efficiency in CPU testing in the related art can be solved, and the effect of improving the efficiency of CPU testing is achieved. Description of the Drawings

[0026] Figure 1 is a schematic diagram of the hardware environment of the CPU testing method according to an embodiment of the present application;

[0027] Figure 2 is a flowchart of the CPU testing method according to an embodiment of the present application;

[0028] Figure 3 is an example diagram of the Imon curve according to an embodiment of the present application;

[0029] Figure 4 is the CPU testing system architecture according to an embodiment of the present application Figure 1 ;

[0030] Figure 5 is the CPU testing system architecture according to an embodiment of the present application Figure 2 ;

[0031] Figure 6 is a diagram of the performance and power consumption tuning testing system architecture according to an embodiment of the present application;

[0032] Figure 7 is a block diagram of the structure of the CPU testing device according to an embodiment of the present application. Detailed Embodiments

[0033] In order to enable those skilled in the art to better understand the solution of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0034] It should be noted that the terms "first", "second", etc. in the specification, claims and above-mentioned drawings of the present application are used to distinguish similar objects, and do not necessarily need to describe a specific order or sequence. It should be understood that such data used may be interchanged under appropriate circumstances so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device including a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0035] The method embodiments provided by the embodiments of the present application can be executed on a server, a computer terminal, a device terminal, or a similar computing device. Taking running on a server as an example, Figure 1 is a schematic diagram of the hardware environment of a server for a CPU testing method according to an embodiment of the present application. As Figure 1 shown, the server may include one or more ( Figure 1 only one is shown in the figure) processors 102 (the processor 102 may include, but is not limited to, a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 104 for storing data. In an exemplary embodiment, the above server may further include a transmission device 106 for communication functions and an input / output device 108. Those of ordinary skill in the art can understand that Figure 1 the structure shown is only illustrative and does not limit the structure of the above server. For example, the server may further include more or fewer components than Figure 1 shown in the figure, or have the same functions as Figure 1 shown in the figure or different configurations with more functions than Figure 1 shown in the figure.

[0036] The memory 104 can be used to store computer programs. For example, software programs and modules of application software, such as the computer program corresponding to the CPU testing method in the embodiments of the present invention. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, that is, implements the above method. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memories, or other non-volatile solid-state memories. In some instances, the memory 104 may further include a memory remotely provided with respect to the processor 102, and these remote memories can be connected to the server through a network. Examples of the above network include, but are not limited to, the Internet, an enterprise intranet, a local area network, a mobile communication network, and combinations thereof.

[0037] The transmission device 106 is used to receive or send data via a network. Specific examples of the above network may include a wireless network provided by a communication provider of the server. In one instance, the transmission device 106 includes a network adapter (abbreviated as NIC), which can be connected to other network devices through a base station and thus can communicate with the Internet. In one instance, the transmission device 106 may be a radio frequency (abbreviated as RF) module, which is used to communicate with the Internet wirelessly.

[0038] In this embodiment, a CPU testing method is provided. Figure 2is a flowchart of a CPU testing method according to an embodiment of the present application. As Figure 2 shown, the process includes the following steps:

[0039] Step S202, the host computer determines a first parameter range and a second parameter range of the power supply chip of the CPU to be tested. Among them, the first parameter range represents the first value range of the first parameter of the power supply chip, the second parameter range represents the second value range of the second parameter of the power supply chip, the first parameter represents the gain parameter for adjusting the current of the power supply chip, and the second parameter represents the bias parameter for adjusting the current of the power supply chip;

[0040] Step S204, the host computer determines N value pairs according to the first parameter range and the second parameter range, and stores the N value pairs in the target storage unit. Among them, each of the N value pairs includes a value in the first value range of the first parameter and a value in the second value range of the second parameter, and N is a positive integer greater than or equal to 2;

[0041] Step S206, the host computer sequentially obtains the value pairs in the N value pairs from the target storage unit, and tests the CPU to be tested according to the obtained value pairs to obtain N groups of results.

[0042] Through the above steps, the host computer determines the first parameter range of the gain parameter for adjusting the current of the power supply chip of the CPU to be tested and the second parameter range of the bias parameter for adjusting the current of the power supply chip, determines N value pairs according to the first parameter range and the second parameter range, and stores the N value pairs in the target storage unit. Among them, each of the N value pairs includes a value in the first value range of the first parameter and a value in the second value range of the second parameter. Then, the host computer sequentially obtains each of the N value pairs from the target storage unit, and tests the CPU to be tested according to the obtained value pairs to obtain N groups of results. The purpose of automatically obtaining each value pair from the N value pairs and sequentially testing the CPU to be tested to obtain N groups of results is achieved, avoiding the problems in the related art that when the CPU is tested multiple times, it is necessary to manually change the first parameter and the second parameter of the power supply chip and rely on manual collection of test data, resulting in low test efficiency. Therefore, the technical problem of low efficiency in CPU testing in the related art can be solved, and the effect of improving the efficiency of CPU testing is achieved.

[0043] Among them, the execution subject of the above steps can be a terminal, such as a PC, or the above host computer, but not limited thereto.

[0044] In the technical solution provided in the above step S202, the host computer determines the first parameter range and the second parameter range of the power supply chip of the CPU to be tested, that is, determines the first value range of the first parameter of the power supply chip (such as the gain Gain parameter for adjusting the current of the power supply chip) and the second value range of the second parameter of the power supply chip (such as the offset Offset parameter for adjusting the current of the power supply chip). Since the Imon curve of the CPU has a certain SPEC standard range, the upper deviation and lower deviation of the Imon curve of the CPU within the SPEC range have a greater impact on the performance and power consumption of the CPU. The Imon curve represents the curve between the first current value provided by the power supply chip monitored by the CPU (such as the above CPU to be tested) and the second current value actually output by the power supply chip. If the values of the first parameter and the second parameter of the power supply chip are different, the obtained Imon curve may also be different. Even if the value of the first parameter or the second parameter is not appropriate, the corresponding Imon curve may exceed the SPEC standard range. Therefore, it is necessary to determine the first parameter range and the second parameter range of the power supply chip. In practical applications, the first value range of the first parameter and the second value range of the second parameter can be determined according to the SPEC standard range of the Imon curve. For example, Figure 3 as shown Figure 3 in the Imon curve example diagram according to the embodiment of the present application, Figure 3 where the red curve corresponds to the first reference curve within the SPEC standard range, and the green curve corresponds to the second reference curve within the SPEC standard range. Generally, the Imon curve of the CPU is approximately a straight line with a slope, such as y = Gain * I + Offset, as Figure 3 shown by the middle gray curve in the figure. Here, y represents the current value provided by the power supply chip monitored by the CPU (such as the above CPU to be tested), or the value in the CPU register (i.e., the current value considered by the CPU), which can also be represented by Iout. I represents the current value actually output by the power supply chip, or the actually loaded current value. In this way, the first value range of the first parameter (Gain parameter) and the second value range of the second parameter (Offset parameter) can be determined according to the first reference curve and the second reference curve.

[0045] In the technical solution provided in the above step S204, the host computer can determine N value pairs according to the first parameter range and the second parameter range, and store the N value pairs in the target storage unit. If the first parameter range is [G1, G2] and the second parameter range is [F1, F2], for example, P values can be taken from the first parameter range [G1, G2], Q values can be taken from the second parameter range [F1, F2], and then N value pairs are obtained by combining the P values of the first parameter and the Q values of the second parameter; optionally, P values can be taken from the first parameter range [G1, G2] at a first predetermined step size, and Q values can be taken from the second parameter range [F1, F2] at a second predetermined step size to obtain N value pairs; N value pairs can also be obtained by other methods. It should be noted that in practical applications, when determining N value pairs, it is necessary to ensure that the Imon curve of the CPU obtained under the conditions of the first parameter and the second parameter corresponding to each value pair in the N value pairs is within the SPEC standard range.

[0046] In the technical solution provided in the above step S206, the host computer can sequentially obtain each value pair in the N value pairs from the above target storage unit, and test the CPU to be tested according to each value pair. For example, the host computer can control the test of the CPU to be tested through a target program (or test script). In practical applications, the host computer can burn the program into the power supply chip to implement the setting of the first parameter and the second parameter of the power supply chip. Optionally, after obtaining the test result of the CPU to be tested corresponding to a certain current value pair, the host computer can automatically obtain the next value pair and continue to test the CPU to be tested. Through this embodiment, the purpose of sequentially configuring multiple groups of first parameters and second parameters for the power supply chip by the host computer and sequentially obtaining multiple groups of results is achieved. That is, the purpose of automatically obtaining each value pair from the N value pairs and sequentially testing the CPU to be tested to obtain N groups of results is achieved, avoiding the problem of low test efficiency caused by the need to manually change the first parameter and the second parameter of the power supply chip and relying on manual collection of test data when the CPU is tested multiple times in the related art. Therefore, the technical problem of low efficiency in CPU testing existing in the related art can be solved, and the effect of improving the efficiency of CPU testing is achieved.

[0047] In an optional embodiment, the host computer determines a first parameter range and a second parameter range of the power supply chip of the CPU to be tested, including: obtaining a first reference curve and a second reference curve, where the first reference curve is used to represent the upper limit of the current value allowed for the current value provided by the power supply chip monitored by the CPU to be tested when the actual output current value of the power supply chip is different values in a target current value range, and the second reference curve is used to represent the lower limit of the current value allowed for the current value provided by the power supply chip monitored by the CPU to be tested when the actual output current value of the power supply chip is different values in the target current value range; determining the first parameter range and the second parameter range according to the first reference curve and the second reference curve, where M value pairs composed of each value of the first parameter in the first parameter range and each value of the second parameter in the second parameter range satisfy a target preset condition, and the target preset condition includes: when the power supply chip supplies power to the CPU to be tested according to the values of the first parameter and the second parameter in the i-th value pair, and when the actual output current value of the power supply chip is the i-th current value in the target current value range, the current value provided by the power supply chip monitored by the CPU to be tested is between the upper limit and the lower limit of the current value corresponding to the i-th current value, where M is a positive integer greater than or equal to 2, and i is a positive integer greater than or equal to 1 and less than or equal to M.

[0048] Optionally, in this embodiment, the first reference curve and the second reference curve can be obtained by referring to the SPEC standard range of the Imon curve, as Figure 3 shown, Figure 3 the red curve in corresponds to the first reference curve of the SPEC standard range, and the green curve corresponds to the second reference curve of the SPEC standard range, Figure 3The abscissa corresponds to the actual output current value of the power supply chip, and the ordinate corresponds to the current value provided by the power supply chip monitored by the CPU under test. The first reference curve represents the upper limit of the allowable current value of the current value provided by the power supply chip monitored by the CPU under test when the actual output current value of the power supply chip is different values within the target current value range. The second reference curve represents the lower limit of the allowable current value of the current value provided by the power supply chip monitored by the CPU under test when the actual output current value of the power supply chip is different values within the target current value range. For example, if the target current value range is 0 - 450A (or other ranges), taking the actual output current value of the power supply chip equal to 200A as an example, the upper limit of the allowable current value of the current value provided by the power supply chip monitored by the CPU under test is 210A (or other values), and the lower limit of the allowable current value is 190A (or other values). Similarly, for other current values within the target current value range of the actual output current value of the power supply chip, there is also a corresponding upper limit and lower limit of the current value. Usually, the Imon curve of the CPU is approximately a straight line. For example, y = Gain * I + Offset, such as Figure 3 In the middle, there is a gray curve. y represents the current value provided by the power supply chip monitored by the CPU (such as the CPU under test above), or the value in the CPU register (i.e., the current value considered by the CPU). I represents the actual output current value of the power supply chip, or the actual loaded current value. In this way, the first parameter interval of the first parameter (Gain parameter) and the second parameter interval of the second parameter (Offset parameter) can be determined according to the first reference curve and the second reference curve. Among them, each value of the first parameter in the first parameter interval and each value of the second parameter in the second parameter interval form M value pairs. When the power supply chip is under the conditions of the value of the first parameter and the value of the second parameter corresponding to any one of the M value pairs, the Imon curve of the CPU under test needs to be between the first reference curve and the second reference curve. For example, taking Figure 3 the middle gray curve as an example, if the values of the first parameter and the second parameter corresponding to the Imon curve are Gain0 and Offset0 respectively, then by adjusting the value of Gain, that is, changing Figure 3 the slope of the gray curve in the middle, but it is necessary to ensure that the adjusted Imon curve (i.e., the corresponding Figure 3 gray curve in the middle) is within the range of the first reference curve and the second reference curve. Similarly, by adjusting the value of Offset, that is, changing Figure 3 the intersection point of the gray curve in the middle and the vertical axis, it is also necessary to ensure that the adjusted Imon curve (i.e., the corresponding Figure 3The medium gray curve) is within the first reference curve and the second reference curve. According to this method, the above-mentioned first parameter interval and second parameter interval can be obtained. Through this embodiment, the purpose of determining the first parameter interval and the second parameter interval according to the first reference curve and the second reference curve is achieved.

[0049] In an optional embodiment, the host computer determines the first parameter interval and the second parameter interval of the power supply chip of the CPU to be measured, including: obtaining a first reference curve and a second reference curve, wherein the first reference curve is used to represent the upper limit of the current value allowed for the current value provided by the power supply chip monitored by the CPU to be measured when the actual output current value of the power supply chip is different values within the target current value interval, and the second reference curve is used to represent the lower limit of the current value allowed for the current value provided by the power supply chip monitored by the CPU to be measured when the actual output current value of the power supply chip is different values within the target current value interval; obtaining a first initial value of the first parameter and a second initial value of the second parameter; determining the first parameter interval according to the first reference curve, the second reference curve and the second initial value, wherein each of the P numerical pairs formed by each numerical value of the first parameter in the first parameter interval and the second initial value satisfies a target preset condition, and the target preset condition includes: when the power supply chip supplies power to the CPU to be measured according to the numerical value of the first parameter and the numerical value of the second parameter in the jth numerical pair, and when the actual output current value of the power supply chip is the jth current value within the target current value interval, the current value provided by the power supply chip monitored by the CPU to be measured is between the upper limit and the lower limit of the current value corresponding to the jth current value, where P is a positive integer greater than or equal to 1; determining the second parameter interval according to the first reference curve, the second reference curve and the first initial value, wherein each of the Q numerical pairs formed by the first initial value and each numerical value of the second parameter in the second parameter interval satisfies the target preset condition, where Q is a positive integer greater than or equal to 1.

[0050] Optionally, in this embodiment, a first reference curve and a second reference curve within the SPEC standard range of the Imon curve can be obtained, and a first initial value of the first parameter and a second initial value of the second parameter can be obtained. Assuming that the first initial value of the first parameter is Gain0 and the second initial value of the second parameter is Offset0, in practical applications, the first initial value and the second initial value can be based on the reference values (or recommended values) provided by the power supply chip manufacturer or in the specification. In this way, the Imon curve of the CPU to be measured under the condition that the first parameter of the power supply chip is Gain0 and the second parameter is Offset0 can be obtained, which is equivalent to Figure 3A gray curve in the middle, and then, according to the first reference curve, the second reference curve, and the second initial value, determine the first parameter interval. That is, with the second initial value unchanged, change the slope of the Imon curve (approximately a straight line), i.e., the Gain parameter value, and ensure that the Imon curve is between Figure 3 the first reference curve and the second reference curve in it, so as to obtain the first parameter interval; similarly, the first initial value can be fixed and the Offset parameter value can be changed, which is equivalent to translating Figure 3 the gray curve in it, but it is necessary to ensure that the Imon curve is between Figure 3 the first reference curve and the second reference curve in it, so as to obtain the second parameter interval. Through this embodiment, the purpose of determining the first parameter interval and the second parameter interval according to the first reference curve, the second reference curve, the first initial value of the first parameter, and the second initial value of the second parameter is achieved.

[0051] In an optional embodiment, the host computer determines N value pairs according to the first parameter interval and the second parameter interval, including: obtaining R values of the first parameter from the first parameter interval according to a first predetermined step size, and obtaining S values of the second parameter from the second parameter interval according to a second predetermined step size, where R is a positive integer greater than or equal to 1, and S is a positive integer greater than or equal to 1; combining each value in the R values with each value in the S values to obtain the N value pairs, where N = R * S.

[0052] Optionally, in this embodiment, when the first parameter interval and the second parameter interval are determined, R values of the first parameter can be obtained from the first parameter interval according to a first predetermined step size, and S values of the second parameter can be obtained from the second parameter interval according to a second predetermined step size, and then the R values and the S values are combined to obtain N value pairs. For example, any one of the R values of the first parameter is combined with each of the S values of the second parameter one by one to obtain S value pairs, and so on, N value pairs can be obtained; R and S can be equal or not equal, and the values of R and S can be set according to actual needs. In practical applications, the host computer can program according to the first parameter interval and the second parameter interval to reasonably set the above first predetermined step size and second predetermined step size to obtain multiple value pairs, that is, obtain multiple sets of values of the first parameter and the second parameter, and each set of values of the first parameter and the second parameter can correspond to an Imon curve. Through this embodiment, the host computer can determine N value pairs through a program and automatically test the CPU to be measured according to the N value pairs in turn to obtain N groups of results, achieving the effect of improving the CPU test efficiency.

[0053] In an optional embodiment, the host computer sequentially obtains the value pairs in the N value pairs from the target storage unit, and tests the CPU under test according to the obtained value pairs, obtaining N groups of results, including: the host computer sequentially obtains each of the N value pairs in the N value pairs from the target storage unit, and respectively performs a performance test and a stress test on the CPU under test, obtaining N first test results and N second test results, where the first test results include the performance score of the CPU under test, and the second test results include the power consumption values of the CPU under test, and each group of the N groups of results includes the first test result and the second test result obtained according to a corresponding value pair.

[0054] Optionally, in this embodiment, according to each of the N value pairs, a performance test and a stress test are respectively performed on the CPU under test to obtain N first test results and N second test results, that is, each value pair corresponds to a first test result and a second test result. The first test results may include the performance score of the CPU under test, and the second test results include the power consumption values of the CPU under test. Each group of the N groups of results includes a first test result and a second test result, and each group of results corresponds to one of the N value pairs. Through this embodiment, the purpose of respectively performing a performance test and a stress test on the CPU under test according to each of the N value pairs is achieved, and the test results respectively corresponding to the CPU under test under different test conditions are automatically obtained, achieving the effect of improving the CPU test efficiency.

[0055] In an optional embodiment, after obtaining the N groups of results, the method further includes: respectively combining each of the N value pairs with the results of each group in the corresponding N groups of results to form a group of test information of the CPU under test, obtaining N groups of test information, where each group of the N groups of test information is used to represent the first test result and the second test result obtained when the first parameter and the second parameter are the values in each of the N value pairs; classifying the N groups of test information to obtain M types of energy consumption information, where each type of energy consumption information in the M types of energy consumption information includes one or more groups of test information, and the performance scores and / or the power consumption values corresponding to different types of energy consumption information in the M types of energy consumption information belong to different value ranges; importing the M types of energy consumption information into the basic input / output system BIOS, where the M types of energy consumption information in the BIOS are set to be selectable.

[0056] Optionally, in this embodiment, after obtaining N groups of results, each value pair in the N value pairs and the corresponding groups of results can be combined into the test information of the CPU to be tested. For example, the test results obtained by the CPU to be tested under the test conditions of a value pair (i.e., a corresponding Gain parameter and Offset parameter), such as including the first test result and the second test result, are combined into a group of test information. In this way, N groups of test information can be obtained. Further, the N groups of test information can be classified to obtain M types of energy consumption information. For example, the CPU to be tested can be classified according to the performance score and power consumption value of the CPU to be tested. For example, the M types of energy consumption information can include high-performance types, and this high-performance type can include one or more groups of test information. Or, the M types of energy consumption information can include low-power types, and this low-power type can include one or more groups of test information. Or, the M types of energy consumption information can include relatively balanced power consumption and performance types. In practical applications, classification can be performed according to needs. Optionally, the M types of energy consumption information can be imported into the BIOS. For example, BIOS options can be set, so that users can quickly and conveniently select options according to the requirements of performance and power consumption. Optionally, the server can automatically adjust or select the Gain parameter and Offset parameter corresponding to different groups of test information according to the detected different events, and enable the power chip to supply power to the CPU according to the Gain parameter and Offset parameter. Through this embodiment, the purpose of setting multiple types of energy consumption information according to the test results to select or optimize the parameters of the power chip is achieved.

[0057] In an alternative embodiment, the host computer sequentially obtains the value pairs in the N value pairs from the target storage unit, and tests the CPU to be tested according to the obtained value pairs to obtain N groups of results, including: obtaining the kth group of results in the N groups of results by performing the following steps, where k is a positive integer greater than or equal to 1 and less than or equal to N: obtaining the kth value pair in the N value pairs from the target storage unit; writing the kth value pair into the power chip of the CPU to be tested, and instructing the power chip to supply power to the CPU to be tested according to the values of the first parameter and the second parameter corresponding to the kth value pair; when the power chip supplies power to the CPU to be tested according to the values of the first parameter and the second parameter corresponding to the kth value pair, performing a performance test and a stress test on the CPU to be tested to obtain the kth group of results, where the kth group of results includes the performance score of the CPU to be tested and the power consumption value of the CPU to be tested.

[0058] Optionally, in this embodiment, for N value pairs, each value pair in the N value pairs can be automatically cyclically obtained, and the parameters of the power supply chip corresponding to each value pair (i.e., the Gain parameter and the Offset parameter) are respectively written into the power supply chip, and the power supply chip is instructed to supply power to the CPU under test according to the parameters, and perform performance testing and stress testing on the CPU under test. For example, the host computer can write the value pairs of the first parameter and the second parameter for configuring the power supply chip into the power supply chip through a program burner (or a burning fixture). Through this embodiment, the purpose of automatically cyclically obtaining each value pair in the N value pairs and respectively testing the CPU under test to obtain N groups of results can be achieved.

[0059] In an optional embodiment, after obtaining the N groups of results, the method further includes: adjusting the first parameter and / or the second parameter of the power supply chip of the CPU under test according to the N groups of results.

[0060] Optionally, in this embodiment, after obtaining the N groups of results, the first parameter and / or the second parameter of the power supply chip of the CPU under test can also be adjusted according to the N groups of results. For example, when the CPU under test obtains a test result of high power consumption under the test conditions of the current values of the first parameter and the second parameter, and if it is necessary to reduce the power consumption of the CPU under test, the first parameter and / or the second parameter of the power supply chip of the CPU under test can be adjusted according to the N groups of results; or, the first parameter and / or the second parameter of the power supply chip can be adjusted according to the N groups of test information in the foregoing embodiment. Similarly, if it is necessary to adjust the performance of the CPU under test, the first parameter and / or the second parameter of the power supply chip can also be adjusted according to the N groups of results or the N groups of test information.

[0061] In this embodiment, a CPU test system is also provided. Figure 4 It is the architecture diagram of the CPU test system according to the embodiment of the present application, as Figure 4 shown. The system includes:

[0062] The host computer 402 is configured to determine a first parameter range and a second parameter range of the power supply chip of the CPU to be tested, and determine N value pairs according to the first parameter range and the second parameter range, and store the N value pairs in a target storage unit, where the first parameter range represents a first value range of a first parameter of the power supply chip, the second parameter range represents a second value range of a second parameter of the power supply chip, the first parameter represents a gain parameter for adjusting the current of the power supply chip, the second parameter represents a bias parameter for adjusting the current of the power supply chip, each of the N value pairs includes a value in the first value range of the first parameter and a value in the second value range of the second parameter, and N is a positive integer greater than or equal to 2;

[0063] The server 404 is connected to the host computer 402, and the server includes the CPU to be tested and the power supply chip ( Figure 4 not shown in the figure) and is configured to sequentially obtain the value pairs in the N value pairs from the target storage unit, and test the CPU to be tested according to the obtained value pairs to obtain N groups of results.

[0064] Through the above system, the host computer determines the first parameter range of the gain parameter for adjusting the current of the power supply chip of the CPU to be tested and the second parameter range of the bias parameter for adjusting the current of the power supply chip, determines N value pairs according to the first parameter range and the second parameter range, and stores the N value pairs in the target storage unit, where each of the N value pairs includes a value in the first value range of the first parameter and a value in the second value range of the second parameter, then sequentially obtains each of the N value pairs from the target storage unit, and tests the CPU to be tested in the server according to the obtained value pairs to obtain N groups of results. The purpose of automatically obtaining each value pair from the N value pairs and sequentially testing the CPU to be tested to obtain N groups of results is achieved, avoiding the problem in the related art that when the CPU is tested multiple times, it is necessary to manually change the first parameter and the second parameter of the power supply chip and rely on manual collection of test data, resulting in low test efficiency. Therefore, the technical problem of low efficiency in CPU testing in the related art can be solved, and the effect of improving the efficiency of CPU testing is achieved.

[0065] In an optional embodiment, the system further includes: a test tool connected to the power supply test board, the test tool being configured to test the power supply chip of the CPU under test to obtain a target curve, wherein the power supply chip is installed on the power supply test board, and the target curve is used to represent the curve between the first current value monitored by the CPU under test provided by the power supply chip and the second current value actually output by the power supply chip when the first parameter is equal to the first initial value and the second parameter is equal to the second initial value.

[0066] Optionally, in this embodiment, as Figure 5 shown, the above system further includes a test tool 406 and a power supply test board 408. The test tool is connected to the power supply test board, and the power supply chip is installed on the power supply test board. For example, the test tool can be a VRTT test tool, and the Imon curve (such as the above target curve) of the power supply chip can be measured through the VRTT test tool. For example, the Imon curve is the curve between the first current value monitored by the CPU under test provided by the power supply chip and the second current value actually output by the power supply chip when the first parameter (such as the gain parameter of the power supply chip for adjusting the current) of the power supply chip is equal to the first initial value and the second parameter (such as the offset parameter of the power supply chip for adjusting the current) is equal to the second initial value. In practical applications, the first parameter interval and the second parameter interval can be determined based on the above target curve.

[0067] In an optional embodiment, the host computer includes: a debugging software unit configured to set the first parameter of the power supply chip to the first initial value and set the second parameter of the power supply chip to the second initial value through a program burner, and instruct the test tool to obtain the target curve; or the debugging software unit is further configured to sequentially write each of the N value pairs in the power supply chip in the server through the program burner, and instruct the power supply chip to supply power to the CPU under test in accordance with the values of the first parameter and the second parameter corresponding to each of the N value pairs in sequence.

[0068] Optionally, in this embodiment, the debugging software unit in the host computer can be used to write the configuration parameters of the power supply chip (such as the first initial value of the first parameter and the second initial value of the second parameter) into the power supply chip through a program burner (or a burning fixture). In practical applications, the power supply chip of the CPU under test can be tested through a power supply test board and test tools to obtain a target curve; alternatively, after determining N value pairs, the host computer uses the debugging software unit to write each value pair in the N value pairs into the power supply chip of the CPU under test in the server in sequence through a program burner. For example, after obtaining the test result of the CPU under test corresponding to a certain current value pair, the host computer can automatically obtain the next value pair and write the value of the first parameter and the value of the second parameter corresponding to the next value pair into the power supply chip to instruct the power supply chip to supply power to the CPU under test according to the value of the first parameter and the value of the second parameter corresponding to the next value pair, and then continue to test the CPU under test.

[0069] In an optional embodiment, the system further includes: a power meter, connected to the server and the host computer, and the power meter is configured to test the second test result of the CPU under test in each of the N value pairs to obtain N second test results, where the second test result includes the power consumption value of the CPU under test, and each group of results in the N groups of results includes one of the second test results.

[0070] Optionally, in this embodiment, the power meter can be used to obtain the second test result of the CPU under test when the first parameter and the second parameter of the power supply chip are respectively each value pair. For example, the second test result is the power consumption information of the CPU under test or the system. At the same time, the power meter can also transmit the power consumption information to the host computer.

[0071] In an optional embodiment, the host computer includes: a virtual system unit, configured to test the CPU under test in the server through a target script to obtain the N groups of results.

[0072] Optionally, in this embodiment, the host computer may include a virtual system unit, and this virtual system unit is used to establish a connection with the server through a target scripting language and perform control to achieve the purpose of testing the CPU under test.

[0073] In an alternative embodiment, the virtual system unit includes: a first window configured to perform a performance test on the CPU under test through a first test script to obtain N first test results, where the first test results include the performance score of the CPU under test; a second window configured to perform a stress test on the CPU under test through a second test script to obtain N second test results, where the second test results include the power consumption value of the CPU under test; the target script includes the first test script and the second test script, and each set of the N sets of results includes the first test result and the second test result obtained by the CPU under test under the same parameter pair.

[0074] Optionally, in this embodiment, the virtual system unit may include a first window and a second window. For example, the first window is a performance test script of SPECCPU, and the second window is a PTU pressure test script of the CPU. The host computer controls the operation of the first window and the second window to obtain the performance test results of the operation of the first window, such as the performance score; run the PTU pressure test program of the second window, and obtain the system power consumption value by collecting and reading the data of the power meter.

[0075] In an alternative embodiment, the host computer includes: a second storage unit configured to store N sets of test information of the CPU under test, and each set of test information in the N sets of test information is used to represent the first test result and the second test result corresponding to the CPU under test under the test conditions of each value pair in the N value pairs.

[0076] Optionally, in this embodiment, the N sets of test information can be stored in the second storage unit, that is, under the test conditions of the values of the first parameter and the second parameter corresponding to each value pair of the power supply chip, the first test result and the second test result of the CPU under test are respectively stored in the second storage unit. Each value pair corresponds to a first test result and a second test result. In this way, a value pair and a corresponding first test result and a second test result can form a set of test information, and this set of test information can be stored in the second storage unit. By analogy, the N sets of test information corresponding to the N value pairs can be stored in the second storage unit.

[0077] Obviously, the above-described embodiments are only part of the embodiments of the present invention, not all of them. The present invention will be specifically described below in conjunction with the embodiments.

[0078] The embodiments of the present application provide a technical solution for a performance and power consumption tuning test system. The overall technical solution is as follows:

[0079] At the software level, develop a host computer system based on Python or other programming languages. The host computer system includes a VR software debugging unit, a server virtual system unit, and a data storage and analysis unit.

[0080] At the hardware level, the server's entire system establishes a communication connection with the host computer PC through a network port. The host computer can control the window operation of the server's entire system and capture the running data through a Python script. The VR debugging software uses a VR programming fixture (USB to I2C interface) to connect to the main board of the server's entire system to establish communication.

[0081] The server's entire system can be connected to the AC220V power supply through a power meter. At the same time, the power meter establishes a communication relationship with the host computer through a USB interface. The power supply test board can separately establish communication with the host computer through the VR TT tool via a USB cable. At the same time, the VR debugging software uses a VR programming fixture (USB to I2C interface) to connect to the main board of the power supply test board to establish communication.

[0082] The embodiment of this application proposes an automatic tuning test platform system for the performance and power consumption of a programmable Imon controlled by a host computer. The specific system architecture is as Figure 6 shown. The following is an explanation of this system architecture.

[0083] I. The main features of this system architecture diagram are as follows:

[0084] 1) Host computer: That is, the PC. At the software level, it includes a server virtual system unit, a VR debugging software unit, and a data storage and analysis unit. It can be implemented by Python or other programs;

[0085] 2) Hardware level: The host computer establishes a communication connection with the server's entire system through a network port; the host computer establishes a communication connection with the power analyzer through a USB interface; the host computer uses a VR programming fixture (USB to I2C) to establish communication with the VR chip of the server's entire system or the power supply test main board; the server PSU is connected to the 220V AC power supply through a power analyzer;

[0086] 3) Server virtual system unit: Controlled by the host computer to establish a connection through a scripting language. Window 1 is the performance test script of SPECCPU, and window 2 is the PTU voltage boosting test script of the CPU. The host computer controls the operation of windows 1 and 2, and at the same time obtains the benchmark result data of window 1 running; runs the PTU voltage boosting test program of window 2, and obtains the system power consumption value by collecting and reading the data of the power meter;

[0087] 4) As Figure 6, the host computer system uses the VR software debugging unit to first obtain the upper and lower limit ranges of the parameters gain&offset that affect the Imon curve through the power supply test board and the VR Tool;

[0088] 5) The host computer system programs through a programming language, fixes one parameter gain (corresponding to the aforementioned first parameter), and cyclically changes the other parameter offset (corresponding to the aforementioned second parameter) to generate a set of gain&offset parameter values (corresponding to the aforementioned N value pairs), runs the server virtual system unit, obtains the performance running score corresponding to this set of parameters (corresponding to the aforementioned first test result), writes it into the data storage and analysis unit, runs the PTU pressure test to obtain power consumption information (corresponding to the aforementioned second test result), and writes it into the data analysis unit;

[0089] 6) The data storage and analysis unit: can be in the format of an EXCEL table, and the python language is used to obtain the performance running score and power consumption value and fill them into the excel table.

[0090] II. Main Features of Imon Curve Adjustment

[0091] 1) The main influencing factors of the Imon curve are the gain and offset parameters in the chip;

[0092] 2) The programmable parameters of the Imon curve are the chip gain and offset values;

[0093] 3) For example Figure 3 the Imon curve is similar to an oblique straight line. Gain mainly affects the slope of the straight line, and offset affects the value of the vertical axis; establish the Imon curve mathematical model y = gain*I + offset; y is Iout, the value in the CPU register is the current value considered by the CPU, and I is the actual loaded current value;

[0094] 4) The range values of gain and offset can be determined through the upper and lower limit values of the Imon curve;

[0095] 5) After obtaining the range values of gain and offset, the program programming reasonably sets the step sizes of gain and offset according to the upper and lower limit ranges of gain and offset, obtains multiple sets of gain and offset values, and each set of values corresponds to an Imon curve and a set of performance and power consumption values.

[0096] III. Power Consumption Data Acquisition

[0097] 1) After the CPU PTU pressure test runs, due to the limited manual data collection before, the collected power consumption has a large gap and is inaccurate. The upper computer Python reads the power consumption value, and within 30 minutes, a power consumption data value can be obtained every 10s. After deleting 10 highest values and 10 lowest values, for the remaining 160 data, a more accurate power consumption value can be obtained through the average algorithm.

[0098] The steps of performance and power consumption tuning test in the embodiments of the present application will be described in detail below.

[0099] Step 1: Build the upper computer system red frame (corresponding to the middle part, that is, the upper computer system) and the black frame (corresponding to the power supply test board, server and power meter in Figure 6 as shown, that is, the two environments); Figure 6 in Figure 6

[0100] Step 2: Through the upper computer system, use the power supply test board to determine the parameter range and programming rules of the programmable Imon (using the dichotomy method) to quickly and efficiently perform power consumption and performance tests;

[0101] Step 3: If the hardware is such that the performance and power consumption automation tuning test platform for the server whole machine system is built as in Figure 6 , then write the multiple sets of gain & offset values corresponding to multiple sets of Imon curves within the intel SPEC range set by programming into the server motherboard in sequence. The upper computer system calls the VR software debugging unit to write into the server power supply chip, and then calls the server virtual system unit to obtain the performance and power consumption data values;

[0102] Step 4: Fill in the same row of the excel table with this set of gain & offset values, the corresponding measured power consumption value, and the performance score value;

[0103] Step 5: After obtaining the power consumption and performance values corresponding to a set of gain & offset, write another set of gain & offset values into the server automatically through the VR debugging software unit according to the loop - set gain and offset parameter values, and then automatically call the server virtual system unit to obtain the performance and power consumption values, and loop in sequence;

[0104] Step 6: After all the data is automatically run, view the excel table exported by the data storage unit to obtain the power consumption and performance values corresponding to all Imon curves set by the loop rule within the SPEC range. At the same time, automatically judge the Imon parameters corresponding to the highest performance, the lowest power consumption, and the performance - power consumption balance for the data in the score - power consumption excel table.

[0105] Step 7: The result table of performance and power consumption tuning can be provided to the customer. According to the customer's requirements for performance and power consumption, the Imon parameters can be selected in reverse.

[0106] Through the above embodiments, an automatic tuning test system for the performance and power consumption of a programmable Imon controlled by a host computer is provided, which can solve the problem of low test efficiency in the related art using a manual solution. Compared with the related art, the embodiments of the present application have the following beneficial effects: 1) The SPECCPU performance and CPU PTU boost power consumption tests can be automatically performed under the control of the host computer system; 2) According to the Imon curve principle, a mathematical model of the Imon curve is established, and a loop principle for the programmable Imon is established; 3) Automatically obtain more accurate power consumption values for CPU PTU boost; 4) Automatically export the performance and power consumption values corresponding to each group of Imon parameters, and can automatically select the Imon parameters corresponding to high performance, low power consumption, and power consumption performance balance.

[0107] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by means of software plus a necessary general hardware platform. Of course, it can also be implemented by hardware, but in many cases, the former is a better implementation method. Based on such an understanding, the technical solution of the embodiments of the present application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. The computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes several instructions for causing a terminal device (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods described in the various embodiments of the present application.

[0108] In this embodiment, a CPU test device is also provided, which is located in the host computer. Figure 7 is the structural block diagram of the CPU test device according to the embodiment of the present application, as Figure 7 shown. The device includes:

[0109] A first determination module 702, configured to determine a first parameter range and a second parameter range of a power supply chip of a CPU to be tested, where the first parameter range represents a first value range of a first parameter of the power supply chip, the second parameter range represents a second value range of a second parameter of the power supply chip, the first parameter represents a gain parameter for adjusting the current of the power supply chip, and the second parameter represents a bias parameter for adjusting the current of the power supply chip;

[0110] The second determination module 704 is configured to determine N value pairs according to the first parameter range and the second parameter range, and store the N value pairs in a target storage unit, where each of the N value pairs includes a value in the first value range of the first parameter and a value in the second value range of the second parameter, and N is a positive integer greater than or equal to 2;

[0111] The first acquisition module 706 is configured to sequentially acquire the value pairs in the N value pairs from the target storage unit, and test the CPU under test according to the acquired value pairs to obtain N groups of results.

[0112] In an optional embodiment, the first determination module 702 includes: a first acquisition unit, configured to acquire a first reference curve and a second reference curve, where the first reference curve is used to represent the upper limit of the current value allowed for the current value provided by the power supply chip monitored by the CPU under test when the actual output current value of the power supply chip is different values in a target current value range, and the second reference curve is used to represent the lower limit of the current value allowed for the current value provided by the power supply chip monitored by the CPU under test when the actual output current value of the power supply chip is different values in the target current value range; a first determination unit, configured to determine the first parameter range and the second parameter range according to the first reference curve and the second reference curve, where the M value pairs formed by each value of the first parameter in the first parameter range and each value of the second parameter in the second parameter range satisfy a target preset condition, and the target preset condition includes: when the power supply chip supplies power to the CPU under test according to the value of the first parameter and the value of the second parameter in the i-th value pair, and when the actual output current value of the power supply chip is the i-th current value in the target current value range, the current value provided by the power supply chip monitored by the CPU under test is between the upper limit and the lower limit of the current value corresponding to the i-th current value, where M is a positive integer greater than or equal to 2, and i is a positive integer greater than or equal to 1 and less than or equal to M.

[0113] In an alternative embodiment, the above-mentioned first determination module 702 includes: a second acquisition unit, configured to acquire a first reference curve and a second reference curve, where the first reference curve is used to represent the upper limit of the current value allowed for the current value provided by the power supply chip monitored by the CPU under test when the actual output current value of the power supply chip is different values within a target current value range, and the second reference curve is used to represent the lower limit of the current value allowed for the current value provided by the power supply chip monitored by the CPU under test when the actual output current value of the power supply chip is different values within the target current value range; a third acquisition unit, configured to acquire a first initial value of the first parameter and a second initial value of the second parameter; a second determination unit, configured to determine the first parameter range according to the first reference curve, the second reference curve, and the second initial value, where each of the P numerical pairs formed by each numerical value of the first parameter in the first parameter range and the second initial value satisfies a target preset condition, and the target preset condition includes: when the power supply chip supplies power to the CPU under test according to the numerical value of the first parameter and the numerical value of the second parameter in the j-th numerical pair, and when the actual output current value of the power supply chip is the j-th current value within the target current value range, the current value provided by the power supply chip monitored by the CPU under test is between the upper limit and the lower limit of the current value corresponding to the j-th current value, where P is a positive integer greater than or equal to 1; a third determination unit, configured to determine the second parameter range according to the first reference curve, the second reference curve, and the first initial value, where each of the Q numerical pairs formed by the first initial value and each numerical value of the second parameter in the second parameter range satisfies the target preset condition, where Q is a positive integer greater than or equal to 1.

[0114] In an alternative embodiment, the above-mentioned second determination module 704 includes: a fourth acquisition unit, configured to acquire R numerical values of the first parameter from the first parameter range according to a first predetermined step size, and acquire S numerical values of the second parameter from the second parameter range according to a second predetermined step size, where R is a positive integer greater than or equal to 1, and S is a positive integer greater than or equal to 1; a first obtaining unit, configured to combine each of the R numerical values with each of the S numerical values to obtain the N numerical pairs, where N = R * S.

[0115] In an alternative embodiment, the above-mentioned first obtaining module 706 includes: a second obtaining unit, configured to sequentially obtain each of the N value pairs from the target storage unit, and respectively perform a performance test and a stress test on the CPU to be measured, so as to obtain N first test results and N second test results, where the first test result includes the performance score of the CPU to be measured, and the second test result includes the power consumption value of the CPU to be measured, and each group of the N groups of results includes the first test result and the second test result obtained according to a corresponding value pair.

[0116] In an alternative embodiment, the above-mentioned device further includes: a second obtaining module, configured to, after obtaining the N groups of results, respectively form a group of test information of the CPU to be measured by combining each of the N value pairs with the corresponding results in each of the N groups of results, so as to obtain N groups of test information, where each group of test information in the N groups of test information is used to represent the first test result and the second test result obtained when the first parameter and the second parameter are the values in each of the value pairs; a third obtaining module, configured to classify the N groups of test information to obtain M types of energy consumption information, where each type of energy consumption information in the M types of energy consumption information includes one or more groups of test information, and the corresponding performance scores and / or power consumption values in different types of energy consumption information in the M types of energy consumption information belong to different value ranges; an importing module, configured to import the M types of energy consumption information into the Basic Input / Output System (BIOS), where the M types of energy consumption information in the BIOS are set to be selectable.

[0117] In an alternative embodiment, the above-mentioned first obtaining module 706 includes: a third obtaining unit, configured to obtain the kth group of results in the N groups of results by performing the following steps, where k is a positive integer greater than or equal to 1 and less than or equal to N: obtaining the kth value pair among the N value pairs from the target storage unit; writing the kth value pair into the power supply chip of the CPU to be measured, and instructing the power supply chip to supply power to the CPU to be measured according to the values of the first parameter and the second parameter corresponding to the kth value pair; performing a performance test and a stress test on the CPU to be measured when the power supply chip supplies power to the CPU to be measured according to the values of the first parameter and the second parameter corresponding to the kth value pair, so as to obtain the kth group of results, where the kth group of results includes the performance score of the CPU to be measured and the power consumption value of the CPU to be measured.

[0118] In an optional embodiment, the above-mentioned device further includes an adjustment module, configured to adjust the first parameter and / or the second parameter of the power supply chip of the CPU to be measured according to the N sets of results after obtaining the N sets of results.

[0119] It should be noted that the above-mentioned various units or modules can be implemented by software or hardware. For the latter, it can be implemented in the following ways, but not limited thereto: the above-mentioned units or modules are all located in the same processor; or, the above-mentioned various units or modules are respectively located in different processors in any combination form.

[0120] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored. Wherein, the computer program is configured to execute the steps in any one of the above method embodiments when running.

[0121] In an exemplary embodiment, the above-mentioned computer-readable storage medium may include, but is not limited to: various media such as USB flash drives, read-only memories (ROM for short), random access memories (RAM for short), mobile hard disks, magnetic disks or optical discs that can store computer programs.

[0122] An embodiment of the present application further provides an electronic device, including a memory and a processor. A computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0123] In an exemplary embodiment, the above-mentioned electronic device may further include a transmission device and an input / output device. Wherein, the transmission device is connected to the above-mentioned processor, and the input / output device is connected to the above-mentioned processor.

[0124] The specific examples in this embodiment may refer to the examples described in the above embodiments and exemplary embodiments, and will not be repeated here.

[0125] Obviously, those skilled in the art should understand that the above-mentioned modules or steps of the embodiments of the present application can be implemented by a general-purpose computing device. They can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices. They can be implemented by program codes executable by the computing device. Thus, they can be stored in a storage device and executed by the computing device. And in some cases, the steps shown or described can be executed in a different order than here, or they can be separately made into individual integrated circuit modules, or multiple modules or steps among them can be made into a single integrated circuit module to implement. In this way, the embodiments of the present application are not limited to any specific combination of hardware and software.

[0126] The above are only the preferred embodiments of the present application and are not intended to limit the embodiments of the present application. For those skilled in the art, various modifications and changes can be made to the present application. Any modification, equivalent replacement, improvement, etc. made within the principle of the embodiments of the present application shall be included in the protection scope of the embodiments of the present application.

Claims

1. A CPU testing method, characterized in that, Including: The host computer determines a first parameter range and a second parameter range of the power supply chip of the CPU to be tested. Wherein, the first parameter range represents a first value range of a first parameter of the power supply chip, the second parameter range represents a second value range of a second parameter of the power supply chip, the first parameter represents a gain parameter for the power supply chip to adjust the current, and the second parameter represents a bias parameter for the power supply chip to adjust the current; The host computer determines N value pairs according to the first parameter range and the second parameter range, and stores the N value pairs in a target storage unit. Wherein, each of the N value pairs includes a value in the first value range of the first parameter and a value in the second value range of the second parameter, and N is a positive integer greater than or equal to 2; The host computer sequentially obtains the value pairs in the N value pairs from the target storage unit, and tests the CPU to be tested according to the obtained value pairs to obtain N groups of results; The host computer determines the first parameter range and the second parameter range of the power supply chip of the CPU to be tested, including: Obtain a first reference curve and a second reference curve, where the first reference curve and the second reference curve are respectively used to represent the upper limit and the lower limit of the current value allowed for the current value provided by the power supply chip monitored by the CPU to be tested when the actual output current value of the power supply chip is different values in a target current value range; Obtain a first initial value of the first parameter and a second initial value of the second parameter; Determine the first parameter range according to the first reference curve, the second reference curve and the second initial value. Wherein, each of the P value pairs composed of each value of the first parameter in the first parameter range and the second initial value satisfies a target preset condition. The target preset condition includes: when the power supply chip supplies power to the CPU to be tested according to the value of the first parameter and the value of the second parameter in the j-th value pair, and when the actual output current value of the power supply chip is the j-th current value in the target current value range, the current value provided by the power supply chip monitored by the CPU to be tested is between the upper limit and the lower limit of the current value corresponding to the j-th current value. Wherein, P is a positive integer greater than or equal to 1; Determine the second parameter range according to the first reference curve, the second reference curve and the first initial value. Wherein, each of the Q value pairs composed of the first initial value and each value of the second parameter in the second parameter range satisfies the target preset condition, and Q is a positive integer greater than or equal to 1.

2. The method according to claim 1, characterized in that The host computer determines N value pairs according to the first parameter range and the second parameter range, including: Obtain R values of the first parameter from the first parameter range according to a first predetermined step size, and obtain S values of the second parameter from the second parameter range according to a second predetermined step size, where R is a positive integer greater than or equal to 1, and S is a positive integer greater than or equal to 1; Combining each of the R values with each of the S values to obtain the N value pairs, where N = R * S.

3. The method according to claim 1, characterized in that The host computer sequentially obtains the value pairs among the N value pairs from the target storage unit, and tests the CPU under test according to the obtained value pairs to obtain N groups of results, including: The host computer sequentially obtains each of the N value pairs among the N value pairs from the target storage unit, and respectively performs a performance test and a stress test on the CPU under test to obtain N first test results and N second test results. Among them, the first test result includes the performance running score of the CPU under test, and the second test result includes the power consumption value of the CPU under test. Each group of the N groups of results includes the first test result and the second test result obtained according to a corresponding value pair.

4. The method according to claim 3, wherein After obtaining the N groups of results, the method further includes: Combining each of the N value pairs with the results of each group among the corresponding N groups of results to respectively form a group of test information of the CPU under test, obtaining N groups of test information. Among them, each group of the N groups of test information is used to represent the first test result and the second test result obtained when the first parameter and the second parameter are the values in each of the value pairs. Classifying the N groups of test information to obtain M types of energy consumption information. Among them, each type of energy consumption information in the M types of energy consumption information includes one or more groups of test information, and the corresponding performance running scores and / or power consumption values in different types of energy consumption information in the M types of energy consumption information belong to different value ranges. Importing the M types of energy consumption information into the Basic Input / Output System (BIOS), where the M types of energy consumption information in the BIOS are set to be selectable.

5. The method according to claim 1, characterized in that, The host computer sequentially obtains the value pairs among the N value pairs from the target storage unit, and tests the CPU under test according to the obtained value pairs to obtain N groups of results, including: Obtaining the k-th group of results among the N groups of results by performing the following steps, where k is a positive integer greater than or equal to 1 and less than or equal to N: Obtaining the k-th value pair among the N value pairs from the target storage unit; Writing the k-th value pair into the power supply chip of the CPU under test, and instructing the power supply chip to supply power to the CPU under test according to the values of the first parameter and the second parameter corresponding to the k-th value pair; When the power supply chip supplies power to the CPU under test according to the values of the first parameter and the second parameter corresponding to the k-th value pair, performing a performance test and a stress test on the CPU under test to obtain the k-th group of results, where the k-th group of results includes the performance running score of the CPU under test and the power consumption value of the CPU under test.

6. The method according to claim 1, wherein After obtaining the N groups of results, the method further includes: Adjusting the first parameter and / or the second parameter of the power supply chip of the CPU under test according to the N groups of results.

7. A CPU testing system, characterized in that, Including: The host computer is configured to determine a first parameter range and a second parameter range of the power supply chip of the CPU to be tested, and determine N value pairs according to the first parameter range and the second parameter range, and store the N value pairs in a target storage unit, where the first parameter range represents a first value range of a first parameter of the power supply chip, the second parameter range represents a second value range of a second parameter of the power supply chip, the first parameter represents a gain parameter for adjusting the current of the power supply chip, the second parameter represents a bias parameter for adjusting the current of the power supply chip, each of the N value pairs includes a value in the first value range of the first parameter and a value in the second value range of the second parameter, and N is a positive integer greater than or equal to 2; The server is connected to the host computer, and the server includes the CPU to be tested and the power supply chip, and is configured to sequentially obtain the value pairs in the N value pairs from the target storage unit, and test the CPU to be tested according to the obtained value pairs to obtain N groups of results; The host computer is configured to determine the first parameter range and the second parameter range of the power supply chip of the CPU to be tested in the following manner: obtain a first reference curve and a second reference curve, where the first reference curve and the second reference curve are respectively used to represent the upper limit and the lower limit of the current value allowed for the current value provided by the power supply chip monitored by the CPU to be tested when the actual output current value of the power supply chip is different values in the target current value range; obtain a first initial value of the first parameter and a second initial value of the second parameter; determine the first parameter range according to the first reference curve, the second reference curve and the second initial value, where P value pairs formed by each value of the first parameter in the first parameter range and the second initial value satisfy a target preset condition, and the target preset condition includes: when the power supply chip supplies power to the CPU to be tested according to the value of the first parameter and the value of the second parameter in the j-th value pair, and when the actual output current value of the power supply chip is the j-th current value in the target current value range, the current value provided by the power supply chip monitored by the CPU to be tested is between the upper limit and the lower limit of the current value corresponding to the j-th current value, where P is a positive integer greater than or equal to 1; determine the second parameter range according to the first reference curve, the second reference curve and the first initial value, where Q value pairs formed by the first initial value and each value of the second parameter in the second parameter range satisfy the target preset condition, where Q is a positive integer greater than or equal to 1.

8. The system according to claim 7, wherein The system further includes: A test tool, connected to a power supply test board, is configured to test a power supply chip of a CPU under test to obtain a target curve. The power supply chip is installed on the power supply test board. The target curve is used to represent a curve between a first current value monitored by the CPU under test and a second current value actually output by the power supply chip when the first parameter is equal to the first initial value and the second parameter is equal to the second initial value.

9. The system according to claim 8, wherein The host computer includes: A debugging software unit, configured to set the first parameter of the power supply chip to the first initial value and set the second parameter of the power supply chip to the second initial value through a program burner, and instruct the test tool to obtain the target curve; or The debugging software unit is further configured to sequentially write each of the N value pairs in the server into the power supply chip in the server through a program burner, and instruct the power supply chip to supply power to the CPU under test according to the values of the first parameter and the second parameter corresponding to each of the N value pairs in sequence.

10. The system according to claim 7, wherein The system further includes: A power meter, connected to the server and the host computer, is configured to test a second test result of the CPU under test in each of the N value pairs to obtain N second test results. The second test result includes the power consumption value of the CPU under test, and each group of results in the N groups of results includes one of the second test results.

11. The system according to any one of claims 7 to 10, characterized in that, The host computer includes: A virtual system unit, configured to test the CPU under test in the server through a target script to obtain the N groups of results.

12. The system according to claim 11, wherein The virtual system unit includes: A first window, configured to perform a performance test on the CPU under test through a first test script to obtain N first test results. The first test result includes the performance score value of the CPU under test; A second window, configured to perform a stress test on the CPU under test through a second test script to obtain N second test results. The second test result includes the power consumption value of the CPU under test; The target script includes the first test script and the second test script. Each group of results in the N groups of results includes the first test result and the second test result obtained by the CPU under test under the same parameter pair.

13. The system according to claim 12, wherein The host computer includes: A second storage unit, configured to store N groups of test information of the CPU under test. Each group of test information in the N groups of test information is used to represent the first test result and the second test result corresponding to the CPU under test under the test conditions of each of the N value pairs.

14. A CPU testing device, located in a host computer, is characterized in that, Includes: A first determination module, configured to determine a first parameter range and a second parameter range of a power supply chip of a CPU to be tested, where the first parameter range represents a first value range of a first parameter of the power supply chip, the second parameter range represents a second value range of a second parameter of the power supply chip, the first parameter represents a gain parameter for the power supply chip to adjust current, and the second parameter represents a bias parameter for the power supply chip to adjust current; A second determination module, configured to determine N value pairs according to the first parameter range and the second parameter range, and store the N value pairs in a target storage unit, where each of the N value pairs includes a value in the first value range of the first parameter and a value in the second value range of the second parameter, and N is a positive integer greater than or equal to 2; A first acquisition module, configured to sequentially acquire the value pairs in the N value pairs from the target storage unit, and test the CPU to be tested according to the acquired value pairs to obtain N groups of results; The first determination module is configured to determine the first parameter range and the second parameter range of the power supply chip of the CPU to be tested in the following manner: acquire a first reference curve and a second reference curve, where the first reference curve and the second reference curve are respectively used to represent the upper limit and lower limit of the current value allowed for the current value provided by the power supply chip monitored by the CPU to be tested when the actual output current value of the power supply chip is different values in a target current value range; acquire a first initial value of the first parameter and a second initial value of the second parameter; determine the first parameter range according to the first reference curve, the second reference curve, and the second initial value, where P value pairs formed by each value of the first parameter in the first parameter range and the second initial value satisfy a target preset condition, and the target preset condition includes: when the power supply chip supplies power to the CPU to be tested according to the value of the first parameter and the value of the second parameter in the j-th value pair, and when the actual output current value of the power supply chip is the j-th current value in the target current value range, the current value provided by the power supply chip monitored by the CPU to be tested is between the upper limit and lower limit of the current value corresponding to the j-th current value, where P is a positive integer greater than or equal to 1; determine the second parameter range according to the first reference curve, the second reference curve, and the first initial value, where Q value pairs formed by the first initial value and each value of the second parameter in the second parameter range satisfy the target preset condition, where Q is a positive integer greater than or equal to 1.

15. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, where when the computer program is executed by a processor, the steps of the method described in any one of claims 1 to 6 are implemented.

16. An electronic device, comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, When the processor executes the computer program, the steps of the method described in any one of claims 1 to 6 are implemented.

Images