A test circuit, test method and test system
By combining an oscillator circuit and a counter with a control module, the problem of difficulty in detecting the read and write capabilities of storage units is solved, enabling fast and low-cost read capability detection and supporting memory design debugging and PDK file verification.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HYGON INFORMATION TECH CO LTD
- Filing Date
- 2022-12-22
- Publication Date
- 2026-05-12
AI Technical Summary
During the memory manufacturing process, the read and write capabilities of memory cells are difficult to detect effectively due to process drift, especially since the fixed design of MOSFETs makes them difficult to detect after siliconization.
An oscillator circuit is used in conjunction with a counter to generate an oscillation signal related to the read capability of the memory cell and count the number of oscillation cycles. Combined with a control module and a decoder, this enables rapid detection of the read capability of the memory cell.
It enables rapid and accurate detection of the read capability of storage units, reduces software development costs, provides reference value for subsequent design and debugging, and verifies the accuracy of the PDK file.
Smart Images
Figure CN116052751B_ABST
Abstract
Description
Technical Field
[0001] This application belongs to the field of integrated circuits, and specifically relates to a test circuit, test method and test system. Background Technology
[0002] During memory manufacturing, process drift and other factors can cause drift in the read / write capabilities of memory cells. Since the MOSFETs within a memory cell are pre-designed by the manufacturing process, including their size, position, and connections to metal lines, these parameters are fixed and cannot be arbitrarily changed. Unlike ordinary MOSFETs, which can be freely placed and connected, this makes it difficult to detect the read / write capabilities of memory cells after silicon processing. Summary of the Invention
[0003] Therefore, the purpose of this application is to provide a test circuit, test method and test system to quickly detect the read capability of memory cells during chip manufacturing.
[0004] The embodiments of this application are implemented as follows:
[0005] In a first aspect, embodiments of this application provide a test circuit, including: an oscillation circuit and a counter; the oscillation circuit is used to connect to a target memory cell circuit in a memory, the oscillation circuit is used to generate an oscillation signal related to the read capability of the target memory cell circuit; the counter is used to count the number of oscillation cycles of the oscillation signal over a period of time, the number of oscillation cycles being used to characterize the read capability of the target memory cell circuit.
[0006] In this embodiment, an oscillation circuit is used to cooperate with the target memory cell circuit in the memory to generate an oscillation signal related to the read capability of the target memory cell circuit. The number of oscillation cycles of the oscillation signal over a period of time (the time can be flexibly set according to the test requirements) is counted to detect the read capability of the target memory cell circuit.
[0007] In one possible implementation of the first aspect embodiment, the target memory cell circuit includes M memory cells connected in series, the M memory cells being controlled by M word lines, where M is an integer greater than or equal to 2; the test circuit further includes: a control module and a decoder; the control module is used to generate word line control signals; the decoder is connected to the control module and the M word lines, the decoder is used to decode the word line control signals, and enable the corresponding word lines according to the decoding result, so that the test circuit can perform tests on the overall read capability of the M memory cells, or on the read capability of any one of the M memory cells.
[0008] In this embodiment of the application, by adding a control module and a decoder, the test circuit can be used to test the overall read capability of M memory cells, or to test the read capability of any one of the M memory cells, so as to meet different test requirements.
[0009] In one possible implementation of the first aspect embodiment, the control module includes: a counting controller connected to the oscillation circuit, the counting controller being used to count the number of oscillation cycles of the oscillation signal and generate word line control signals based on the counting results, wherein different counting results generate different word line control signals, so that the test circuit can perform tests on the overall read capability of the M memory cells.
[0010] In this embodiment, by using a counting controller to count the number of oscillation cycles of the oscillation signal and generating word line control signals based on the counting results (different counting results generate different word line control signals), the overall read capability of M memory cells can be tested without software logic configuration, saving the manpower cost of software development.
[0011] In one possible implementation of the first aspect embodiment, the control module includes: a register, the register being used to generate word line control signals according to configuration parameters, so that the test circuit can test the read capability of any one of the M memory cells.
[0012] In this embodiment, the required word line control signal can be generated simply by configuring the configuration parameters of the configuration register, enabling the test circuit to test the read capability of any one of the M memory cells. By using a pure hardware approach, compared to configuring through software logic, the manpower cost of software development is saved.
[0013] In one possible implementation of the first aspect embodiment, the target storage cell circuit includes M storage cells connected in series in N columns. N storage cells connected in parallel in the same row are controlled by the same word line (WL), and M storage cells connected in series in the same column are controlled one-to-one by M word lines, where N is an integer greater than or equal to 2. The number of oscillation circuits is N, and each oscillation circuit is connected to the M storage cells connected in series in the same column. The test circuit further includes a selector connected to each oscillation circuit. The selector is used to select one oscillation signal from the N oscillation signals and transmit it to the counter, so that the test circuit can test the overall read capability of any column of storage cells in the N columns, or test the read capability of any single storage cell in any column of the N columns.
[0014] In this embodiment of the application, by increasing the number of oscillation circuits and the selector, the test circuit can test the overall read capability of any column of memory cells in N columns, or test the read capability of any one memory cell in any column of N columns.
[0015] In one possible implementation of the first aspect embodiment, the oscillation circuit includes: a first logic device, a second logic device, and a third logic device; the first logic device has its output terminal connected to a word line of the target memory cell circuit, and the first logic device is used to invert its own input signal and output it, the number of the first logic devices being the same as the number of word lines in the target memory cell circuit; the second logic device has its output terminal connected to a precharge control line of the target memory cell circuit, and the second logic device is used to invert its own input signal and output it; the third logic device has its input terminal connected to a bit line of the target memory cell circuit, and the output terminal of the third logic device is also connected to the first logic device and the second logic device respectively, the third logic device being used to invert its own input signal and output it.
[0016] In this embodiment, an oscillator can be formed by connecting an odd number of logic devices to the target memory cell circuit, thereby generating an oscillation signal related to the read capability of the target memory cell circuit, so as to quickly measure the read capability of the target memory cell circuit.
[0017] In one possible implementation of the first aspect embodiment, the type of the second logic device is the same as the type of the third logic device.
[0018] In this embodiment, the same type of second and third logic devices are used to implement the circuit, which can reduce the complexity of the circuit design and facilitate management and control.
[0019] In one possible implementation of the first aspect embodiment, the second logic device and the third logic device include an inverter, a NOR gate, or a NAND gate.
[0020] In one possible implementation of the first aspect embodiment, the first logic device includes: an inverter and a switch; the input terminal of the inverter is connected to the output terminal of the third logic device, the output terminal of the inverter is connected to the signal input terminal of the switch, the signal output terminal of the switch is connected to the word line of the target memory cell circuit, and the control terminal of the switch is used to receive a word line control signal.
[0021] In this embodiment, an inverter and switch structure is used. The corresponding word line is enabled by controlling the on and off of the switch. While achieving the expected effect (such as testing the overall read capability of any column of memory cells in N columns, or testing the read capability of any one memory cell in any column of N columns), the complexity and cost of the circuit can be reduced.
[0022] In one possible implementation of the first aspect embodiment, the first logic device includes: an inverter and a NOR gate; the first signal input terminal of the NOR gate is connected to the signal output terminal of the third logic device, the output terminal of the NOR gate is connected to the word line of the target memory cell circuit, the output terminal of the inverter is connected to the second signal input terminal of the NOR gate, and the input terminal of the inverter is used to receive a word line control signal.
[0023] In this embodiment, the first logic device using the above structure can reduce circuit complexity and cost.
[0024] Secondly, embodiments of this application provide a testing system, including: a memory and a testing circuit provided in the first aspect embodiment and / or a possible implementation in conjunction with the first aspect embodiment, the testing circuit being used to test the read capability of the memory.
[0025] Thirdly, embodiments of this application provide a testing method, including: the method includes:
[0026] An oscillation circuit is used to generate an oscillation signal related to the read capability of the target memory cell circuit in the memory.
[0027] The number of oscillation cycles of the oscillation signal over a period of time is counted, and the number of oscillation cycles is used to characterize the read capability of the target memory cell circuit.
[0028] In one possible implementation of the third aspect embodiment, the target memory cell circuit includes M memory cells connected in series, the M memory cells being controlled by M word lines, where M is an integer greater than or equal to 2; the method further includes: generating word line control signals, and based on the word lines...
[0029] The control signal enables the corresponding word line to test the overall read capability of the M memory cells, or to test the read capability of any one of the M memory cells.
[0030] In one possible implementation of the third aspect embodiment, the target memory cell circuit includes M memory cells connected in series in N columns, with N memory cells connected in parallel in the same row controlled by the same WL. The number of oscillation circuits is N, and each oscillation circuit is used to connect in series with the same column.
[0031] The method further comprises: connecting M storage units; N being an integer greater than or equal to 2; before counting the number of oscillation cycles of the oscillation signal over a period of 5 time, the method further comprises: selecting from the N oscillation signals...
[0032] Choose to output an oscillation signal to test the overall read capability of any column of N column memory cells, or to test the read capability of any single memory cell in any column of N column memory cells. Attached Figure Description
[0033] 0 To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the following will describe...
[0034] The accompanying drawings used in the embodiments are briefly described below. Obviously, the drawings described below are merely some embodiments of this application. Those skilled in the art can obtain other drawings based on these drawings without any creative effort. The above and other objects, features, and advantages of this application will become clearer through the accompanying drawings. The same reference numerals indicate the same parts in all the drawings. The drawings are not intentionally drawn to scale with actual dimensions; the focus is on illustrating the main points of this application.
[0035] Figure 1 This illustration shows a schematic diagram of a test circuit connected to a target memory cell circuit in a memory, according to an embodiment of this application.
[0036] Figure 2 A circuit schematic diagram of a storage unit provided in an embodiment of this application is shown.
[0037] Figure 3 This illustration shows a circuit diagram of a test circuit connected to a target memory cell circuit according to an embodiment of this application.
[0038] Figure 4 for Figure 3 The schematic diagram shows the principle when the first, second, and third logic devices are all inverters.
[0039] Figure 5 for Figure 4 The circuit diagram shown is a partial waveform diagram of the oscillation signal generated.
[0040] Figure 6 This illustration shows a circuit diagram of another test circuit connected to a target memory cell circuit according to an embodiment of this application.
[0041] Figure 7 This illustration shows a partial schematic diagram of a test circuit connected to a column of memory cells according to an embodiment of this application.
[0042] Figure 8 This illustration shows a partial schematic diagram of another test circuit provided in this application connected to a column of memory cells.
[0043] Figure 9 This illustration shows a partial schematic diagram of a test circuit connected to N columns of memory cells according to an embodiment of this application.
[0044] Figure 10 A flowchart illustrating a testing method provided in an embodiment of this application is shown. Detailed Implementation
[0045] The technical solutions in the embodiments of this application will now be described with reference to the accompanying drawings.
[0046] It should be noted that similar reference numerals and letters in the following figures denote similar items; therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures. Furthermore, relational terms such as "first," "second," etc., in the description of this application are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one…" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0047] Furthermore, the term "and / or" in this application is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.
[0048] Given the current difficulty in detecting the read / write capabilities of memory after silicon fabrication, this application provides a test circuit that can quickly detect the read capability of memory cells during chip manufacturing. This application utilizes an oscillation circuit to cooperate with the target memory cell circuit in the memory, thereby generating an oscillation signal related to the read capability of the target memory cell circuit. The number of oscillation cycles (e.g., Count) of the oscillation signal over a period of time (the time can be flexibly set according to testing needs, denoted by Ti) is counted, thus realizing the detection of the read capability of the target memory cell circuit. The detection results have significant reference value and guiding significance for subsequent memory design and debugging.
[0049] Furthermore, these measurement results can also be used to verify the accuracy of the Spice Model in the PDK file provided by the development engineer. For example, the accuracy of the Spice Model in the PDK file provided by the development engineer can be verified by comparing the measurement results with the expected read capability estimated using this Spice Model.
[0050] The test circuit provided in this application includes an oscillation circuit and a counter. The oscillation circuit is connected to the target storage cell circuit and the counter, and its schematic diagram is shown below. Figure 1 As shown.
[0051] An oscillation circuit is used in conjunction with the target memory cell circuit to generate an oscillation signal (e.g., denoted by RO) related to the read capability of the target memory cell circuit. A counter is used to count the number of oscillation cycles of the oscillation signal over a period of time, where the number of oscillation cycles characterizes the read capability of the target memory cell circuit. The number of oscillation cycles is positively correlated with the read capability of the target memory cell; the more oscillation cycles, the stronger the read capability of the target memory cell circuit.
[0052] After obtaining the number of oscillation cycles (Count) within a certain period (Ti), the average time corresponding to each oscillation cycle can be calculated according to the formula Ti / Count, and then the time required for the target storage unit to perform one data read can be obtained.
[0053] A memory typically consists of M*N storage units, where M and N are both positive integers greater than or equal to 2. N storage units connected in parallel in the same row are controlled by the same word line (WL), and M storage units connected in series in the same column are controlled individually by M word lines (WL).
[0054] In one implementation, the circuit structure of the storage cell in the memory is as follows: Figure 2 As shown. Among them, Figure 2In this code, WL represents the word line, BL and BLB are a pair of bit lines, and PU and PD, along with PU_X and PD_X, form two inverters connected end-to-end. That is, the output of one inverter (composed of PU and PD) is connected to the input of another inverter (composed of PU_X and PD_X), and vice versa. The two inverters connected end-to-end form a latch. Under normal conditions, the data stored in Q and QB is very stable and complementary; for example, when Q=0, QB=1, or when Q=1, QB=0.
[0055] Assuming Q = 0, QB = 1, and BL = BLB = Float1 (meaning that after bit lines BL and BLB are charged to 1, the pre-charge circuit is turned off, causing them to float at 1), when reading data, when WL = 1, both PG and PG_X are in the on state. Since Q = 0, PG's conduction pulls BL = Float1 low, while BLB remains unchanged, creating a voltage difference (DeltaV) between BL and BLB. This voltage difference is amplified by the subsequent sense amplifier (SA) circuit to read the data. Afterward, BL and BLB are charged to 1, completing one data read.
[0056] Among them, the read capability of a storage cell is related to the pull-down transistor (PD or PD_X) in the storage cell, the pull-down capability of BL is related to the pull-down capability of PD_X, and the pull-down capability of BLB is related to the pull-down capability of PD.
[0057] The target memory cell circuit can be divided according to testing needs. For example, in one optional implementation, the target memory cell circuit may include only one memory cell and a pre-charge circuit for charging the bit lines (BL and BLB) of that memory cell. In yet another optional implementation,
[0058] The target memory cell circuit no longer contains only one memory cell, but can include a series of M5 memory cells, which share a precharge circuit. Another alternative implementation...
[0059] In this case, the target memory cell circuit can contain either a single column of M memory cells connected in series, or N columns of M memory cells connected in series. Correspondingly, the number of precharge circuits is also N. One precharge circuit charges the bit lines (BL and BLB) of a single column of M memory cells connected in series.
[0060] The oscillation circuit is connected to the target memory cell circuit. Specifically, the oscillation circuit is connected to the word lines, precharge control lines (e.g., represented by Precharge), and bit lines (BL or BLB) of the target memory cell circuit. Figure 3 As shown, the oscillation circuit includes a first logic device, a second logic device, and a third logic device. Figure 3 In the schematic diagram shown, the target memory cell circuit contains only one memory cell.
[0061] The output of the first logic device is connected to the word line of the target memory cell circuit, the output of the second logic device is connected to the precharge control line of the target memory cell circuit, and the third...
[0062] The input terminals of the logic devices are connected to the bit lines (e.g., BL) of the target memory cell circuit. The output terminals of the third logic device are connected to the input terminals of the first and second logic devices, respectively. The third logic device is used to invert its own input signal (BL) to obtain the RO signal.
[0063] One logic device is used to invert its own input signal (RO) and output it, and a second logic device is used to invert its own input signal (RO) and output it.
[0064] The first, second, and third logic devices, together with the target memory cell circuit, form a ring oscillator, generating a continuous oscillating signal that cycles from '1' (high level) to '0' (low level) and then back to '1' and '0'. Assume that initially Q = 0 and QB = 1, and the values of Q and QB...
[0065] Unless rewritten, its value will remain unchanged throughout the entire RO oscillation cycle. Assuming initially 5BL = BLB = 1 (it's understandable that BL could initially be 0), at this time RO = 0, Precharge = 1, the precharge circuit is off, and BL and BLB are not charged; WL = 1, Q point and BL are connected, and Q point will gradually pull down the voltage of BL. The speed of this drop reflects the strength of the memory cell's read capability. When the BL voltage drops to a certain level, such as below the voltage corresponding to the trigger point of the second logic device connected to it, RO will be changed from 0 to 1. RO = 1, corresponding to WL = 0, will disconnect BL and Q. Simultaneously, Precharge = 0 will control the three PMOS transistors of the precharge circuit to charge BL and BLB to '1', thus completing one cycle. This process will then repeat continuously, resulting in a clock-like oscillation signal with a fixed frequency.
[0066] Understandably, due to Figure 3In the circuit shown, Q = 0 and QB = 1. Therefore, the oscillation circuit is connected to the BL bit line of the memory cell (at this time, this bit line will be pulled down, and the strength of the pull-down is related to the pull-down capability of the memory cell's pull-down transistor PD_X). When Q = 1 and QB = 0 in the memory cell, the oscillation circuit is connected to the BLB bit line of the memory cell (at this time, this bit line will be pulled down, and the strength of the pull-down is related to the pull-down capability of the memory cell's pull-down transistor PD). That is, the oscillation circuit is always connected to the bit line that is pulled down in the memory cell. By rewriting the values of Q and QB, the test circuit can be connected to different bit lines to test the pull-down capability of different pull-down transistors.
[0067] In the oscillation signal, the low pulse is approximately equal to the pull-down time of the blackout transistor (BL), and the high pulse is approximately equal to the charging time of BL. Because BL pull-down involves a small current discharge (i.e., PD or PD_X is a small-sized MOSFET), the low pulse has a wider proportion and a more significant impact on the cycle. Conversely, because BL charging involves a large-sized MOSFET, the high pulse has a smaller proportion in the cycle. Through this design, the cycle length reflects the strength of the cell's pull-down capability; a longer cycle indicates a weaker cell read pull-down capability, and a shorter cycle indicates a stronger cell read pull-down capability. The proportion of low and high pulses can be adjusted by changing the size of the charging transistor in the pre-charge circuit. It's important to understand that "small" and "large" sizes here are relative, simply indicating that the size of the surface-mount pull-down transistor (PD or PD_X) is smaller than the size of the charging transistor.
[0068] The number of first logic devices is the same as the number of word lines in the target memory cell circuit. For example, when there are M word lines, the number of first logic devices is also M. The number of test circuits is the same as the number of columns in the memory cell array. For example, assuming the memory cell array is an M*N array, the number of test circuits is N. M and N are integers greater than or equal to 2.
[0069] The second and third logic devices can include any one of the following: inverter, NOR gate, OR gate, and NAND gate. The second and third logic devices can be the same or different logic devices. For ease of management, it is preferable that the second and third logic devices are the same logic devices.
[0070] When the second and third logic devices include NOR gates, setting the signal at one of the input terminals of the NOR gate to 0 (low level) will enable it to function as an inverter; when the second and third logic devices include NAND gates, setting the signal at one of the input terminals of the NAND gate to 1 (high level) will enable it to function as an inverter.
[0071] The first logic device includes an inverter and a switch. The input of the inverter is connected to the output of the third logic device. The output of the inverter is connected to the signal input of the switch. The signal output of the switch is connected to the word line of the target memory cell circuit. The control terminal of the switch is used to receive the word line control signal (WL).
[0072] Optionally, the switch can be a transistor switch, such as an NMOS transistor, in which case the gate terminal of the NMOS transistor can be the control terminal of the switch. Alternatively, the switch can also be a logic gate switch, such as an AND gate, in which case one of the signal input terminals of the AND gate can be the control terminal of the switch.
[0073] Understandably, logic devices that implement the same logic can be used to replace the inverter + AND gate, for example, replacing the AND inverter + AND gate with an inverter + NOR gate. In this case, the first logic gate device includes an inverter + NOR gate, the output of the third logic device is connected to one signal input of the NOR gate, the signal output of the NOR gate is connected to the word line of the target memory cell circuit, the output of the inverter is connected to the other signal input of the NOR gate, and the input of the inverter is used to receive the word line control signal.
[0074] It is understandable that when the test circuit only tests the read capability of a specific memory cell, i.e., when the target memory cell circuit contains only one memory cell, the first logic device may consist only of an inverter, a NOR gate, or a NAND gate.
[0075] When the first logic device, the second logic device, and the third logic device are inverters Figure 3 The circuit diagram shown is as follows Figure 4 As shown, the corresponding waveform diagram is shown in Figure 5. Figure 5 The dashed line in the diagram represents the voltage BL, which is equal to the flip-point voltage of the inverter connected to it.
[0076] It is understandable that there are many storage cells in a memory. In addition to measuring the read capability of a specific storage cell in the memory, this test circuit can also detect the overall read capability of a column of storage cells in the memory, or detect the read capability of any storage cell in this column of storage cells.
[0077] In another implementation, the target memory cell circuit no longer includes only one memory cell, but can include a series of M memory cell word lines. Correspondingly, the number of first logic devices in the oscillation circuit is also M. The corresponding circuit schematic is shown below. Figure 6 As shown. In this case, the first logic device may include an inverter + a switch (which may be an AND gate), or an inverter + a NOR gate.
[0078] When the target memory cell circuit comprises a series of M memory cells, the test circuit also includes a control module and a decoder. This decoder can be the same decoder used in the memory.
[0079] The decoder is connected to the control module and M word lines. The control module generates word line control signals, and the decoder decodes these signals and enables the corresponding word lines based on the decoding results. Enabled word lines have a read speed of 1 (WL=1), while disabled word lines have a read speed of 0 (WL=0). This allows the test circuit to test the overall read capability of the M memory cells, or the read capability of any one of the M memory cells.
[0080] To better understand, taking M=128 as an example, controlling these 128 (WL[0]~WL
[127] ) word lines requires 7 bits of binary word line control signals (2 7 =128). The decoder decodes these 7 binary word line control signals, converts them into decimal word line addresses, and enables the word line corresponding to the address. For example, if the word line control signal is 0000000, then the corresponding WL[0] is enabled; if the word line control signal is 0000001, then the corresponding WL[1] is enabled; and so on. If the word line control signal is 1111111, then the corresponding WL
[127] is enabled.
[0081] The word line control signal generated by the control module can be any one of 0000000 to 1111111. If the control module generates the same word line control signal for a period of time, the test circuit can test the read capability of any one of the M memory cells. If the control module cyclically generates signals from 0000000 to 1111111 for a period of time, for example, initially generating 0000000, then generating 0000001 after a preset time (which can be one oscillation cycle), then generating 0000010 after another preset time, and so on, until generating 1111111, then generating 0000000 again after a preset time, then generating 0000001 after another preset time, and so on, until generating 1111111, the test circuit can test the overall read capability of the M memory cells. It is understandable that the address control signal generated initially can be any of the 128 signals from 0000000 to 1111111, and is not necessarily 0000000.
[0082] The control module may include a processor, which may be an integrated circuit chip with signal processing capabilities. The processor can be a general-purpose processor, including a Central Processing Unit (CPU), a Network Processor (NP), etc.; it can also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The general-purpose processor can be a microprocessor or any conventional processor.
[0083] Optionally, the control module includes: a counting controller connected to the oscillation circuit, the corresponding circuit schematic of which is shown below. Figure 7 As shown, the counting controller is used to count the number of oscillation cycles of the oscillation signal and generate word line control signals based on the counting results. Different counting results generate different word line control signals, so that the test circuit can test the overall read capability of M memory cells.
[0084] When the oscillation cycle count counted by the counter controller increases by 1, the corresponding word line control signal also increases by 1. For example, assuming the initial word line control signal is 0000000, after the oscillation cycle count increases by 1, the word line control signal generated by the counter controller changes to 0000001. After the oscillation cycle count increases by 1 again, the word line control signal generated by the counter controller changes to 0000010, and so on, until the word line control signal is 1111111. After that, the counter controller will initialize the counted oscillation cycle count, restoring it to the default value (e.g., zero). The corresponding word line control signal will also be initialized to the word line control signal corresponding to this default value (e.g., 0000000). When the counter controller counts the oscillation cycle count again, the corresponding word line control signal will be increased by 1 again, and so on.
[0085] Optionally, the control module may further include a register. The register is used to generate word line control signals according to configuration parameters, enabling the test circuit to test the read capability of any one of the M memory cells. Its schematic diagram is shown below. Figure 8As shown, configuration parameters (such as 0000000) for generating word line control signals can be output via the SI (Scan Input) interface. In this implementation, the word line control signals are fixed unless the configuration parameters are changed, and can be any one of 0000000 to 1111111. It is understood that in this implementation, it is also possible to test the overall read capability of M memory cells.
[0086] In another implementation, the target memory cell circuit can include not only one column of M memory cells connected in series, but also N columns of M memory cells connected in series. In this implementation, the number of oscillator circuits is N, and each oscillator circuit is connected to the same column of M memory cells connected in series. In this case, the number of first logic devices in each oscillator circuit is M, and the M first logic devices correspond one-to-one with the WL of the same column of M memory cells connected in series. The test circuit also includes a selector (MUX), which is connected to each oscillator circuit, and its schematic diagram is shown below. Figure 9 As shown. The selector is used to select one oscillation signal from N oscillation signals and transmit it to the counter, so that the test circuit can perform a test on the overall read capability of any column of memory cells in N columns, or a test on the read capability of any one memory cell in any column of N columns.
[0087] By adding a selector, it is possible to test the overall read capability of any column of storage cells in an M*N storage cell array, or to test the read capability of any single storage cell in any column of N storage cells.
[0088] Based on the same inventive concept, this application also provides a testing system, which includes a memory and the aforementioned testing circuit. The testing circuit is used to test the read capability of the memory. By combining different testing circuits, the overall read capability of a specified column or any column of memory cells can be tested, or the read capability of a specified memory cell, any memory cell in a specified column, or any memory cell in any column can be tested, to meet various testing requirements.
[0089] The memory shown in this application can be, but is not limited to, Random Access Memory (RAM), Read Only Memory (ROM), Programmable Read-Only Memory (PROM), Erasable Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), etc. Among them, the random access memory can be either Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM).
[0090] The test circuit provided in the test system embodiment has the same implementation principle and technical effect as the aforementioned test circuit embodiment. For the sake of brevity, any parts not mentioned in the test system embodiment can be referred to the corresponding content in the aforementioned test circuit embodiment.
[0091] Based on the same inventive concept, this application also provides a method for testing the read capability of a memory, which can be implemented using the aforementioned test circuit. The following will combine... Figure 10 The principle behind this testing method will be explained.
[0092] S1: Use an oscillating circuit to generate an oscillating signal that is related to the read capability of the target memory cell circuit in the memory.
[0093] When testing the memory, the test circuit is connected to the target memory cell circuit in the memory, and an oscillation circuit is used to generate an oscillation signal related to the read capability of the target memory cell circuit in the memory.
[0094] S2: Count the number of oscillation cycles of the oscillation signal over a period of time, wherein the number of oscillation cycles is used to characterize the read capability of the target memory cell circuit.
[0095] After an oscillation signal is generated, a counter is used to count the number of oscillation cycles of the oscillation signal over a period of time. The number of oscillation cycles is used to characterize the read capability of the target memory cell circuit, thereby realizing the detection of the read capability of the target memory cell circuit.
[0096] In one embodiment, the target memory cell circuit includes M memory cells connected in series, the M memory cells being controlled by M word lines, where M is an integer greater than or equal to 2; the testing method further includes: generating word line control signals, and controlling the corresponding word lines to enable based on the word line control signals, so as to test the overall read capability of the M memory cells, or to test the read capability of any one of the M memory cells.
[0097] For example, word line control signals can be generated based on the control module described above, and a decoder can be used to control the corresponding word line enable based on the word line control signals, so as to test the overall read capability of M memory cells, or test the read capability of any one of the M memory cells.
[0098] In one implementation, the target storage cell circuit includes M storage cells connected in series in N columns. N storage cells connected in parallel in the same row are controlled by the same WL. In this case, the number of oscillation circuits is N, and each oscillation circuit is used to connect to the M storage cells connected in series in the same column; N is an integer greater than or equal to 2. Before S2, the test method further includes: selecting and outputting one oscillation signal from the N oscillation signals to test the overall read capability of any column of storage cells in the N columns, or to test the read capability of any single storage cell in any column of the N columns. For example, the selector described above can be used to select and output one oscillation signal from the N oscillation signals.
[0099] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.
[0100] It should also be noted that the functional modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.
[0101] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. A test circuit, characterized in that, include: An oscillation circuit is used to connect to a target memory cell circuit in the memory to generate an oscillation signal related to the read capability of the target memory cell circuit. A counter is used to count the number of oscillation cycles of the oscillation signal over a period of time, wherein the number of oscillation cycles is used to characterize the read capability of the target memory cell circuit. The oscillation circuit includes: The first logic device has its output terminal connected to the word line of the target memory cell circuit. The first logic device is used to invert its own input signal and output it. The number of the first logic devices is the same as the number of word lines in the target memory cell circuit. The second logic device has its output terminal connected to the precharge control line of the target memory cell circuit. The second logic device is used to invert its own input signal and output it. The third logic device has its input terminal connected to a bit line of the target memory cell circuit, and its output terminal is also connected to the first logic device and the second logic device respectively. The third logic device is used to invert its own input signal and output it.
2. The test circuit according to claim 1, characterized in that, in, The target memory cell circuit includes M memory cells connected in series, each of which is controlled by M word lines, where M is an integer greater than or equal to 2; the test circuit further includes: The control module is used to generate word line control signals; A decoder is connected to the control module and the M word lines. The decoder is used to decode the word line control signals and enable the corresponding word lines according to the decoding results, so that the test circuit can test the overall read capability of the M memory cells, or test the read capability of any one of the M memory cells.
3. The test circuit according to claim 2, characterized in that, The control module includes a counting controller connected to the oscillation circuit. The counting controller is used to count the number of oscillation cycles of the oscillation signal and generate word line control signals based on the counting results. Different counting results generate different word line control signals, so that the test circuit can test the overall read capability of the M memory cells.
4. The test circuit according to claim 2, characterized in that, The control module includes a register, which is used to generate word line control signals according to configuration parameters, so that the test circuit can test the read capability of any one of the M memory cells.
5. The test circuit according to claim 2, characterized in that, in, The target storage unit circuit includes M storage units connected in series in N columns. The N storage units connected in parallel in the same row are controlled by the same WL, and the M storage units connected in series in the same column are controlled one by one by M word lines. N is an integer greater than or equal to 2. The number of oscillation circuits is N, and each oscillation circuit is used to connect with M memory cells connected in series in the same column; the test circuit also includes: a selector; The selector is connected to each oscillation circuit. The selector is used to select one oscillation signal from N oscillation signals and transmit it to the counter so that the test circuit can test the overall read capability of any column of N storage cells, or test the read capability of any one storage cell in any column of N storage cells.
6. The test circuit according to any one of claims 1-5, characterized in that, The type of the second logic device is the same as the type of the third logic device.
7. The test circuit according to any one of claims 1-5, characterized in that, The second logic device and the third logic device include inverters, NOR gates, and NAND gates.
8. The test circuit according to any one of claims 1-5, characterized in that, The first logic device includes: an inverter and a switch; The input terminal of the inverter is connected to the output terminal of the third logic device, the output terminal of the inverter is connected to the signal input terminal of the switch, the signal output terminal of the switch is connected to the word line of the target memory cell circuit, and the control terminal of the switch is used to receive the word line control signal.
9. The test circuit according to any one of claims 1-5, characterized in that, The first logic device includes: an inverter and a NOR gate; The first signal input terminal of the NOR gate is connected to the signal output terminal of the third logic device, the output terminal of the NOR gate is connected to the word line of the target memory cell circuit, the output terminal of the inverter is connected to the second signal input terminal of the NOR gate, and the input terminal of the inverter is used to receive the word line control signal.
10. A testing system, characterized in that, include: The memory and the test circuit as described in any one of claims 1-9, the test circuit being used to test the read capability of the memory.
11. A testing method, characterized in that, include: The method includes: An oscillation signal related to the read capability of the target memory cell circuit in the memory is generated using an oscillation circuit. The number of oscillation cycles of the oscillation signal over a period of time is counted, and the number of oscillation cycles is used to characterize the read capability of the target memory cell circuit. The oscillation circuit includes: The first logic device has its output terminal connected to the word line of the target memory cell circuit. The first logic device is used to invert its own input signal and output it. The number of the first logic devices is the same as the number of word lines in the target memory cell circuit. The second logic device has its output terminal connected to the precharge control line of the target memory cell circuit. The second logic device is used to invert its own input signal and output it. The third logic device has its input terminal connected to a bit line of the target memory cell circuit, and its output terminal is also connected to the first logic device and the second logic device respectively. The third logic device is used to invert its own input signal and output it.
12. The test method according to claim 11, characterized in that, The target storage unit circuit includes M storage units connected in series, the M storage units are controlled by M word lines, and M is an integer greater than or equal to 2; the method further includes: Generate word line control signals and enable corresponding word lines based on the word line control signals to test the overall read capability of the M memory cells, or to test the read capability of any one of the M memory cells.
13. The test method according to claim 12, characterized in that, The target storage unit circuit includes M storage units connected in series in N columns, with N storage units connected in parallel in the same row controlled by the same WL. The number of oscillation circuits is N, and each oscillation circuit is used to connect to the M storage units connected in series in the same column; N is an integer greater than or equal to 2; before counting the number of oscillation cycles of the oscillation signal over a period of time, the method further includes: One oscillation signal is selected from N oscillation signals to be output, so as to test the overall read capability of any column of memory cells in N columns, or to test the read capability of any one memory cell in any column of N columns.