Semiconductor device and method for manufacturing the same

Abstract

The present invention provides a semiconductor device and a method for fabricating the same. By etching away a portion of the gate electrode layer in the area where a chip resistor is to be fabricated to form a resistor trench, and then filling the resistor trench with a resistor buffer layer, a resistor layer, and an etch barrier layer, combined with a chemical mechanical polishing process corresponding to the etch barrier layer, a chip resistor circuit component can be fabricated without adding additional thickness to the chip resistor area. This effectively reduces the depth required for subsequent contact hole etching and filling, thereby lowering the aspect ratio of the contact hole and increasing the contact hole manufacturing process window. Furthermore, the present invention can effectively improve the flatness of the device and reduce the overall thickness of the device.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor integrated circuit design and manufacturing, and in particular relates to a semiconductor device and a preparation method thereof. Background Art

[0002] In logic chip circuit design, the required total circuit resistance is typically achieved by retaining a portion of the gate area and adjusting the resistance through ion implantation. However, since the polysilicon surface remains exposed during the front-end of line (FEOL) process, the subsequent junction resistance varies with process differences between different products.

[0003] Furthermore, in advanced metal gate processes, because the metal resistance is too low to achieve the desired resistance using this method, titanium nitride is typically deposited additionally, and the resistance region is defined using a photolithography process to achieve the same design as the original polysilicon gate. The process requires the initial deposition of a certain thickness of silicon oxide dielectric layer as a buffer layer for the titanium nitride. Simultaneously, silicon nitride is deposited above the titanium nitride as a contact etch stop layer (CESL) for the subsequent contact hole etching process. Using titanium nitride as a circuit resistance source is more stable and reliable than ion implantation to alter the polysilicon gate resistance. However, the additional deposition of a thick silicon oxide layer results in an excessively high aspect ratio for the contact holes required in the subsequent contact hole etching process, significantly compressing the process window for dry etching and tungsten metal plug deposition. Furthermore, the deposition of the silicon oxide and resistor layers above the gate affects device flatness and increases device thickness.

[0004] It should be noted that the above introduction to the technical background is merely intended to provide a clear and complete description of the technical solutions of this application and facilitate understanding by those skilled in the art. Simply because these solutions are described in the background technology section of this application, it should not be assumed that the above technical solutions are well known to those skilled in the art. Summary of the Invention

[0005] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a semiconductor device and a method for manufacturing the same, so as to solve the problem in the prior art that the addition of a sheet resistor causes the contact hole process window to be compressed.

[0006] To achieve the above-mentioned object and other related objects, the present invention provides a method for preparing a semiconductor device, the method comprising: 1) providing a semiconductor structure, the semiconductor structure comprising a substrate and a gate structure located on the substrate, the gate structure comprising a stacked gate dielectric layer and a gate electrode layer, and a sidewall structure formed on the periphery of the gate structure; 2) defining a sheet resistance region and a non-sheet resistance region by photolithography, and etching away a portion of the thickness of the gate electrode layer in the sheet resistance region to form a resistance groove; 3) depositing a resistance buffer layer in the resistance grooves in the non-sheet resistance region and the sheet resistance region; 4) depositing a resistance buffer layer in the sheet resistance region; 5) depositing a resistor layer on the resistor buffer layer; 5) depositing an etch barrier layer on the resistor layer, wherein the resistor buffer layer, the resistor layer and the etch barrier layer are filled in the resistor groove; 6) removing the excess etch barrier layer in the non-chip resistor area and the chip resistor area by a chemical mechanical polishing process, so that the etch barrier layer retained in the resistor groove of the chip resistor area is flush with the top surface of the resistor layer in the non-chip resistor area; 7) removing the resistor layer in the non-chip resistor area, and retaining the resistor layer in the resistor groove of the chip resistor area based on the etch barrier layer to form a chip resistor in the resistor groove.

[0007] Optionally, step 1) further includes the step of: depositing a first etch stop layer on the substrate, the first etch stop layer covering the substrate surface, the sidewall structure of the gate structure and the top surface of the gate structure, wherein the etch barrier layer serves as a second etch stop layer.

[0008] Optionally, the gate structure includes a first type of gate and a second type of gate, the first type of gate is located in the sheet resistance area, the second type of gate is located in the non-sheet resistance area, the width of the first type of gate is greater than the width of the second type of gate, and the sheet resistor is made on the first type of gate.

[0009] Optionally, the gate dielectric layer of the first type gate includes one of a silicon oxide layer and a high-k dielectric layer, and the gate electrode layer of the first type gate includes one of a polysilicon gate and a metal gate.

[0010] Optionally, the gate dielectric layer of the second type gate includes one of a silicon oxide layer and a high-k dielectric layer, and the gate electrode layer of the second type gate includes one of a polysilicon gate and a metal gate.

[0011] Optionally, step 1) also includes the steps of: depositing a dielectric layer on the substrate, wherein the deposition thickness of the dielectric layer is greater than the height of the gate structure, and removing the dielectric layer above the top surface of the gate structure by a chemical mechanical polishing process so that the top surface of the dielectric layer is flush with the top surface of the gate structure.

[0012] Optionally, the material of the resistance buffer layer includes silicon dioxide, the material of the resistance layer includes titanium nitride or tantalum nitride, and the material of the etch stop layer includes silicon nitride, silicon oxynitride, and a combination layer of silicon nitride and silicon oxynitride.

[0013] Optionally, in step 7), the resistance layer on the substrate is removed by a wet etching process or a dry etching process.

[0014] The present invention also provides a semiconductor device, comprising: a semiconductor structure, the semiconductor structure comprising a substrate and a gate structure located on the substrate, the gate structure comprising a stacked gate dielectric layer and a gate electrode layer, a sidewall structure formed around the gate structure, and a portion of the thickness of the gate electrode layer being removed to form a resistor groove; a resistor buffer layer, arranged in the resistor groove; a resistor layer, arranged on the resistor buffer layer; and an etch stop layer, arranged on the resistor layer, the resistor buffer layer, the resistor layer and the etch stop layer being filled in the resistor groove to form a sheet resistor.

[0015] Optionally, the substrate further has a first etch stop layer, which covers the substrate surface and the sidewall structure of the gate structure, wherein the etch barrier layer serves as a second etch stop layer.

[0016] Optionally, the gate structure includes a first type of gate and a second type of gate, the first type of gate is located in the sheet resistance area, the second type of gate is located in the non-sheet resistance area, the width of the first type of gate is greater than the width of the second type of gate, and the sheet resistor is made on the first type of gate.

[0017] Optionally, the gate dielectric layer of the first type of gate includes one of a silicon oxide layer and a high-k dielectric layer, the gate electrode layer of the first type of gate includes one of a polysilicon gate and a metal gate, the gate dielectric layer of the second type of gate includes one of a silicon oxide layer and a high-k dielectric layer, and the gate electrode layer of the second type of gate includes one of a polysilicon gate and a metal gate.

[0018] Optionally, the material of the resistance buffer layer includes silicon dioxide, the material of the resistance layer includes titanium nitride or tantalum nitride, and the material of the etch stop layer includes silicon nitride, silicon oxynitride, and a combination layer of silicon nitride and silicon oxynitride.

[0019] As described above, the semiconductor device and the method for manufacturing the same of the present invention have the following beneficial effects:

[0020] The present invention forms a resistor groove by etching away a portion of the gate electrode layer in the area where the chip resistor is to be formed during the gate manufacturing process, and then fills the resistor groove with a resistor buffer layer, a resistor layer, and an etch barrier layer. Combined with a chemical mechanical polishing process for the corresponding etch barrier layer, this allows the chip resistor circuit component to be manufactured without adding additional thickness to the chip resistor area. This effectively reduces the depth required for subsequent contact hole etching and filling, thereby reducing the aspect ratio of the contact hole and increasing the manufacturing process window for the contact hole. Furthermore, the present invention can effectively improve the flatness of the device and reduce the overall thickness of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The accompanying drawings are included to provide a further understanding of the embodiments of the present application, and constitute a part of the specification, and are used to illustrate the implementation of the present application and, together with the text description, to explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application.

[0022] Figures 1 to 7 It shows a schematic structural diagram of each step of the method for manufacturing a semiconductor device according to embodiment 1 of the present invention.

[0023] Figures 8 to 14 Shown are structural schematic diagrams of various steps in a method for manufacturing a semiconductor device according to embodiment 2 of the present invention.

[0024] Figure 15 It is a schematic structural diagram of a semiconductor device according to embodiment 3 of the present invention.

[0025] Component number description

[0026] 10 substrate

[0027] 11. First type of fence

[0028] 111 Gate dielectric layer of the first type gate

[0029] 112 Gate electrode layer of the first type gate

[0030] 12 Second type of fence

[0031] 121 Gate dielectric layer of the second type gate

[0032] 122 Gate electrode layer of the second type gate

[0033] 13 Side wall structure

[0034] 14 First etch stop layer

[0035] 15 dielectric layer

[0036] 16 Resistor buffer layer

[0037] 17 Resistor layer

[0038] 18 Etch stop layer

[0039] 19 resistor slots

[0040] 191 Photoresist Pattern

[0041] 201, 301 metal grille DETAILED DESCRIPTION

[0042] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0043] It should be emphasized that the term "include / comprising" when used herein refers to the presence of features, integers, steps or components, but does not exclude the presence or addition of one or more other features, integers, steps or components.

[0044] Features described and / or illustrated with respect to one embodiment may be used in the same or similar manner in one or more other embodiments, combined with features in other embodiments, or substituted for features in other embodiments.

[0045] For example, when describing the embodiments of the present invention, cross-sectional views of device structures may be partially enlarged to scale for ease of explanation. Furthermore, these schematic views are merely illustrative and should not limit the scope of the present invention. Furthermore, in actual manufacturing, three-dimensional dimensions, including length, width, and depth, should be included.

[0046] For convenience, spatially relative terms such as "under," "below," "below," "below," "above," and "on" may be used herein to describe the relationship of one element or feature to other elements or features shown in the drawings. It will be understood that these spatially relative terms are intended to encompass orientations of the device in use or operation in addition to the orientation depicted in the drawings. Additionally, when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.

[0047] In the context of the present application, a structure described as a first feature being "above" a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature is formed between the first and second features, such that the first and second features may not be in direct contact.

[0048] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0049] Example 1

[0050] like Figures 1 to 7 As shown, this embodiment provides a method for preparing a semiconductor device, the method comprising:

[0051] like Figures 1 and 2 As shown, step 1) is first performed to provide a semiconductor structure, which includes a substrate 10 and a gate structure located on the substrate 10. The gate structure includes a stacked gate dielectric layer and a gate electrode layer, and a sidewall structure 13 is formed around the gate structure.

[0052] In some embodiments, the substrate 10 may be, for example, a silicon substrate 10. The substrate 10 may include various layers, including conductive or insulating layers formed on the semiconductor substrate 10. In addition, depending on design requirements, the substrate 10 may include various doping configurations. The substrate 10 may also include other semiconductors, such as germanium, silicon carbide (SiC), silicon germanium (SiGe), or diamond. The substrate 10 may include compound semiconductors and / or alloy semiconductors, such as gallium nitride, gallium arsenide, etc. In addition, the substrate 10 may optionally include an epitaxial layer (epitaxial layer), may be strained to improve performance, may include a silicon-on-insulator (SOI) structure, and / or have other suitable enhancement features.

[0053] In some embodiments, various device elements may be formed in and / or on the substrate 10. Examples of various device elements that may be formed in and / or on the semiconductor substrate 10 include metal oxide semiconductor field effect transistors (MOSFETs), complementary metal oxide semiconductor (CMOS) transistors, bipolar junction transistors, high voltage transistors, high frequency transistors, P-channel and / or N-channel field effect transistors, diodes, other suitable elements, or combinations thereof. Various device elements may be formed by various processes, such as deposition, etching, implantation, photolithography, annealing, planarization, one or more other applicable processes, or combinations thereof. In addition, in some embodiments, isolation components may be formed in the substrate 10 to define and isolate the various device elements formed in and / or on the substrate 10. Isolation components include, for example, shallow trench isolation (STI) structures, or local oxidation of silicon (LOCOS) structures. The gate structure is a gate structure corresponding to one or more of the above-mentioned device elements.

[0054] The material of the sidewall structure 13 may be, for example, silicon dioxide, silicon nitride, silicon oxynitride, or a stacked structure of the above materials.

[0055] In one embodiment, step 1) also includes the step of: depositing a first etch stop layer 14 on the substrate 10, the first etch stop layer 14 covering the surface of the substrate 10, the sidewall structure 13 of the gate structure and the top surface of the gate structure, the first etch stop layer 14 can expose the top surface of the gate structure or completely cover the top surface of the gate structure, wherein the subsequently formed etch barrier layer 18 serves as a second etch stop layer.

[0056] like Figures 1 and 2 As shown, in this embodiment, the gate structure includes a first type of gate 11 and a second type of gate 12, the first type of gate is located in the sheet resistance area, the second type of gate 12 is located in the non-sheet resistance area, the width of the first type of gate 11 is greater than the width of the second type of gate 12, and the sheet resistance is made on the first type of gate 11.

[0057] As an example, the gate dielectric layer 111 of the first type of gate may include one of a silicon oxide layer and a high-k dielectric layer, and the gate electrode layer 112 of the first type of gate may include one of a polysilicon gate and a metal gate. The gate dielectric layer 121 of the second type of gate may include one of a silicon oxide layer and a high-k dielectric layer, and the gate electrode layer 122 of the second type of gate may include one of a polysilicon gate and a metal gate. In this embodiment, the gate dielectric layer 111 of the first type of gate is a silicon oxide layer, and the gate electrode layer 112 of the first type of gate is a polysilicon gate. The gate dielectric layer 121 of the second type of gate is a silicon oxide layer, and the gate electrode layer 122 of the second type of gate is a polysilicon gate.

[0058] In one embodiment, step 1) further includes the steps of: depositing a dielectric layer 15 on the substrate 10, wherein the thickness of the dielectric layer 15 is greater than the height of the gate structure, and removing the dielectric layer 15 above the top surface of the gate structure by a chemical mechanical polishing process so that the top surface of the dielectric layer 15 is flush with the top surface of the gate structure. The material of the dielectric layer 25 can be, for example, tetraethyl orthosilicate (TEOS) oxide, carbon-containing silicon oxide, silicon oxide, porous dielectric material, undoped silicate glass or doped silicon oxide, such as borophosphosilicate glass (BPSG), fluorinated silicate glass (FSG), phosphosilicate glass (PSG), borosilicate glass (BSG), etc., and can be formed by processes such as plasma enhanced chemical vapor deposition (PECVD), high density plasma chemical vapor deposition (HDP), atomic layer deposition (ALD), etc.

[0059] like Figures 3 and 4As shown, step 2 is then performed. First, a sheet resistance region and a non-sheet resistance region are defined by photolithography, and a portion of the thickness of the gate electrode layer in the sheet resistance region is removed by etching to form a resistance groove 19.

[0060] In one embodiment, a photoresist material may be first spin-coated on the substrate 10, and then a photoresist pattern 191 may be formed through an exposure process and a development process to serve as an etching mask. Subsequently, a portion of the thickness of the gate electrode layer may be removed by dry etching (e.g., reactive plasma etching) to form a resistor groove 19. In this embodiment, the resistor groove 19 completely covers the gate electrode layer in the lateral width of the gate structure. The depth of the resistor groove 19 may be set based on the thickness of the resistor buffer layer 16, the resistor layer 17, and the etching stop layer 18 to be prepared subsequently, and the sheet resistance value is related to the thickness of the resistor buffer layer 16 and the resistor layer 17. For example, the thickness of the resistor groove 19 may be designed so that after the resistor buffer layer 16, the resistor layer 17, and the etching stop layer 18 of sufficient thickness are subsequently filled, the top surface of the etching stop layer 18 may be flush with the top surface of the resistor layer 17 on the substrate 10.

[0061] like Figure 5 As shown, step 3) is then performed to deposit a resistor buffer layer 16 in the resistor grooves 19 of the non-sheet resistor area and the sheet resistor area.

[0062] In one embodiment, the material of the resistor buffer layer 16 is silicon dioxide, which can be formed by processes such as plasma enhanced chemical vapor deposition (PECVD), high density plasma chemical vapor deposition (HDP), atomic layer deposition (ALD), etc., wherein the resistor buffer layer 16 located in the resistor groove 19 covers the bottom and side walls of the resistor groove 19.

[0063] like Figure 5 As shown, step 4 is then performed to deposit a resistor layer 17 on the resistor buffer layer 16 .

[0064] In one embodiment, the resistance layer 17 may be a titanium nitride or tantalum nitride layer with a certain resistance value, which may be formed by processes such as CVD, PVD (such as sputtering, evaporation or MOCVD).

[0065] like Figure 5 As shown, step 5 is then performed to deposit an etching stop layer 18 on the resistor layer 17 , wherein the resistor buffer layer 16 , the resistor layer 17 and the etching stop layer 18 are filled in the resistor groove 19 .

[0066] In one embodiment, the etch stop layer 18 may be made of silicon nitride, silicon oxynitride, or a combination of silicon nitride and silicon oxynitride, and may be formed by a process such as plasma enhanced chemical vapor deposition (PECVD). The etch stop layer 18 fills the resistor groove 19 .

[0067] like Figure 6 As shown, 6) is then performed to remove the excess etching barrier layer 18 in the non-chip resistor area and the chip resistor area through a chemical mechanical polishing process, so that the etching barrier layer 18 retained in the resistor groove 19 in the chip resistor area is flush with the top surface of the resistor layer 17 in the non-chip resistor area.

[0068] The etch barrier layer 18 retained in the resistor groove 19 can serve as a protective mask for the resistor layer 17 and the resistor buffer layer 16 below and on the sidewalls thereof, so as to protect the subsequent removal of the resistor layer 17 on the surface of the substrate 10, so that the resistor layer 17 in the resistor groove 19 can be effectively retained and not be affected by the etching or corrosion process, thereby ensuring that the resistor layer 17 has a stable resistance value and a high film quality.

[0069] like Figure 7 As shown, 7) the resistor layer 17 in the non-sheet resistor area is removed, and the resistor layer 17 in the resistor groove 19 in the sheet resistor area is retained based on the etch stop layer 18 to form a sheet resistor in the resistor groove 19 .

[0070] In one embodiment, in step 7), the resistance layer 17 on the substrate 10 may be removed by a wet etching process or a dry etching process.

[0071] In the subsequent process, it also includes depositing an insulating layer on the above structure, etching contact holes in the insulating layer, and the contact holes include contact holes for gate lead-out, contact holes for source and drain lead-out, etc., and then filling the above contact holes with metal conductors to realize the lead-out of the source, drain, gate, etc. In the gate manufacturing process, the present invention forms a resistor groove 19 by etching away part of the thickness of the gate electrode layer in the area where the chip resistor needs to be made, and fills the resistor groove 19 with a resistor buffer layer 16, a resistor layer 17 and an etching stopper layer 18, and cooperates with the chemical mechanical polishing process corresponding to the etching stopper layer 18. It can be achieved that the chip resistor circuit component does not need to be additionally increased in the chip resistor area, and the depth required for etching and filling of the subsequent contact holes can be effectively reduced, thereby reducing the aspect ratio of the contact holes and increasing the manufacturing process window of the contact holes. At the same time, the present application can effectively improve the flatness of the device and reduce the overall thickness of the device.

[0072] like Figure 7As shown, this embodiment also provides a semiconductor device, which includes: a semiconductor structure, the semiconductor structure including a substrate 10 and a gate structure located on the substrate 10, the gate structure including a stacked gate dielectric layer and a gate electrode layer, a sidewall structure 13 formed on the periphery of the gate structure, and a portion of the thickness of the gate electrode layer is removed to form a resistor groove 19; a resistor buffer layer 16, arranged in the resistor groove 19; a resistor layer 17, arranged on the resistor buffer layer 16; an etch stop layer 18, arranged on the resistor layer 17, the resistor buffer layer 16, the resistor layer 17 and the etch stop layer 18 are filled in the resistor groove 19 to form a sheet resistor.

[0073] In one embodiment, the substrate 10 further has a first etch stop layer 14 , which covers the surface of the substrate 10 and the sidewall structure 13 of the gate structure, wherein the etch barrier layer 18 serves as a second etch stop layer.

[0074] In one embodiment, the gate structure includes a first-type gate 11 and a second-type gate 12. The first-type gate is located in the sheet resistance region, and the second-type gate 12 is located in the non-sheet resistance region. The width of the first-type gate 11 is greater than the width of the second-type gate 12, and the sheet resistance is fabricated on the first-type gate 11. As an example, the gate dielectric layer 111 of the first-type gate may include one of a silicon oxide layer and a high-k dielectric layer, and the gate electrode layer 112 of the first-type gate may include one of a polysilicon gate and a metal gate. The gate dielectric layer 121 of the second-type gate may include one of a silicon oxide layer and a high-k dielectric layer, and the gate electrode layer 122 of the second-type gate may include one of a polysilicon gate and a metal gate. In this embodiment, the gate dielectric layer 111 of the first-type gate is a silicon oxide layer, and the gate electrode layer 112 of the first-type gate is a polysilicon gate. The gate dielectric layer 121 of the second-type gate is a silicon oxide layer, and the gate electrode layer 122 of the second-type gate is a polysilicon gate.

[0075] In one embodiment, the resistance buffer layer 16 is made of silicon dioxide, the resistance layer 17 is made of titanium nitride or tantalum nitride, and the etch stop layer 18 is made of silicon nitride, silicon oxynitride, or a combination of silicon nitride and silicon oxynitride.

[0076] Example 2

[0077] like Figures 8 to 14As shown, this embodiment provides a method for fabricating a semiconductor device. The basic steps of the fabrication method can be referred to in Example 1. The difference from Example 1 is that the gate dielectric layer of the second-type gate is a high-k dielectric layer (such as a hafnium-based high-k dielectric material such as hafnium oxide), and the gate electrode layer of the second-type gate is a metal gate 201. The gate dielectric layer of the first-type gate is a silicon oxide layer, and the gate electrode layer of the first-type gate is a polysilicon gate. The material of the metal gate 201 can be, for example, one or more of TiAl, Al, Ta, Ti, W, Cu, HfCN, HfC, Pt, Ru, Mo, or Ir.

[0078] Specifically, as 8~ Figure 9 As shown, the polysilicon gate of the second type gate 12 in Example 1 can be removed by a process such as etching or corrosion, and then a metal gate 201 is filled in the cavity where the polysilicon gate is removed by a metal filling process (such as sputtering, evaporation, electroplating).

[0079] Example 3

[0080] like Figure 15 As shown, this embodiment provides a method for manufacturing a semiconductor device. The basic steps of the manufacturing method can be referred to in Example 2. The difference from Example 2 is that the gate dielectric layer of the second type of gate is a high-k dielectric layer (such as hafnium oxide), and the gate electrode layer of the second type of gate is a metal gate 201. The gate dielectric layer of the first type of gate is a high-k dielectric layer (such as hafnium oxide), and the gate electrode layer of the first type of gate is a metal gate 301. Specifically, the polysilicon gate of the first type of gate in Example 2 can be removed simultaneously by a process such as etching or corrosion, and then the metal gate 301 is filled in the cavity where the polysilicon gate is removed by a metal filling process (such as sputtering, evaporation, electroplating).

[0081] As described above, the semiconductor device and the method for manufacturing the same of the present invention have the following beneficial effects:

[0082] The present invention forms a resistor groove 19 by etching away part of the thickness of the gate electrode layer in the area where the chip resistor is to be made during the gate manufacturing process, and then fills the resistor groove 19 with a resistor buffer layer 16, a resistor layer 17, and an etch stop layer 18. In conjunction with the chemical mechanical polishing process corresponding to the etch stop layer 18, a chip resistor circuit component can be manufactured without adding additional thickness to the chip resistor area. This can effectively reduce the depth required for subsequent contact hole etching and filling, thereby reducing the aspect ratio of the contact hole and increasing the manufacturing process window of the contact hole. At the same time, the present application can effectively improve the flatness of the device and reduce the overall thickness of the device.

[0083] Therefore, the present invention effectively overcomes various shortcomings of the prior art and has high industrial utilization value.

[0084] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A method for preparing a semiconductor device, characterized in that: The preparation method comprises: 1) Providing a semiconductor structure, the semiconductor structure comprising a substrate and a gate structure located on the substrate, the gate structure comprising a stacked gate dielectric layer and a gate electrode layer, and a sidewall structure formed around the gate structure; 2) defining a sheet resistance region and a non-sheet resistance region by photolithography, and etching away a portion of the thickness of the gate electrode layer in the sheet resistance region to form a resistance groove; 3) depositing a resistor buffer layer in the resistor grooves of the non-sheet resistor area and the sheet resistor area; 4) depositing a resistor layer on the resistor buffer layer; 5) depositing an etch stop layer on the resistor layer, wherein the resistor buffer layer, the resistor layer and the etch stop layer are filled in the resistor groove; 6) removing excess etch barrier layers in the non-chip resistor region and the chip resistor region by a chemical mechanical polishing process, so that the etch barrier layer remaining in the resistor groove in the chip resistor region is flush with the top surface of the resistor layer in the non-chip resistor region; 7) removing the resistor layer in the non-sheet resistor area and retaining the resistor layer in the resistor trench in the sheet resistor area based on the etch stop layer to form a sheet resistor in the resistor trench.

2. The method for preparing a semiconductor device according to claim 1, wherein: Step 1) also includes the step of: depositing a first etch stop layer on the substrate, the first etch stop layer covering the substrate surface, the sidewall structure of the gate structure and the top surface of the gate structure, wherein the etch barrier layer serves as a second etch stop layer.

3. The method for preparing a semiconductor device according to claim 1, wherein: The gate structure includes a first type of gate and a second type of gate, the first type of gate is located in the sheet resistance area, the second type of gate is located in the non-sheet resistance area, the width of the first type of gate is greater than the width of the second type of gate, and the sheet resistor is made on the first type of gate.

4. The method for manufacturing a semiconductor device according to claim 3, wherein: The gate dielectric layer of the first type gate includes one of a silicon oxide layer and a high-k dielectric layer, and the gate electrode layer of the first type gate includes one of a polysilicon gate and a metal gate.

5. The method for preparing a semiconductor device according to claim 3, wherein: The gate dielectric layer of the second type gate includes one of a silicon oxide layer and a high-k dielectric layer, and the gate electrode layer of the second type gate includes one of a polysilicon gate and a metal gate.

6. The method for manufacturing a semiconductor device according to claim 1, wherein: Step 1) also includes the steps of: depositing a dielectric layer on the substrate, wherein the deposition thickness of the dielectric layer is greater than the height of the gate structure, and removing the dielectric layer above the top surface of the gate structure by a chemical mechanical polishing process so that the top surface of the dielectric layer is flush with the top surface of the gate structure.

7. The method for manufacturing a semiconductor device according to claim 1, wherein: The material of the resistance buffer layer includes silicon dioxide, the material of the resistance layer includes titanium nitride or tantalum nitride, and the material of the etch stop layer includes silicon nitride, silicon oxynitride, and a combination layer of silicon nitride and silicon oxynitride.

8. The method for manufacturing a semiconductor device according to claim 1, wherein: Step 7) removing the resistance layer on the substrate by a wet etching process or a dry etching process.

9. A semiconductor device manufactured by the method for manufacturing a semiconductor device according to any one of claims 1 to 8, characterized in that: include: A semiconductor structure comprising a substrate and a gate structure located on the substrate, the gate structure comprising a stacked gate dielectric layer and a gate electrode layer, a sidewall structure formed around the gate structure, and a portion of the gate electrode layer having its thickness removed to form a resistor trench; a resistance buffer layer, disposed in the resistance slot; a resistance layer, disposed on the resistance buffer layer; The etching stop layer is arranged on the resistance layer. The resistance buffer layer, the resistance layer and the etching stop layer are filled into the resistance groove to form a sheet resistor.

10. The semiconductor device according to claim 9, wherein: The substrate also has a first etch stop layer, which covers the substrate surface and the sidewall structure of the gate structure, wherein the etch barrier layer serves as a second etch stop layer.

11. The semiconductor device according to claim 9, wherein: The gate structure includes a first type of gate and a second type of gate, the first type of gate is located in the sheet resistance area, the second type of gate is located in the non-sheet resistance area, the width of the first type of gate is greater than the width of the second type of gate, and the sheet resistor is made on the first type of gate.

12. The semiconductor device according to claim 11, wherein: The gate dielectric layer of the first type of gate includes one of a silicon oxide layer and a high-k dielectric layer, the gate electrode layer of the first type of gate includes one of a polysilicon gate and a metal gate, the gate dielectric layer of the second type of gate includes one of a silicon oxide layer and a high-k dielectric layer, and the gate electrode layer of the second type of gate includes one of a polysilicon gate and a metal gate.

13. The semiconductor device according to claim 9, wherein: The material of the resistance buffer layer includes silicon dioxide, the material of the resistance layer includes titanium nitride or tantalum nitride, and the material of the etch stop layer includes silicon nitride, silicon oxynitride, and a combination layer of silicon nitride and silicon oxynitride.

Images