A power device with integrated gate resistor and a manufacturing method thereof

Abstract

The present invention discloses a power device with integrated gate resistor and a manufacturing method thereof, and relates to the technical field of semiconductor integrated circuit manufacturing. The device comprises: a device layer comprises a gate layer, and the gate layer comprises a plurality of strip-shaped gates and N polycrystalline silicon strips; the power device also comprises an insulating layer located on the surface of the gate layer and a metal layer located on the surface of the insulating layer, and the metal layer comprises a gate bus, a gate metal, a first fuse and a second fuse; wherein the gate bus connects the two ends of each strip-shaped gate; one end of each polycrystalline silicon strip is connected to the gate bus through the first fuse, and the other end of each polycrystalline silicon strip is connected to the gate metal, and the gate metal is connected to the gate bus through the second fuse; the power device also comprises a passivation layer located on the surface of the metal layer, a first window located above the first fuse and a second window located above the second fuse; and the manufacturing cost of the power device is effectively reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor integrated circuit manufacturing, and in particular to a power device with integrated gate resistor and a manufacturing method thereof. Background Art

[0002] Gate resistance (Rg) is a relatively important parameter of the isolation layer device. The gate resistance can attenuate the oscillation on the gate, but it also reduces the conversion efficiency. The higher the driving frequency, the higher the conversion efficiency requirement, and the smaller the gate resistance is. However, too small a gate resistance will result in higher electromagnetic interference (EMI) interference. Therefore, it is necessary to design power devices with different gate resistances according to different application scenarios.

[0003] In order to meet the demand for power devices with different gate resistances in different occasions, it is usually necessary to place an external discrete resistor at the gate end of the device, but adding an external discrete resistor will increase the cost; to solve the above problem, the conventional practice in the prior art is to integrate a polycrystalline resistor strip on the gate polysilicon of the power device, integrating the external discrete resistor into the power device, which saves costs to a certain extent; however, in actual applications, different application scenarios have different requirements for the gate resistance of the power device. If the gate resistance needs to be modified, the aspect ratio of the gate resistor strip can only be redesigned to change the gate resistance, which requires redesigning the mask and re-taping the wafer, resulting in higher manufacturing costs for the power device. Summary of the Invention

[0004] Based on this, it is necessary to provide a power device with integrated gate resistor and a manufacturing method thereof to address the above technical problems, so as to solve the problem of high manufacturing cost of power devices in the prior art.

[0005] In a first aspect, the present invention provides a power device with an integrated gate resistor, comprising:

[0006] device layer;

[0007] The device layer includes a gate layer, the gate layer includes a plurality of strip-shaped gates and N polysilicon strips, the ends of each of the strip-shaped gates are connected together, and N is an integer greater than zero;

[0008] The power device further includes an insulating layer located on the surface of the gate layer and a metal layer located on the surface of the insulating layer, wherein the metal layer includes a gate bus, a gate metal, a first fuse and a second fuse;

[0009] The gate bus connects two ends of each of the strip-shaped gates; one end of each of the polysilicon strips is connected to the gate bus via the first fuse, and the other end of each of the polysilicon strips is connected to the gate metal, and the gate metal is connected to the gate bus via the second fuse;

[0010] The power device also includes a passivation layer located on the surface of the metal layer, a first window located above the first fuse, and a second window located above the second fuse. The windows are used to provide an operating window for blowing the first fuse and / or the second fuse to obtain a gate resistor with an adjusted resistance after blowing the fuse.

[0011] The above solution has the following beneficial effects:

[0012] The power device with integrated gate resistor of the present invention has a plurality of polysilicon strips arranged on the gate of the power device. The polysilicon strips are connected in parallel and in series with the strip-shaped gate. A window is opened above the fuse so that the fuse connecting the polysilicon strip and the gate bus can be blown through the opened window later, thereby adjusting the gate resistance of the power device. Only one power device needs to be manufactured, and the resistance value of the gate resistor can be adjusted as needed later, which effectively reduces the manufacturing cost of the power device.

[0013] Optionally, strip metal columns are provided in the insulating layer corresponding to the two ends of each polysilicon strip, wherein the two ends of the strip metal column at one end are respectively connected to the first fuse and the polysilicon strip, and the two ends of the strip metal column at the other end are respectively connected to the gate metal and the polysilicon strip.

[0014] Optionally, the polysilicon strips have the same length and equal or unequal widths; the width of the polysilicon strips is greater than 10 μm, and the spacing between the polysilicon strips is greater than 1.0 μm.

[0015] Optionally, the first fuse and the second fuse have a width of 1.0 μm-3.0 μm and a length of 10 μm-20 μm.

[0016] Optionally, the first window and the second window are rectangular windows, and the width of the rectangular windows is greater than 8.0 μm.

[0017] In a second aspect, the present invention provides a method for manufacturing a power device with an integrated gate resistor, comprising:

[0018] Make gate mask;

[0019] Manufacturing a device layer of a power device, the device layer including a gate layer comprising a plurality of strip-shaped gates with ends connected together and N polysilicon strips manufactured using the gate mask, where N is an integer greater than zero;

[0020] forming an insulating layer on the surface of the gate layer;

[0021] A metal layer is formed on the surface of the insulating layer, wherein the metal layer includes a gate bus, a gate metal, a first fuse, and a second fuse, such that the gate bus connects two ends of each of the strip-shaped gates, one end of each of the polysilicon strips is connected to the gate bus through the first fuse, and the other end of each of the polysilicon strips is connected to the gate bus, and the gate metal is connected to the gate bus through the second fuse;

[0022] Growing a passivation layer on the surface of the metal layer, forming a first window above the first fuse, and forming a second window above the second fuse, so as to blow the first fuse and / or the second fuse through the first window and the second window to adjust the resistance value of the gate resistor;

[0023] The package is wire bonded to obtain a power device with integrated gate resistor.

[0024] The above solution has the following beneficial effects:

[0025] The manufacturing method of the power device with integrated gate resistor of the present invention is to make a plurality of polysilicon strips on the gate of the power device. After the polysilicon strips are connected in parallel, they are connected in series with the strip gate through a fuse, and a window is opened above the fuse so that the fuse connecting the polysilicon strip and the gate bus can be blown through the opened window at a later time, thereby adjusting the gate resistance of the power device. Only one mask needs to be designed to realize the manufacturing of different gate resistances, which effectively reduces the manufacturing cost of the power device.

[0026] Optionally, a metal layer is formed on the surface of the insulating layer, and the metal layer includes a gate bus, a gate metal, a first fuse, and a second fuse, including:

[0027] Making polysilicon strip contact holes on the surface of the insulating layer corresponding to the two ends of the polysilicon strip, so that the polysilicon strip contact holes connect the two ends of each polysilicon strip;

[0028] Making gate bus contact holes on the surface of the insulating layer corresponding to the two ends of each strip-shaped gate, so that the gate bus contact holes connect the two ends of the strip-shaped gate;

[0029] growing a metal layer on the surface of the insulating layer so that the metal layer fills each contact hole;

[0030] The metal layer is etched to form the gate bus, the gate metal, the first fuse, and the second fuse.

[0031] Optionally, the equivalent resistance values ​​of the polysilicon strips are the same or different.

[0032] Optionally, forming an insulating layer on the surface of the gate layer includes:

[0033] An insulating material having a preset thickness is grown on the surface of the gate layer by a chemical vapor deposition method to form the insulating layer.

[0034] Optionally, after growing a passivation layer on the surface of the metal layer, the method further comprises:

[0035] A gate pad is made on the surface of the gate metal, and a source pad is made on the metal layer above the strip-shaped gate. The gate pad and the source pad are used for packaging and wiring. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments of the present invention. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0037] Figure 1 1 is a schematic top view of a power device with an integrated gate resistor provided in one embodiment of the present invention;

[0038] Figure 2 1 is a schematic diagram of a gate resistor equivalent circuit provided in one embodiment of the present invention;

[0039] Figure 3 1 is a schematic top view of another power device with integrated gate resistor provided in one embodiment of the present invention;

[0040] Figure 4 This is a schematic diagram of a process for manufacturing a power device with an integrated gate resistor provided in one embodiment of the present invention;

[0041] Figure 5-1 1 is a schematic structural diagram of a gate layer manufactured using a gate mask provided in one embodiment of the present invention;

[0042] Figure 5-2 is a schematic diagram of a method for fabricating a contact hole provided in one embodiment of the present invention;

[0043] Figure 5-3 is a schematic diagram of manufacturing a metal layer provided in one embodiment of the present invention;

[0044] Figure 5-4 is a schematic diagram of manufacturing a fuse window provided in one embodiment of the present invention;

[0045] The symbols are explained as follows:

[0046] 1. Strip gate; 2. Polysilicon strip; 3. Gate metal; 4. Source metal; 5. Gate bus; 6. First fuse; 7. Second fuse; 8. Strip metal column; 9. First window; 10. Second window; 11. Gate pad; 12. Source pad; 13. Contact hole. DETAILED DESCRIPTION

[0047] The technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, but not all of the embodiments.

[0048] It should be understood that the embodiments set forth below represent the necessary information to enable those skilled in the art to implement the embodiments and to illustrate the best mode of implementing the embodiments. After reading the following description in light of the accompanying drawings, those skilled in the art will understand the concepts of the present disclosure and will recognize applications of these concepts not specifically mentioned herein. It should be understood that these concepts and applications fall within the scope of the present disclosure and the appended claims.

[0049] It should also be understood that although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element without departing from the scope of this disclosure. As used herein, the term "and / or" includes any and all combinations of one or more of the related listed items.

[0050] It should also be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or intervening elements may be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements.

[0051] It should also be understood that the terms "upper", "lower", "left", "right", "front", "back", "bottom", "middle", "center", "top", etc. may be used in this document to describe various elements, and the indicated orientation or position relationship is based on the orientation or position relationship shown in the accompanying drawings, which is only for the convenience of describing the present invention and simplifying the description, and does not indicate or imply that the device or component referred to must have a specific orientation, be constructed and operated in a specific orientation, so these elements should not be restricted by these terms.

[0052] These terms are only used to distinguish one element from another. For example, a first element can be referred to as an "upper" element, and similarly, a second element can be referred to as an "upper" element based on the relative orientation of these elements without departing from the scope of the present disclosure.

[0053] It is further understood that the terms “comprises,” “includes,” “includes,” and / or “comprising” when used herein specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0054] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that the terms used herein should be interpreted as having a meaning consistent with their meaning in the context of this specification and the related art, and will not be interpreted in an idealized or overly formal sense unless expressly defined as such herein.

[0055] In one embodiment, a power device with an integrated gate resistor is provided, the power device comprising: a device layer, the device layer comprising a substrate, an epitaxial layer, an isolation layer and other structures of the power device, the device layer of the power device further comprising a gate layer, such as Figure 1 As shown, the figure is a top view of the gate and source, and the layers are stacked. The bottom gate layer includes several strip-shaped gates 1 and four polysilicon strips 2, and the ends of each strip-shaped gate 1 are connected together.

[0056] The power device also includes an insulating layer located on the surface of the gate layer and a metal layer located on the surface of the insulating layer, that is, an insulating layer is provided on the surface of the strip gate 1 and the polysilicon strip 2, and a metal layer is provided above the insulating layer. The metal layer includes a gate bus 5, a gate metal 3, a first fuse 6, and a second fuse 7; wherein the gate bus 5 connects the two ends of each strip gate 1; one end of each polysilicon strip 2 is connected to the gate bus 5 via the first fuse 6, and the other end of each polysilicon strip 2 is connected to the gate metal 3, and the gate metal 3 is connected to the gate bus 5 via the second fuse 7.

[0057] The power device also includes a passivation layer located on the surface of the metal layer, a first window 9 and a second window 10, wherein the first window 9 is located above the first fuse 6, passes through the insulating layer, and the first fuse 6 can be exposed through the first window 9; the second window 10 is located above the second fuse 7, passes through the insulating layer, and the second fuse 7 can be exposed through the second window 10. The first window 9 and the second window 10 can provide an operating window for blowing the first fuse 6 and / or the second fuse 7, so as to obtain a gate resistor with an adjusted resistance value after blowing the first fuse 6 and / or the second fuse 7.

[0058] As another embodiment, the number of polysilicon strips is N, where N is an integer greater than zero. By providing a plurality of polysilicon strips, the resistance value of the gate resistor can be adjusted more accurately.

[0059] The working principle of the above-mentioned power device with integrated gate resistor is as follows:

[0060] Each strip gate 1 is connected together through a gate bus. It has its own resistance, namely the intrinsic resistance Ra of the gate. The four polysilicon strips are equivalent to four resistors, namely R1, R2, R3, and R4. After being connected in parallel, they are connected in series with the intrinsic resistance Ra of the gate to form a Figure 2 In the equivalent circuit shown, F1, F2, F3, and F4 are first fuses connected to resistors R1, R2, R3, and R4, respectively; and F5 is a second fuse connected to the intrinsic resistor Ra.

[0061] If the resistance values ​​of resistors R1, R2, R3, and R4 are 10 ohms, 20 ohms, 40 ohms, and 80 ohms, respectively, and the resistance value of the intrinsic resistor Ra is 1.0 ohm, then the resistance value of the resistors R1, R2, R3, and R4 after being connected in parallel is 5.3 ohms. The resistors R1, R2, R3, and R4 are connected in parallel between the gate metal and the gate bus, and the intrinsic resistor Ra is connected to the gate metal through the second fuse F5. At this time, the overall resistance value of the gate resistor is 6 / 7 ohms, which is approximately equal to the resistance value of the intrinsic resistor Ra.

[0062] If the second fuse F5 is blown, the total resistance of the gate is the resistance of the resistors R1 , R2 , R3 , and R4 connected in parallel, which is 5.3 ohms.

[0063] If the second fuse F5 and the first fuse F4 are blown, the total resistance of the gate is the resistance of the resistors R1 , R2 , and R3 in parallel, which is 5.7 ohms.

[0064] If the second fuse F5 and the first fuses F4 and F3 are blown, the total resistance of the gate is the resistance of the resistors R1 and R2 in parallel, which is 6.7 ohms. Therefore, different gate resistance values ​​can be obtained by using the above different fuse blowing combinations.

[0065] As another embodiment, a plurality of polysilicon strips may be designed so that the resistance difference between each polysilicon strip is small, thereby being able to more accurately adjust the resistance of the gate resistor.

[0066] In the power device with integrated gate resistor of this embodiment, a plurality of polysilicon strips are arranged on the gate of the power device. The polysilicon strips are connected in parallel and in series with the strip gate. A window is opened above the fuse so that the fuse connecting the polysilicon strip and the gate bus can be blown through the opened window later, thereby adjusting the gate resistance of the power device. Only one power device needs to be manufactured, and the resistance value of the gate resistor can be adjusted as needed later, which effectively reduces the manufacturing cost of the power device.

[0067] Further, such as Figure 3As shown, a gate pad 11 is further provided on the surface of the gate metal 3, a source metal 4 is further provided above the corresponding insulating layer of the strip gate 1, and a source pad 12 is provided above the source metal 4; metal columns are provided between each strip gate 1 to connect the source metal 4 and the source structure below the strip gate 1; the gate pad 11 and the source pad 12 are used for subsequent testing and packaging wiring.

[0068] Furthermore, strip metal pillars 8 are provided in the insulating layer corresponding to the two ends of each polysilicon strip 2, wherein the two ends of the strip metal pillar 8 at one end are respectively connected to the first fuse 6 and the polysilicon strip 2, and the two ends of the strip metal pillar 8 at the other end are respectively connected to the gate metal 3 and the polysilicon strip 2.

[0069] Furthermore, the polysilicon strips 2 have the same length and equal or different widths, thereby equivalently producing resistors of different resistance values; the width of the polysilicon strips 2 is greater than 10 μm, and the spacing between each polysilicon strip 2 is greater than 1.0 μm to ensure that a sufficiently large gate current can pass through.

[0070] Furthermore, the first fuse 6 and the second fuse 7 have a width of 1.0 μm-3.0 μm and a length of 10 μm-20 μm, so as to facilitate subsequent blowing.

[0071] Furthermore, the first window 9 and the second window 10 are rectangular windows, and the width of the rectangular windows is greater than 8.0 μm, so as to provide a larger blowing operation space and ensure the yield of fuse trimming.

[0072] Furthermore, the width of the strip metal pillar 8 is greater than 2.0 μm. This size can ensure that the contact resistance at both ends of the strip metal pillar 8 is less than 0.1 ohm, thereby improving the adjustment accuracy of the gate resistance.

[0073] In one embodiment, a method is provided as follows Figure 4 The method for manufacturing a power device with an integrated gate resistor shown in FIG. 1 includes the following steps:

[0074] Step S100: making a gate mask.

[0075] The gate mask is a photomask used to make the gate. When designing the gate mask, N polysilicon strips of different widths are designed below the gate pad area. This mask is used to make the gate layer of the power device.

[0076] Step S200: manufacturing a device layer of a power device, the device layer including a gate layer including a plurality of strip-shaped gates with ends connected together and N polysilicon strips manufactured through a gate mask, where N is an integer greater than zero.

[0077] The device layer of the power device is manufactured on the substrate. The device layer includes the epitaxial layer, drift layer, etc. of the power device, as well as the gate mask manufactured by the above-mentioned gate mask. Figure 5-1 The gate layer shown includes a plurality of strip-shaped gates 1 and N polysilicon strips 2, where the N polysilicon strips 2 are equivalent to N resistors with preset resistance values. The two ends of each strip-shaped gate are connected together, and the equivalent resistance of the connected strip-shaped gates is the intrinsic resistance Ra of the gate. The width of the polysilicon strip is greater than 10 μm, and the distance between each polysilicon strip is greater than 1.0 μm to ensure that a sufficiently large gate current can pass through.

[0078] Step S300: forming an insulating layer on the surface of the gate layer.

[0079] After the device layer is manufactured, an insulating material is grown on the surface of the gate layer by chemical vapor deposition (CVD) to form an insulating layer.

[0080] See also Figure 5-2 Contact holes 13 are made on the surface of the insulating layer by photolithography and etching. The contact holes 13 are distributed at both ends of the polysilicon strip 2 and the strip gate 1. At the same time, source contact holes are formed between the strip gates to connect the source metal. The width of the contact holes should be as large as possible. In order to ensure the accuracy of the adjustment, the contact resistance on one side of the polysilicon strip is less than 0.1 ohm. As a preferred solution, the width of the contact holes is greater than 2.0 μm.

[0081] Step S400: A metal layer is formed on the surface of the insulating layer, the metal layer including a gate bus, a gate metal, a first fuse and a second fuse, so that the gate bus connects the two ends of each strip gate, so that one end of each polysilicon strip is connected to the gate bus through the first fuse, and the other end of each polysilicon strip is connected to the gate metal, and the gate metal is connected to the gate bus through the second fuse.

[0082] See also Figure 5-3 A metal layer is grown on the surface of the insulating layer, and then the metal layer is photoetched to form a gate metal 3, a source metal 4, a gate bus 5, a first fuse 6, and a second fuse 7. During the growth of the metal layer, the contact hole is filled with metal to form a strip metal pillar 8; during the etching of the metal layer, one end of each polysilicon strip 2 is connected to one end of the first fuse 6 through the strip metal pillar 8, and the other end of the first fuse 6 is connected to the gate bus 5; the other end of each polysilicon strip 2 is connected to the gate metal 3 through the strip metal pillar 8, and the gate metal 3 is connected to the gate bus 5 through the second fuse 7.

[0083] In this embodiment, the first fuse 6 and the second fuse 7 are designed to have a width of 1.0 μm-3.0 μm and a length of 10 μm-20 μm to facilitate subsequent blowing. The thickness of the metal layer is generally 3.0 μm-5.0 μm, and the resistance of the metal layer can be ignored.

[0084] Step S500: growing a passivation layer on the surface of the metal layer, forming a first window above the first fuse, and forming a second window above the second fuse, so as to blow the first fuse and / or the second fuse through the first window and the second window to adjust the resistance value of the gate resistor.

[0085] See also Figure 5-4 A passivation layer is grown on the surface of the metal layer fabricated above, and then photolithography is performed to form a gate pad 11, a source pad 12, a first window 9, and a second window 10. The first window 9 is located above the first fuse 6, and the second window 10 is located above the second fuse 7. The first fuse 6 can be blown by a laser at the position of the first window 9, and the second fuse 7 can be blown by a laser at the position of the second window 10, thereby adjusting the resistance value of the gate resistor; the gate pad 12 and the source pad 13 are used for testing and packaging wire bonding. In order to ensure the yield of fuse trimming, the width of the first window 9 and the second window 10 is greater than 8.0μm.

[0086] Step S600: packaging and bonding to obtain a power device with integrated gate resistor.

[0087] Wire bonding is performed at the locations of the gate pad and source pad manufactured above, and then packaging is performed to obtain a power device with an integrated gate resistor.

[0088] In the manufacturing method of a power device with an integrated gate resistor of this embodiment, a plurality of polysilicon strips are produced on the gate of the power device. After the polysilicon strips are connected in parallel, they are connected in series with the strip-shaped gate through a fuse, and a window is opened above the fuse so that the fuse connecting the polysilicon strip and the gate bus can be blown through the opened window later, thereby adjusting the gate resistance of the power device. Only one mask needs to be designed to realize the manufacturing of different gate resistances, which effectively reduces the manufacturing cost of the power device.

[0089] The embodiments described above are only used to illustrate the technical solutions of the present invention, rather than to limit the same. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention, and should all be included in the scope of protection of the present invention.

Claims

1. A power device with integrated gate resistor, characterized in that: include: Device layer; The device layer includes a gate layer, the gate layer includes a plurality of strip-shaped gates and N polysilicon strips, the ends of each of the strip-shaped gates are connected together, and N is an integer greater than zero; The power device further comprises an insulating layer located on the surface of the gate layer and a metal layer located on the surface of the insulating layer, wherein the metal layer comprises a gate bus, a gate metal, a first fuse and a second fuse; The gate bus connects two ends of each of the strip-shaped gates; one end of each of the polysilicon strips is connected to the gate bus through the first fuse, and the other end of each of the polysilicon strips is connected to the gate metal, and the gate metal is connected to the gate bus through the second fuse; The power device also includes a passivation layer located on the surface of the metal layer, a first window located above the first fuse, and a second window located above the second fuse. The windows are used to provide an operation window for blowing the first fuse and / or the second fuse to obtain a gate resistor with an adjusted resistance after blowing the fuse.

2. The power device with integrated gate resistor according to claim 1, characterized in that: Strip metal columns are arranged in the insulating layer corresponding to the two ends of each polysilicon strip, wherein the two ends of the strip metal column at one end are respectively connected to the first fuse and the polysilicon strip, and the two ends of the strip metal column at the other end are respectively connected to the gate metal and the polysilicon strip.

3. The power device with integrated gate resistor according to claim 1, characterized in that: The polysilicon strips have the same length and the same or different widths; the width of the polysilicon strips is greater than 10 μm, and the spacing between the polysilicon strips is greater than 1.0 μm.

4. The power device with integrated gate resistor according to claim 1, characterized in that: The first fuse and the second fuse have a width of 1.0 μm-3.0 μm and a length of 10 μm-20 μm.

5. The power device with integrated gate resistor according to claim 1, characterized in that: The first window and the second window are rectangular windows, and the width of the rectangular windows is greater than 8.0 μm.

6. A method for manufacturing a power device with an integrated gate resistor, characterized in that: include: Make gate mask; Manufacturing a device layer of a power device, the device layer comprising a gate layer including a plurality of strip-shaped gates with ends connected together and N polysilicon strips manufactured by the gate mask, where N is an integer greater than zero; Forming an insulating layer on the surface of the gate layer; A metal layer is formed on the surface of the insulating layer, the metal layer comprising a gate bus, a gate metal, a first fuse and a second fuse, so that the gate bus connects two ends of each of the strip-shaped gates, one end of each of the polysilicon strips is connected to the gate bus through the first fuse, and the other end of each of the polysilicon strips is connected to the gate metal, and the gate metal is connected to the gate bus through the second fuse; A passivation layer is grown on the surface of the metal layer, a first window is formed above the first fuse, and a second window is formed above the second fuse, so that the first fuse and / or the second fuse are blown through the first window and the second window to adjust the resistance value of the gate resistor; The package is wire bonded to obtain a power device with integrated gate resistor.

7. The method for manufacturing a power device with integrated gate resistor according to claim 6, characterized in that: A metal layer is formed on the surface of the insulating layer, wherein the metal layer includes a gate bus, a gate metal, a first fuse and a second fuse, including: Making polysilicon strip contact holes on the surface of the insulating layer corresponding to the two ends of the polysilicon strip, so that the polysilicon strip contact holes connect the two ends of each polysilicon strip; Making gate bus contact holes on the surface of the insulating layer corresponding to the two ends of each of the strip-shaped gates, so that the gate bus contact holes connect the two ends of the strip-shaped gates; Growing a metal layer on the surface of the insulating layer so that the metal layer fills each contact hole; The metal layer is etched to form the gate bus, the gate metal, the first fuse and the second fuse.

8. The method for manufacturing a power device with integrated gate resistor according to claim 6, characterized in that: The equivalent resistance values ​​of the polysilicon strips are the same or different.

9. The method for manufacturing a power device with integrated gate resistor according to claim 6, characterized in that: Producing an insulating layer on the surface of the gate layer, comprising: An insulating material with a preset thickness is grown on the surface of the gate layer by a chemical vapor deposition method to form the insulating layer.

10. The method for manufacturing a power device with integrated gate resistor according to claim 6, characterized in that: After a passivation layer is grown on the surface of the metal layer, the method comprises: A gate pad is made on the surface of the gate metal, and a source pad is made on the metal layer above the strip-shaped gate. The gate pad and the source pad are used for packaging and wiring.

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