Conductive line contact regions with multiple multi-directional conductive lines and stepped conductive line contact structures for semiconductor devices

Abstract

Systems, methods, and devices include a conductive line contact region having a plurality of multi-directional conductive lines and stepped conductive line contact structures for a semiconductor device. One memory device includes a vertically stacked array of memory cells having a plurality of multi-directional conductive line arrays of vertically stacked memory cells including a vertically stacked of layers formed from repeated iterations of a group of layers including a first dielectric material layer, a semiconductor material layer, and a second dielectric material layer having conductive lines formed therein in a horizontal plane, and the vertically stacked of layers having a plurality of multi-directional conductive lines in an interconnect region having a first portion of the interconnect region formed in an array region and a second portion formed in a conductive line contact region spaced apart from the array region.

Description

TECHNICAL FIELD

[0001] The present disclosure relates generally to memory devices, and more particularly, to conductive line contact regions having multiple multi-directional conductive lines and stepped conductive line contact structures for semiconductor devices. BACKGROUND

[0002] Memory is typically implemented in electronic systems such as computers, cellular telephones, handheld devices, etc. There are many different types of memory, including volatile and non-volatile memory. Volatile memory can require power to maintain its data, and can include random access memory (RAM), dynamic random access memory (DRAM), static random access memory (SRAM), and synchronous dynamic random access memory (SDRAM). Non-volatile memory can provide persistent data by retaining stored data when unpowered, and can include NAND flash memory, NOR flash memory, nitride read-only memory (NROM), phase change memory (e.g., phase change random access memory), resistive memory (e.g., resistive random access memory), cross point memory, ferroelectric random access memory (FeRAM), etc.

[0003] As design rules shrink, less semiconductor space is available for fabricating memory including DRAM arrays. A respective memory cell for a DRAM can include an access device (e.g., a transistor) having first and second source / drain regions separated by a channel region. A gate can oppose the channel region and be separated from the channel region by a gate dielectric. An access line, such as a word line, is electrically connected to the gate of a DRAM cell. The DRAM cell can include a storage node, such as a capacitor cell, coupled to a conductive line, such as a digit line, through the access device. The access device can be activated (e.g., to select the cell) through the access line coupled to the access transistor. The capacitor can store a charge corresponding to a data value (e.g., a logic "1" or "0") for the respective cell. BRIEF DESCRIPTION OF DRAWINGS

[0004] Figure 1 is a schematic diagram of a vertical three-dimensional (3D) memory device in accordance with a number of embodiments of the present disclosure.

[0005] Figure 2 is a perspective view illustrating a portion of a conductive line and stepped contact for a semiconductor device in accordance with a number of embodiments of the present disclosure.

[0006] Figure 3 is a perspective view illustrating a portion of a conductive line and stepped contact for a semiconductor device in accordance with a number of embodiments of the present disclosure.

[0007] FIG. 4A is a top view illustrating a conventional memory device configuration.

[0008] Figure 4B is a top view illustrating a memory device configuration according to a number of embodiments of the present disclosure.

[0009] Figure 4C is a top view illustrating another memory device configuration according to a number of embodiments of the present disclosure.

[0010] Figures 5A to 5T An example method for forming an array of vertically stacked memory cells with conductive line contact regions having a plurality of multi-directional conductive lines and stepped conductive line contact structures according to one or more embodiments of the present disclosure is described.

[0011] Figures 6A to 6C is a cross-sectional view illustrating different levels of conductive lines and stepped contact structures for a vertical memory array according to one or more embodiments of the present disclosure.

[0012] Figure 7 is a top view of a three-dimensional (3D) memory array according to one or more embodiments of the present disclosure.

[0013] Figure 8 is a top view of a three-dimensional (3D) memory array according to one or more embodiments of the present disclosure.

[0014] Figure 9 is a top view of a three-dimensional (3D) memory array according to one or more embodiments of the present disclosure.

[0015] Figure 10 is a block diagram of a device in the form of a computer system that includes a memory device according to a number of embodiments of the present disclosure. DETAILED DESCRIPTION

[0016] Embodiments of the present disclosure describe conductive line contact regions having a plurality of multi-directional conductive lines and stepped conductive line contact structures for semiconductor devices. Conductive line contact regions having a plurality of multi-directional conductive lines and stepped conductive line contact structures can be formed with horizontal access devices in an array of vertically stacked memory cells. As discussed herein, the horizontal access devices can be integrated with vertically oriented access lines and horizontal digit lines. Although discussed herein as having vertically oriented access lines (e.g., word lines) and having horizontal digit lines, some embodiments can have vertically oriented digit lines and horizontal access lines, where the access devices are, for example, word line drivers or other suitable access devices. Embodiments described herein have advantages of increasing interconnect density compared to conventional structures and processes, among other advantages.

[0017] In this manner, stacked memory devices, such as 3D DRAM devices include multiple levels of vertically stacked memory cells. Coupling conductive lines (e.g., digit lines, word lines) of a 3D array to sense amplifiers or word line drivers can be challenging and can increase interconnect area size. For example, traditional geometries of conductive lines can result in relatively large interconnect areas associated with contacts for connecting digit lines to sense amplifiers. Various embodiments of the present disclosure can provide multi-directional conductive lines and can allow for connections to those conductive lines through layered (e.g., stepped) structures. In some embodiments, the conductive lines can be digit lines coupled to one or more circuitry components (e.g., sense amplifiers) through interconnects and / or sense amplifier contacts. In other embodiments, the conductive lines can be access lines (i.e., word lines) coupled to one or more circuitry components (e.g., word line drivers). Embodiments of the present disclosure can provide the benefit of greater density of connections between conductive lines and sense amplifiers in interconnect areas, for example, as compared to previous approaches.

[0018] The figures herein follow a convention relating to the numbering of elements wherein the first digit or digits correspond to the figure number and the remaining digits identify an element or component in the drawing. Similar elements or components between different figures can be identified by the use of similar digits. For example, element 104 can be referred to as element "04" in Figure 1, and similar elements can be referred to as 204 in Figure 2. Multiple similar elements between different figures can be referred to by the reference number followed by a hyphen and an additional number or letter. For example, 302-1 can refer to element 302-1 in Figure 3, and 302-2 can refer to element 302-2, which can be similar to element 302-1. Such similar elements can be generally referred to without the hyphen and additional number or letter. For example, elements 302-1 and 302-2, or other similar elements, can be generally referred to as 302. The use of a letter, such as 302-N, means that any number of items 302 can be utilized. Figure 1 Figure 2 Figure 3

[0019] Figure 1 is a block diagram of a device in accordance with a number of embodiments of the present disclosure. Figure 1 The illustration shows a circuit diagram of a cell array of a three-dimensional (3D) semiconductor memory device in accordance with embodiments of the present disclosure. Figure 1 ​​​The array of memory cells can have a plurality of sub-array of memory cells 101-1, 101-2,..., 101-N. The sub-arrays of memory cells 101-1, 101-2,..., 101-N can be arranged along a second direction (D2) 105. Each of the sub-arrays of memory cells (e.g., sub-array of memory cells 101-2) can include a plurality of access lines 103-1, 103-2,..., 103-Q (which can also be referred to as word lines). Also, each of the sub-arrays of memory cells (e.g., sub-array of memory cells 101-2) can include a plurality of digit lines 107-1, 107-2,..., 107-Q (which can also be referred to as bit lines, data lines, or sense lines). In Figure 1 In the first direction (D1) 109, the digit lines 107-1, 107-2,..., 107-Q are illustrated, and in the third direction (D3) 111, the access lines 103-1, 103-2,..., 103-Q are illustrated.

[0020] The first direction (D1) 109 and the second direction (D2) 105 can be considered to be in a horizontal (“X-Y”) plane. The third direction (D3) 111 can be considered to be in a vertical (“Z”) direction (e.g., transverse to the X-Y plane). Thus, according to the embodiments described herein, the access lines 103-1, 103-2,..., 103-Q extend in a vertical direction (e.g., the third direction (D3) 111).

[0021] A memory cell (e.g., 110) can include an access device (e.g., an access transistor) and a storage node at the intersection of each access line 103-1, 103-2,..., 103-Q and each digit line 107-1, 107-2,..., 107-Q. The access lines 103-1, 103-2,..., 103-Q and the digit lines 107-1, 107-2,..., 107-Q can be used to write to or read from the memory cells. The digit lines 107-1, 107-2,..., 107-Q can conductively interconnect the memory cells along the horizontal columns of each sub-array of memory cells 101-1, 101-2,..., 101-N, and the access lines 103-1, 103-2,..., 103-Q can conductively interconnect the memory cells along the vertical rows of each sub-array of memory cells 101-1, 101-2,..., 101-N. One memory cell (e.g., 110) can be located between one access line (e.g., 103-2) and one digit line (e.g., 107-2). Each memory cell can be uniquely addressed by a combination of the access lines 103-1, 103-2,..., 103-Q and the digit lines 107-1, 107-2,..., 107-Q.

[0022] The digit lines 107-1, 107-2,..., 107-Q can be or include electrically conductive patterns (e.g., metal lines) disposed on and spaced apart from the substrate. The digit lines 107-1, 107-2,..., 107-Q can extend in a first direction (D1) 109. The digit lines 107-1, 107-2,..., 107-Q in one subarray array (e.g., 101-2) can be spaced apart from each other in a vertical direction (e.g., in a third direction (D3) 111).

[0023] The access lines 103-1, 103-2,..., 103-Q can be or include electrically conductive patterns (e.g., metal lines) extending in a vertical direction (e.g., in a third direction (D3) 111) relative to the substrate. The access lines in one subarray array (e.g., 101-2) can be spaced apart from each other in a first direction (D1) 109.

[0024] A gate of a memory cell (e.g., memory cell 110) can be connected to an access line (e.g., 103-2), and a first conductive node (e.g., a first source / drain region) of an access device (e.g., a transistor) of the memory cell 110 can be connected to a digit line (e.g., 107-2). Each of the memory cells (e.g., memory cell 110) can be connected to a storage node (e.g., a capacitor). A second conductive node (e.g., a second source / drain region) of the access device (e.g., a transistor) of the memory cell 110 can be connected to the storage node (e.g., a capacitor). The storage node, e.g., a capacitor, can be formed of a ferroelectric and / or a dielectric material, e.g., zirconium oxide (Zr02), hafnium oxide (Hf02), lanthanum oxide (La203), lead zirconate titanate (PZT, Pb[Zr(x)Ti(l-x)]03), barium titanate (BaTi03), aluminum oxide (e.g., Al203), combinations of these with or without dopants, or other suitable materials.

[0025] While references are made herein to first and second source / drain regions to refer to two separate and distinct source / drain regions, it is not intended that the source / drain regions referred to as the "first" and / or "second" source / drain regions have some unique meaning. It is only intended that one of the source / drain regions be connected to a digit line (e.g., 107-2) and the other can be connected to a storage node.

[0026] Figure 2 A perspective view of a portion of a subarray 101-2 showing vertically oriented stacks of memory cells in an array is illustrated in FIG. 1C in accordance with some embodiments of the present disclosure. Figure 1 A perspective view of a portion of a subarray 101-2 showing vertically oriented stacks of memory cells in an array is illustrated in FIG. 1C in accordance with some embodiments of the present disclosure. Figure 3 A perspective view of a portion of a subarray 101-2 showing vertically oriented stacks of memory cells in an array is illustrated in FIG. 1C in accordance with some embodiments of the present disclosure. Figure 2 A perspective view of a portion of a subarray 101-2 showing vertically oriented stacks of memory cells in an array is illustrated in FIG. 1C in accordance with some embodiments of the present disclosure.Figure 1 A perspective view of the memory cell 110 shown.

[0027] like Figure 2 As shown, a bonding element can be formed on the substrate 200. Figure 1 One of the described array of sub-cells (e.g., 101-2). For example, substrate 200 may be or comprise a silicon substrate, a germanium substrate, or a silicon-germanium substrate, etc. However, the embodiments are not limited to these examples.

[0028] like Figure 2 As shown in the example embodiments, memory cells extending in a vertical direction (e.g., third direction (D3) 111) can be fabricated on the substrate 200. Figure 1 The memory cells 110 in the memory are vertically stacked. According to some embodiments, the vertical stacking of the memory cells can be manufactured such that each memory cell (e.g., Figure 1 The memory cells 110 are formed on multiple vertical levels (e.g., a first level (L1), a second level (L2), and a third level (L3)). Repeating vertical levels L1, L2, and L3 can be arranged along the vertical direction (e.g., ...). Figure 1 The third-party (D3) 111 arrangement shown is (e.g., “stacked”) and can be spaced apart from the substrate 200 by an insulating material 220. Each of the repeating vertical levels L1, L2, and L3 may include multiple discrete components (e.g., regions) and memory nodes (e.g., capacitors) to a laterally oriented access device 230 (e.g., a transistor), the memory nodes including access lines 103-1, 103-2, ..., 103-Q connections and digital lines 107-1, 107-2, ..., 107-Q connections. The multiple discrete components to the laterally oriented access device 230 (e.g., a transistor) may be formed in multiple iterations of the vertical repeating layers within each level, as described in more detail below with reference to Figures 4A to 4C, and may be similar to Figure 1 The second direction (D2) 105 shown extends horizontally on the second direction (D2) 205.

[0029] Multiple discrete components of a laterally oriented access device 230 (e.g., a transistor) may include a first source / drain region 221 and a second source / drain region 223 separated by a channel region 225 extending laterally in a second direction (D2) 205 and formed in the body of the access device. In some embodiments, the channel region 225 may comprise silicon, germanium, silicon-germanium, and / or indium gallium zinc oxide (IGZO). In some embodiments, the first source / drain region 221 and the second source / drain region 223 may comprise n-type dopant regions formed in the p-type doped body of the access device to form n-type conductive transistors. In some embodiments, the first source / drain region 221 and the second source / drain region 223 may comprise p-type dopant formed in the n-type doped body of the access device to form p-type conductive transistors. By way of example, but not limitation, the n-type dopant may comprise phosphorus (P) atoms, and the p-type dopant may comprise boron (B) atoms formed in the opposite doped body region of the polycrystalline silicon semiconductor material. However, the embodiments are not limited to these examples.

[0030] Storage node 227 (e.g., a capacitor) can be connected to a corresponding terminal of the access device. For example... Figure 2 As shown, storage node 227 (e.g., a capacitor) may be connected to the second source / drain region 223 of the access device. Storage nodes may be or contain memory elements capable of storing data. Each of the storage nodes may be a memory element using one of a capacitor, a magnetic tunnel junction pattern, and / or a variable resistor body containing a phase change material. However, embodiments are not limited to these examples. In some embodiments, with unit cells (e.g. Figure 1 Each access device associated with a memory node in memory cell 110 can be in a similar manner to... Figure 1 It extends on the second direction (D2) 205 shown in the second direction (D2) 105.

[0031] like Figure 2 As shown, multiple horizontally oriented digital lines 207-1, 207-2, ..., 207-Q are similar to Figure 1 Extending from the first direction (D1) 109 in the first direction (D1) 209. Multiple horizontally oriented digital lines 207-1, 207-2, ..., 207-Q can be similar to... Figure 1The plurality of horizontally oriented digit lines 207-1, 207-2,..., 207-Q can be arranged (e.g.,“stacked”) along a third direction (D3) 211. The plurality of horizontally oriented digit lines 207-1, 207-2,..., 207-Q can include a conductive material. For example, the conductive material can include one or more of a doped semiconductor (e.g., doped silicon, doped germanium, etc.), a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.), a metal (e.g., tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), cobalt (Co), molybdenum (Mo), etc.), and / or a metal-semiconductor compound (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.). However, embodiments are not limited to these examples.

[0032] Within each of the vertical levels (LI) 213-1, (L2) 213-2, and (L3) 213-P, the horizontally oriented memory cells (e.g., memory cells 110 in Figure 1 However, as described in greater detail below in connection with FIG. 4A and the following, etc., the plurality of discrete components of the laterally oriented access devices 230 (e.g., the first source / drain region 221 and the second source / drain region 223 separated by the channel region 225) extending laterally in the second direction (D2) 205, and the plurality of horizontally oriented digit lines 207-1, 207-2,..., 207-Q extending laterally in the first direction (D1) 209 can be formed within different vertical layers within each level. For example, the plurality of horizontally oriented digit lines 207-1, 207-2,..., 207-Q extending in the first direction (D1) 209 can be disposed on and in electrical contact with a top surface of the first source / drain region 221 and orthogonal to the laterally oriented access devices 230 (e.g., transistors) extending laterally in the second direction (D2) 205. In some embodiments, the plurality of horizontally oriented digit lines 207-1, 207-2,..., 207-Q extending in the first direction (D1) 209 are formed in a higher vertical layer than the layers in which the discrete components of the laterally oriented access devices (e.g., the first source / drain region 221 and the second source / drain region 223 separated by the channel region 225) are formed within a level (e.g., within level (LI)). In some embodiments, the plurality of horizontally oriented digit lines 207-1, 207-2,..., 207-Q extending in the first direction (D1) 209 can be connected directly and / or through additional contacts including metal silicides to the top surface of the first source / drain region 221.

[0033] As Figure 2As shown in example embodiments, access lines 203-1, 203-2,..., 203-Q extend in a vertical direction (e.g., in third direction (D3) 211) relative to substrate 200. Further, as shown in Figure 2 access lines 203-1, 203-2,..., 203-Q in a subcell array 101-2 in Figure 1 may be spaced apart from one another in first direction (D1) 209. Access lines 203-1, 203-2,..., 203-Q can be provided that extend vertically in third direction (D3) 211 relative to substrate 200 between a pair of laterally oriented access devices 230 (e.g., transistors) that extend laterally in second direction (D2) 205, but are adjacent to one another in first direction (D1) 209 on a level (e.g., first level (LI)). Each of access lines 203-1, 203-2,..., 203-Q can extend vertically in third direction (D3) on a sidewall of a respective access device of a plurality of laterally oriented access devices 230 (e.g., transistors) that are vertically stacked.

[0034] For example, and as shown in more detail in Figure 3 a first access line (e.g., 203-1) of the vertically extending access lines can be adjacent to a sidewall of a channel region 225 of a first access device of laterally oriented access devices 230 (e.g., transistors) in first level (LI) 213-1, a sidewall of a channel region 225 of the first access device of laterally oriented access devices 230 (e.g., transistors) in second level (L2) 213-2, and a sidewall of a channel region 225 of the first access device of laterally oriented access devices 230 (e.g., transistors) in third level (L3) 213-P, etc. Similarly, a second access line (e.g., 203-2) of the vertically extending access lines can be adjacent to a sidewall of a channel region 225 of a second access device of laterally oriented access devices 230 (e.g., transistors) in first level (LI) 213-1, spaced apart from the first access device of laterally oriented access devices 230 (e.g., transistors) in first level (LI) 213-1 in first direction (D1) 209. Also, the second access line (e.g., 203-2) of the vertically extending access lines can be adjacent to a sidewall of a channel region 225 of the second access device of laterally oriented access devices 230 (e.g., transistors) in second level (L2) 213-2, and a sidewall of a channel region 225 of the second access device of laterally oriented access devices 230 (e.g., transistors) in third level (L3) 213-P, etc. Embodiments are not limited to a particular number of levels.

[0035] The vertically extending access lines 203-1, 203-2, ..., 203-Q may contain a conductive material, such as a doped semiconductor material, a conductive metal nitride, a metal, and / or a metal-semiconductor compound. Access lines 203-1, 203-2, ..., 203-Q may correspond to... Figure 1 The word line (WL) of the description.

[0036] like Figure 2 As shown in the example embodiment, conductive body contacts 295 extending in a first direction (D1) 209 may be formed along the end surface of a laterally oriented access device 230 (e.g., a transistor) in each layer (L1) 213-1, (L2) 213-2, and (L3) 213-P above the substrate 200. The body contacts 295 may be connected to each memory cell (e.g., Figure 1 The body of the laterally oriented access device 230 (e.g., a transistor) in the memory cell 110) Figure 3 (As shown in 336) (e.g., the body region). The body contact 295 may contain a conductive material, such as a doped semiconductor material, a conductive metal nitride, a metal, and / or a metal-semiconductor compound.

[0037] although Figure 2 Not shown, but insulating material may fill other spaces in a vertically stacked array of memory cells. For example, the insulating material may comprise one or more of silicon oxide, silicon nitride, and / or silicon oxynitride. However, the embodiments are not limited to these examples.

[0038] Figure 3 A more detailed description of vertically stacked memory cell arrays according to some embodiments of the present disclosure (e.g., Figure 1 The unit cells (e.g., within the sub-unit array 101-2) in the sub-unit array 101-2 Figure 1 (Memory unit 110 in the middle). For example Figure 3 As shown, the first source / drain region 321 and the second source / drain region 323 may be impurity-doped regions of a laterally oriented access device 330 (e.g., a transistor). The first source / drain region 321 and the second source / drain region 323 may be similar to Figure 2 The first source / drain region 221 and the second source / drain region 223 are shown. The first and second source / drain regions may be separated by channels 325 formed in a body (e.g., body region 326) of the semiconductor material of the laterally oriented access device 330 (e.g., a transistor). The first source / drain region 321 and the second source / drain region 323 may be formed by n-type or p-type dopant doped in the body region 326. Embodiments are not limited thereto.

[0039] For example, in an n-type conductive transistor configuration, the body region 326 of the laterally oriented access device 330 (e.g., a transistor) may be formed of a lightly doped (p-)p-type semiconductor material. In some embodiments, the body region 326 and the channel 325 separating the first source / drain region 321 and the second source / drain region 323 may comprise a lightly doped p-type (e.g., lower dopant concentration (p-)) polysilicon material composed of boron (B) atoms as an impurity dopant for the polysilicon. The first source / drain region 321 and the second source / drain region 323 may also comprise metals and / or metal composites formed using atomic layer deposition processes, etc., containing: ruthenium (Ru), molybdenum (Mo), nickel (Ni), titanium (Ti), copper (Cu), highly doped degenerate semiconductor materials, and / or indium oxide (In₂O₃) or indium tin oxide (In₂O₃). 2-x Sn x At least one of O3). However, the embodiments are not limited to these examples.

[0040] As used herein, degenerate semiconductor materials refer to semiconductor materials, such as polycrystalline silicon, containing high levels of doping with significant interactions between dopants (e.g., phosphorus (P), boron (B), etc.). In contrast, non-degenerate semiconductors contain moderate levels of doping, where dopant atoms are well separated from each other in the semiconductor host lattice with negligible interactions.

[0041] In this example, the first source / drain region 321 and the second source / drain region 321 may contain highly doped n-type conductive impurities (e.g., highly doped (n+)) doped into the first source / drain region 321 and the second source / drain region 323. In some embodiments, the highly doped n-type conductive first drain region 321 and the second drain region 323 may contain a high concentration of phosphorus (P) atoms deposited therein. However, the embodiments are not limited to this example. In other embodiments, the laterally oriented access device 330 (e.g., a transistor) may have a p-type conductive configuration, in which case the conductivity type of the impurity (e.g., the dopant) will be reversed.

[0042] like Figure 3 As shown in the example embodiment, the first source / drain region 321 may occupy the upper portion of the body 326 of the laterally oriented access device 330 (e.g., a transistor). For example, the first source / drain region 321 may have a bottom surface 324 within the body 326 of the laterally oriented access device 330, which is vertically higher in a third direction (D3) 311 compared to the bottom surface of the body 326 of the laterally oriented access device 330. Therefore, the laterally oriented transistor 330 may have a lower portion below the first source / drain region 321 and adjacent to the body contact (e.g., ...). Figure 2 The main body portion 326 of the electrical contact shown in Figure 295. Furthermore, as...Figure 3 As shown in example embodiments of Figure 2 the digit lines 207-1, 207-2,..., 207-Q in Figure 1 the digit lines (e.g., 307-1) shown in 107-1, 107-2,..., 107-Q in

[0043] As shown in example embodiments of Figure 3 the access lines (e.g., similar to the access lines 203-1, 203-2,..., 203-Q in Figure 2 the 303-1, 103-2,..., 103-Q in 103-1, 103-2,..., 103-Q in Figure 1 may extend vertically adjacent to a sidewall portion of a channel region 325 to a body 326 of a laterally-oriented access device 330 (e.g., a transistor) in a third direction (D3) 311, the laterally-oriented access device conductive horizontally between the first source / drain region 321 and the second source / drain region 323 along a second direction (D2) 305. A gate dielectric material 304 can be interposed between the access line 303-1 (a portion of which forms a gate of the laterally-oriented access device 330 (e.g., transistor)) and the channel region 325.

[0044] The gate dielectric material 304 can include, for example, a high-k dielectric material, a silicon oxide material, a silicon nitride material, a silicon oxynitride material, etc., or combinations thereof. Embodiments are not limited in this context. For example, in a high-k dielectric material example, the gate dielectric material 304 can include one or more of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, etc.

[0045] FIG. 4A is a top view illustrating a conventional three-dimensional (3D) memory device configuration. In such a configuration, a 3D DRAM array 440 of vertically-stacked memory cells (i.e., a memory cell array) can have a plurality of digit lines (e.g., 407-1,..., 407-2) (collectively, digit lines 407) formed therein. Each digit line can extend in a first horizontal direction (D1) 409.

[0046] Each digit line can be coupled to one or more access devices (not shown). For example, in the embodiment illustrated in FIG. 4A, the 3D DRAM array 440 of vertically-stacked memory cells has two digit lines 407 formed therein and extending parallel to each other in the direction (D1) 409, and each of the digit lines 407 within the array region is coupled to a sense amplifier located within a sense amplifier region 435 via interconnects 434-1,..., 434-S.

[0047] Interconnects 434-1, ..., 434-S may each comprise a first portion extending in the (D1) 409 direction and a second portion extending in the (D2) 405 direction, such that each second portion can be coupled to one of the digital lines 407 extending in the (D1) 409 direction. This configuration of interconnects 434-1, ..., 434-S and digital lines 407-1, ..., 407-Q adds additional device space to the memory cell array 440 (described at 436-1), which may be undesirable where space constraints apply. Furthermore, it may be difficult to manufacture the L-shaped connectors forming interconnects 434-1, ..., 434-S.

[0048] Figure 4B This is a top view illustrating the configuration of a memory device according to one or more embodiments of the present disclosure. Figure 4B The structure described herein reduces the total space occupied by each interconnect region and therefore by the memory device. The memory device may include a 3D array 440 of vertically stacked memory cells (i.e., a memory cell array), a plurality of interconnects 434-1, ..., 434-S, and a sense amplifier region 435 having a plurality of sense amplifiers. Each of the plurality of interconnects 434-1, ..., 434-S is electrically coupled to the sense amplifier 435.

[0049] A 3D array 440 of vertically stacked memory cells may comprise a vertical stack of horizontally oriented conductive lines (e.g., 407-1, 407-2). The conductive lines may be digital lines or access lines (i.e., word lines). Each conductive line 407 formed within the array 440 may comprise a first portion 441-1, ..., 441-2 extending in a first horizontal direction (D1) 409. Each horizontal conductive line may further comprise a second portion 442-1, ..., 442-T extending in a second horizontal direction D2 at an angle to the first horizontal direction (D1) 409. In other words, the memory cell array 440 may comprise a plurality of multi-directional conductive lines 407 (also referred to as curved conductive lines).

[0050] In some embodiments, the vertically stacked memory cell array may be electrically coupled, for example, in an open digital line architecture. In other embodiments, the vertically stacked memory cell array may be electrically coupled in a folded digital line architecture.

[0051] For example, such as Figure 4B As shown, in some embodiments, the second portion of each conductive line (e.g., 442-1, 442-2) may extend in a second horizontal direction (D2) 405 at an angle to the first portion (e.g., perpendicular to the first horizontal direction (D1) 409).

[0052] Although Figure 4B While the conductive lines 407-1 and 407-2 are illustrated as having two portions 442-1 and 442-2, embodiments of the present disclosure are not so limited. For example, in some embodiments, each conductive line can further include a third portion extending in a third direction. The third portion can extend in the direction (D1) 409. The third portion can be coupled to an end of the second portion. This embodiment is shown and discussed, for example, in Figure 5C

[0053] As explained in Figure 4B , the memory device can further include a plurality of horizontally oriented interconnects 434-1,..., 434-S. In some embodiments, each horizontally oriented interconnect 434-1,..., 434-S can be electrically coupled to the second portion 442-1, 442-2 of the conductive line 407-1, 407-2. In some embodiments, each interconnect 434-1,..., 434-S can be coupled to the second portion 442-1, 442-2 of the conductive line 407-1, 407-2 by a horizontally oriented storage node. These horizontally oriented storage nodes can include capacitor cells.

[0054] The conductive lines 407-1, 407-2 can be coupled to a sense amplifier region 435 by the interconnects 434-1,..., 434-S. In some embodiments, the conductive lines 407-1, 407-2 can be digit lines, and the sense amplifier region 435 can include a plurality of sense amplifiers. While not illustrated herein, in some embodiments, the conductive lines 407-1, 407-2 can be access lines (i.e., word lines) that can not be coupled to the sense amplifier region 435 but can instead be coupled to one or more other circuit system components (e.g., word line drivers) via contacts.

[0055] Figure 4B The multi-directional conductive line configuration illustrated in Figure 4B may reduce space constraints by allowing the interconnects 434-1,..., 434-S to occupy less space (i.e., occupy less space 436-2 than the space 436-1 of FIG. 4A). Coupling each interconnect 434-1,..., 434-S to the second portion 442-1, 442-2 of each conductive line 407-1, 407-2 as illustrated in

[0056] Although not illustrated in Figure 4B , the 3D array 440 can include a plurality of vertical levels, which can also be referred to as a plurality of tiers. Each vertical level can include one or more tiers in which one or more horizontal conductive lines 407 are formed.

[0057] ​In some embodiments, each second portion 442-1,..., 442-T of each conductive line 407 can have a length that is greater than a length of a second portion 442-1,..., 442-T of a conductive line 407 on a lower vertical level. Thus, if the 3D array consists of levels LI, L2,..., LN and LI is the top level of the vertical stack, the length of the second portion of the conductive line of LI can be less than the length of the second portion of the conductive line of L2,..., LN. For example, consider Figure 4B is a top view, Figure 4B Conductive lines 407-1 and 407-2 illustrated in FIG. 4B can be formed on the top level LI of the vertical 3D array 440. Thus, conductive lines 407-1 and 407-2 can each include second portions 442-1 and 442-2 that are less than the length of the second portion of each conductive line on a lower level of the 3D array 440.

[0058] Figure 4C Also included are conductive line portions 438-1,..., 438-U oriented in a first horizontal direction (Dl) 409 and fourth portions 429 that extend in a horizontal direction (D2) 405 that is at an angle to the first horizontal direction (Dl) 409 and are coupled to a sense amplifier, one or more other circuit system components located within a sense amplifier region 435 via interconnects 437-1,..., 437-V.

[0059] For example, in the embodiment shown in Figure 4C In the embodiment illustrated in FIG. 4B, the third portion is in the first direction and the fourth portion is in the same direction as the second portion. This results in a cascading arrangement that allows for even more connections than in the embodiment of FIGS. 4A and 4B. As will be seen below, the cascading structure can be extended to include more portions, thereby allowing the structure to allow for even more connections than Figure 4C connections than shown in the embodiment illustrated in FIG. 4B.

[0060] Also, while the first and second portions and the third and fourth portions are shown as being perpendicular to each other, they can be at any suitable angle to achieve the cascading capabilities discussed herein. Also, while the first and third portions and the second and fourth portions are shown as being parallel to each other, they can be at any suitable angle to achieve the cascading capabilities discussed herein.

[0061] Figures 5A to 5T An example method for forming a vertically stacked array of memory cells is described in accordance with one or more embodiments of the present disclosure. Figure 5A is a top view illustrating a memory device configuration in accordance with a number of embodiments of the present disclosure.

[0062] As described, the memory device may include multiple 3D array regions 540-1, ..., 540-W (i.e., multiple memory cell arrays). Each of these array regions 540-1, ..., 540-W contains vertically stacked memory cells (e.g., ...). Figure 1 (Memory cell 110). Multiple memory cell array regions 540-1, ..., 540-W can be positioned in a configuration to form array 550. During formation, each of the memory cell array regions 540-1, ..., 540-W can be temporarily coupled to an adjacent array region 540-1, ..., 540-W in the same column via one or more bridges 546 (e.g., 546-1, ..., 546-Y) and one or more conductive line contact regions 547 (e.g., digital line contact regions 547-1, ..., 547-X), such as... Figure 5A As shown in the diagram. This coupling will be cut off later in the process, resulting in a single array with one or more bridges and conductive wire contact areas.

[0063] Figure 5B It is along Figure 5A A cross-sectional view taken from line A-A', for example... Figures 1 to 3 The stages of the process for forming a conductive line contact region having a plurality of multidirectional conductive lines and a stepped conductive line contact structure for a semiconductor device are described in the description and according to one or more embodiments of the present disclosure. Figure 5B As described herein, the method comprises forming alternating layers of a first dielectric material 530-0, 530-1, ..., 530D (collectively referred to as first dielectric material 530), a semiconductor material 532-0, 532-1, ..., 532-D (collectively referred to as semiconductor material 532), and a second dielectric material 533-0, 533-1, ..., 533-D (collectively referred to as second dielectric material 533) in repeated iterations, to achieve a similar effect to... Figure 2 A vertical stack 501 is formed on the working surface of the substrate 500 of the substrate 200. In some embodiments, the method may further include depositing a top layer of a first dielectric material 530 and a top layer of a second dielectric material 533 over alternating layers. Figure 5B As shown in Figures 4A to 4C, among the first, second, and third directions, the horizontal direction is described as a first horizontal direction (D3) similar to the first direction (D2) (e.g., the Y direction in the XYZ coordinate system). A second horizontal direction (D3) similar to that shown in Figures 4A to 4C is also described in Figure 5B as a second horizontal direction (D3) (e.g., the X direction in the XYZ coordinate system). The vertical direction (D1) (e.g., the Z direction in the XYZ coordinate system) is also... Figure 5B The vertical direction (D1) is illustrated and is similar to that shown in Figures 4A to 4C.

[0064] In some embodiments, the first dielectric material can be an interlayer dielectric (ILD). By way of example but not by way of limitation, the first dielectric material can include a silicon nitride (Si3N4) material (also referred to herein as (“SiN”)). In another example, the first dielectric material can include a silicon carbon oxide (SiOC) material, a silicon oxynitride (SiON) material (also referred to herein as “SiON”), and / or combinations thereof. Embodiments are not limited to these examples. x N Y ) material (also referred to herein as “SiON”), and / or combinations thereof. Embodiments are not limited to these examples.

[0065] In some embodiments, the semiconductor material can include a silicon material. The semiconductor material can be in a polycrystalline and / or amorphous state. For example, the semiconductor material can be a low-doped p-type (p-) silicon material. For example, the semiconductor material can be formed at a low concentration by gas-phase doping boron atoms (B) as an impurity dopant to form a low-doped p-type (p-) silicon material. In some embodiments, the low-doped p-type (p-) silicon material can be a polycrystalline silicon material. However, embodiments are not limited to these examples.

[0066] In some embodiments, the second dielectric material can be an interlayer dielectric (ILD). By way of example but not by way of limitation, the second dielectric material can include a nitride material. The nitride material can be a silicon nitride (Si x N4) material (also referred to herein as (“SiN”)).

[0067] In another example, the second dielectric material 533-0, 533-1,..., 533-D can include a silicon carbon oxide (SiOC) material. In another example, the second dielectric material can include a silicon oxynitride (SiON), and / or combinations thereof. Embodiments are not limited to these examples. However, according to some embodiments, the second dielectric material can be purposefully selected to be different in material or composition as compared to the first dielectric material such that a selective etching process can be performed on one of the first and second dielectric layers that is selective to the other (e.g., a second SiN dielectric material can be selectively etched with respect to the semiconductor material).

[0068] The repeated iterations of alternating first dielectric material 530-0, 530-1,..., 530-D layers, semiconductor material 532-0, 532-1,..., 532-D layers, and second dielectric material 533-0, 533-1,..., 533-D layers can be deposited according to a semiconductor manufacturing process such as chemical vapor deposition (CVD) in a semiconductor manufacturing facility. However, embodiments are not limited to this example, and other suitable manufacturing techniques can be used to deposit the alternating layers of first dielectric material, semiconductor material, and second dielectric material in the repeated iterations to form the vertical stack 501.

[0069] In Figure 5BIn the example, three levels of repeated iterations are shown. For example, the stack may include: a first dielectric material 530-1, a semiconductor material 532-1, a second dielectric material 533-1, a third dielectric material 530-2, a second semiconductor material 532-2, a fourth dielectric material 533-2, a fifth dielectric material 530-3, a third semiconductor material 532-3, and a sixth dielectric material 533-3. Therefore, in further repeated iterations, the stack may include: a first oxide material 530-1, a first semiconductor material 532-1, a first nitride material 533-1, a second oxide material 530-2, a second semiconductor material 532-2, a second nitride material 533-2, a third oxide material 530-D, a third semiconductor material 532-D, and a third nitride material 533-D. However, the embodiments are not limited to this example and may include more or fewer repeated iterations.

[0070] Readers should note that, although Figure 5A or Figure 5B Not specified, but multiple trenches can be formed between multiple rows of interconnects in the memory cell array. These trenches can be configured such that conductive lines can be formed therein. Conductive lines formed in these trenches can be referred to as "undercut" or "embedded" conductive lines.

[0071] Figure 5C This is a top view of another stage of a method for forming a vertically stacked array of memory cells with horizontally oriented digital lines and vertically oriented access lines. (Example) Figure 5C As shown, conductive lines 507-1, ..., 507-4 may be formed in the second dielectric (e.g., Figure 5B Within 533-0, 533-1, ..., 533-D). The conductive lines in this disclosure include portions that are angled relative to each other (e.g., 541-1, 542-1, 543-1, 544-1, 545-1, 551-1 and 541-2, 542-2, 543-2, 544-2, 545-2, 551-2), for example, when they advance through array regions 540-1, ..., 540-W, bridges 546-1, ..., 546-Y, and conductive line contact regions 547-1, ..., 547-X, as... Figure 5C As shown in the figure. For example, these conductive lines 507-1, ..., 507-4 may be aligned with the edges of the periphery of the array area, bridge, and / or conductive line contact area (i.e., typically travel parallel to the edges of the array area 540, bridge 546, or conductive line contact area 547, as shown). In some embodiments, the conductive lines may be undercut or embedded.

[0072] Figure 5D For example, in Figures 1 to 3 The description and various embodiments of this disclosure are described below.Figure 5C a cross-sectional view taken along the line A-A' illustrating a stage of a method for forming conductive line contact regions having a plurality of multi-directional conductive lines and stepped conductive line contact structures.

[0073] In some embodiments, conductive lines can be formed within one or more layers of the second dielectric material 533-0, 533-1,..., 533-D of the stack. This can be accomplished by a conductive line formation process that includes, for example, selectively removing the second dielectric material 533-0, 533-1,..., 533-D (e.g., to form first horizontal openings by removing the second dielectric material a first distance back from a reference line 562 (e.g., a center line in a vertical opening between memory cell stacks 501)).

[0074] The conductive line formation process can further include depositing a conductive material into the vertical openings. In some embodiments, this can include conformally depositing a conductive material into a portion of the vertical openings (e.g., using a chemical vapor deposition (CVD) process) such that the conductive material can also be deposited into the first horizontal openings. In some embodiments, the conductive material can include a titanium nitride (TiN) material. The conductive material can form horizontally (e.g., laterally) oriented digit lines.

[0075] The conductive material can then be recessed in the horizontal openings (e.g., etched away from the vertical openings using reactive ion etching or other suitable technique). In some examples, the conductive material can be recessed back into the horizontal openings a second distance from the vertical openings to form digit lines. The conductive material can be selectively etched, leaving intact portions of the dielectric material 530, the conductive material, and the semiconductor material 532. The conductive material can be etched to define a desired conductive line width. In some embodiments, an atomic layer etching (ALE) process can be used to etch the conductive material. In some embodiments, an isotropic etching process can be used to etch the conductive material.

[0076] Accordingly, the conductive material can be selectively removed a second distance back from the vertical openings, forming smaller horizontal openings between the first dielectric 530-0,..., 530-D and the semiconductor 532-0,..., 532-D layers. A third dielectric 531-L can then be deposited into each of the horizontal openings laterally adjacent to the conductive material. In some embodiments, the third dielectric material 531-L can be the same as or similar to the second dielectric material 533. For example, in some embodiments, the second and third dielectric materials can each include a nitride material.

[0077] The third dielectric material 531-L can be recessed to a second distance from the reference line 562 to be removed from the first vertical openings and to maintain the first vertical openings to allow deposition of conductive material to form direct electrical contacts between such conductive material deposited within the vertical openings and the low doped semiconductor material 532-0,..., 532-D (e.g., body region contacts) of horizontally oriented interconnects (e.g., access devices) Figure 5D not depicted) within the memory cell array region 540. In some embodiments, the third dielectric material 531-L can be removed from the vertical openings to expose the sidewalls of the first dielectric material 530-0,..., 530-D, the third dielectric material 531-L, and the semiconductor material 532-0,..., 532-D.

[0078] Figure 5E is a top-down view of another stage of a method for forming conductive line contact regions having multiple multi-directional conductive lines and stepped conductive line contact structures for semiconductor devices in accordance with one or more embodiments of the present disclosure. For simplicity, Figure 5E the upper half of a memory cell structure is illustrated (e.g., as shown in Figure 5C however, the description of the method described with respect to Figure 5E also applies to those elements in the lower half of the memory cell structure.

[0079] This method can include depositing a conductive material 576 (e.g., polysilicon) over, around, or between, for example, one or more memory cell regions 540-1,..., 540-W, the bridges 546-1,..., 546-Y, and the digit line contact regions 547,..., 547-X for body bias control during this portion of the formation process. The conductive material 576 can include, for example, a conductive polymer material. In some embodiments, the conductive material 576 can form to the doped body contacts of the multiple interconnects described in conjunction with Figure 4B The conductive material 576 can also be etched back as needed.

[0080] While Figure 5E only two memory cell regions 540-1 and 540-2 are illustrated, embodiments of the present disclosure are not so limited. For example, the conductive material 576 can be deposited between or around groups of memory cell array regions of arrays (e.g., four cell arrays 550 as illustrated in Figure 5A and 5C other arrangements of cell arrays.

[0081] Figure 5F is a cross-sectional view of line A-A' in Figure 5E which is similar to line A-A' in Figure 5C and line A-A' in Figure 5A As Figure 5FAs shown in Figure 5E The process described, the memory cell array region (e.g., Figure 5E The vertical openings 571 between the regions 540-1 and 540-2 in

[0082] Figure 5G is a top-down view of another stage of a method for forming conductive line contact regions having multiple multi-directional conductive lines and stepped conductive line contact structures for semiconductor devices in accordance with one or more embodiments of the present disclosure. As Figure 5G As shown in Figure 5G Although not shown in

[0083] Figure 5H is a cross-sectional view taken along line B-B' of Figure 5G described in conjunction with Figure 5G . Figure 5H Portions 543-1 and 543-2 of the conductive lines 507-1 and 507-2 of Figure 5G have been formed at this stage are illustrated. However, embodiments of the present disclosure are not limited thereto. For example, in some embodiments, the regions of conductive lines illustrated in Figure 5H may include empty trenches, and those trenches can be filled with conductive material at a later stage to form the conductive lines. Figure 5H Conductive line portions 543-5 and 543-6 and portions 543-9 and 543-10 of digit lines formed below the conductive lines 507-1 and 507-2 shown in Figure 5G

[0084] Figure 5I is a top-down view of another stage of a method for forming conductive line contact regions having multiple multi-directional conductive lines and stepped conductive line contact structures for semiconductor devices in accordance with one or more embodiments of the present disclosure. As Figure 5I As shown in In some embodiments, the fourth dielectric material 537 can be similar to or the same as the first dielectric material 530. For example, in some embodiments, the first dielectric material 530 and the fourth dielectric material 537 can each include an oxide material.

[0085] Figure 5J is a cross-sectional view taken along line B-B' of Figure 5I described in conjunction withFigure 5I The cross-sectional view taken by line B-B'. (Similar to...) Figure 5I , Figure 5J The fourth dielectric material 537 can be deposited into the region on the side of the stack.

[0086] Figure 5K This is a top view of another stage of a method for forming conductive line contact regions having a plurality of multidirectional conductive lines and stepped conductive line contact structures for a semiconductor device, according to one or more embodiments of the present disclosure. In some embodiments, a hard mask material (e.g., a photoresist layer) may be deposited over portions 592 of array regions 540-1, 540-2. In other embodiments, the hard mask material may be deposited over portions of each memory array region. The hard mask material may be used to protect the memory cell array regions and body contacts throughout the remainder of the process described herein.

[0087] In some embodiments, a photoresist layer may be deposited over region 592. The photoresist layer may act as a protective layer to keep portions of the memory cell array that are not removed intact during the stair-stepping process.

[0088] In addition, such as Figure 5K As shown, a portion of the array area (e.g., 540-1 and 540-2) containing the digital lines (e.g., 542-1 and 542-2) can be exposed for further processing, as described in more detail below. In this way, a part of the staircase structure can be formed.

[0089] Figure 5L Explanation along Figure 5K The cross-sectional view taken by line C-C'. In other words, Figure 5L Explanation along Figure 5K The cross-sectional views of the second portions 542-1 and 542-2 of the conductive wire shown are as follows. Figure 5L As described herein, each memory cell region comprises a vertical stack of horizontally oriented conductive lines, each conductive line including a portion 542 extending in the horizontal direction.

[0090] Each memory cell region may contain multiple groups of layers (e.g., 539-1, 539-2, 539-3), wherein each group of layers contains a first dielectric material layer 530-0, ..., 530-D, a semiconductor material layer 532-0, ..., 532-D, and a second dielectric material layer 533-0, ..., 533-D. The second dielectric material has one or more conductive lines formed therein.

[0091] For example, the second dielectric material layers 533-0, ..., 533-D of each group of layers 539-0, ..., 539-2 may include a second portion 542 of one or more conductive lines. Each memory cell 540-1, ..., 540-W may be contained in a layer 533 of the second dielectric material above the top group of layers 539-2.

[0092] Figure 5M This is a top view of a stage in a method embodiment according to one or more embodiments of the present disclosure for forming a conductive line contact area having a plurality of multidirectional conductive lines arranged in odd and even patterns for a semiconductor device and a stepped conductive line contact structure. Figure 5M As shown, in some embodiments, each conductive wire may include a third portion (e.g., 543-1, ..., 543-4) extending in a third horizontal direction at an angle to the second horizontal direction. In some embodiments, such as Figure 5M As shown, the third part 543-1, ..., 543-4 can extend at an angle perpendicular to the second part 542-1, ..., 542-4 and parallel to the first part 541-1, ..., 541-4.

[0093] In some embodiments, the masking, patterning, and etching processes can be combined with selectively open areas, for example, through... Figure 5M The rectangular identifiers 594 shown (e.g., areas 594-1, ..., 594-2) are used together to form a stepped structure as described below. Each area may be a region spanning multiple areas of the array structure. For example, the area may include portions of array area 540, bridge 546, and conductive line contact area 547.

[0094] Zone 594 may include combinations such as Figure 5L The described layers are vertically stacked groups, and material can be removed from each zone to form, for example... Figure 5S The structures shown are as follows. For example, zones 594-1, ..., 594-2 may comprise vertically stacked groups of layers, wherein each group of layers comprises a first dielectric layer, a semiconductor layer, and a second dielectric layer having conductive lines formed therein. For example, zones 594-1, ..., 594-2 may comprise groups of layer groups 539-0, ..., 539-2, such as... Figure 5L As shown in the image.

[0095] Figure 5M Zones 594-1 to 594-7 are the lowest levels of the already opened zones, forming a ladder, for example in... Figure 5S The diagram in 5M shows level 535-1. As the reader will understand, the diagram in 5M represents the lowest level used to form the steps and the opening area located directly above those sections of the staircase. Therefore, when forming other levels of the steps, for example...Figure 5S As shown in 535-2 and 535-3, different regions will be opened to form those structures.

[0096] One method that can be used to form these steps involves two processes. First, an etching trimming sequence can be used to form the step itself, and subsequently, cutting or shredding a mask can be used to reduce the stepped structure to the desired level of a layered stack. Typically, a series of steps are formed, for example in... Figure 5S The three steps shown in C1-C1' (e.g., in) Figure 5S (as shown in 535-1, 535-2, and 535-3), and then the entire series of steps are introduced to their desired levels (e.g., in) through a cutting or shredding mask process. Figure 5S (as shown in vd-2, vd-3, and vd-4). For deeper layers, more than one cutting or shredding mask can be used.

[0097] Additionally, if multiple steps (e.g., three levels of a staircase) are formed in different locations (e.g., Figure 5R In some embodiments, all staircases (C1-C1', C2-C2', C3-C3') can be formed at the same level (e.g., all sets of stairs are formed at vertical depths of vd-1, vd-2, vd-3), and subsequent different cutting or shredding masking processes can be used to lower these sets of stairs to different levels. For example, in Figure 5S The two steps shown at C1-C1' and C3-C3' may initially have vertical depths of vd-1, vd-2 and vd-3, but further cutting or shredding masking can be done at C3-C3' to lower the set of steps to vd-8, vd-9 and vd-10.

[0098] For example, a hypothetical reference line could be drawn through the center of each memory cell array to provide the reader with a reference when discussing the formation process in this article. Vertical openings could be formed, such as... Figure 5N As described in the document. In some embodiments, the reference line may be centered in the vertical opening. In some embodiments, the vertical opening may be centered around the intersection of the reference line and line C-C'.

[0099] Figure 5N It is along Figure 5M The cross-sectional view taken by line C-C'. (See figure) Figure 5NAs shown in FIG. 5A, a vertical opening 580 can be formed through layers within a vertical stack of memory cells to expose vertical sidewalls in the vertical stack. A notional reference line 564 can pass through the center of each memory cell array region. The vertical opening 580 can be formed. In some embodiments, the reference line 564 can be in the center of the vertical opening 580. In some embodiments, the vertical opening 580 can be centered around the intersection of the reference line 564 and the line C-C’.

[0100] The vertical opening 580 can have a first horizontal width (w1) and a first vertical depth (vd-1) as shown in FIG. 5A. The vertical opening 580 can be formed by selectively removing the top layer 538, 533 and then removing one or more groups of layers in the group of layers 539-0,..., 539-2 of the vertical stack. One or more layers of the vertical stack are selectively removed a first distance on each side of the reference line 564 (i.e., a first distance to the left of the reference line 564 and a first distance to the right of the reference line 564). Figure 5N Figure 5N The vertical opening 580 can have a first horizontal width (w1) and a first vertical depth (vd-1) as shown in FIG. 5A. The vertical opening 580 can be formed by selectively removing the top layer 538, 533 and then removing one or more groups of layers in the group of layers 539-0,..., 539-2 of the vertical stack. One or more layers of the vertical stack are selectively removed a first distance on each side of the reference line 564 (i.e., a first distance to the left of the reference line 564 and a first distance to the right of the reference line 564).

[0101] In some embodiments, the vertical opening 580 can be formed through the mask 538 and the second dielectric material 533. Forming the vertical opening 580 can include removing a first portion of the mask 538 and a first portion of the second dielectric layer 533. The first portion of the mask 538 and the second dielectric material layer 533 can be equal in horizontal length. Although not shown in FIG. 5A, in some embodiments where the mask 538 has not yet been deposited over the vertical stack 501, the vertical opening 580 can be formed through a top layer of the first dielectric material 530-D and / or a top layer of the second dielectric material 533. Figure 5N As shown in FIG. 5A, the vertical stack can include a layer of the second dielectric material 533 having a portion 542 of a digit line formed therein. In some embodiments, the vertical opening 580 can be formed by removing each layer of material between the top of the vertical stack and the first layer of the first dielectric material 530-D.

[0102] Figure 5N As shown in FIG. 5A, the vertical stack can include a layer of the second dielectric material 533 having a portion 542 of a digit line formed therein. In some embodiments, the vertical opening 580 can be formed by removing each layer of material between the top of the vertical stack and the first layer of the first dielectric material 530-D.

[0103] As shown in FIG. 5A, the vertical stack can include a plurality of levels (also referred to as tiers) 539-0,..., 539-2 (e.g., three tiers as shown in FIG. 5A). Figure 5N Figure 5N As shown in FIG. 5A, the vertical stack can include a plurality of levels (also referred to as tiers) 539-0,..., 539-2 (e.g., three tiers as shown in FIG. 5A).

[0104] As shown in FIG. 5A, the vertical stack can include a plurality of levels (also referred to as tiers) 539-0,..., 539-2 (e.g., three tiers as shown in FIG. 5A).​​​Figures 5O to 5S , Figure 5T , Figures 6A to 6C more detail, the method of forming the various levels of the array region can be repeated in any number of iterations to form multiple levels of conductive line contacts at more than two levels. For example, the method can be repeated in multiple iterations in order to form eight levels of conductive line contacts, as illustrated in Figures 5O to 5S , Figure 5T , Figures 6A to 6C .

[0105] Figure 5O is a cross-sectional view taken along line C-C' of 5M, illustrating another stage of a method for forming a conductive line contact region having multiple multi-directional conductive lines and stepped conductive line contact structures for semiconductor devices, according to one or more embodiments of the disclosure. In this embodiment, the stack has more layers 530, 532, 533 and thus a group of layers 539. Figure 5M The vertical depth of the vertical openings can be increased to a second vertical depth "vd-2". This can be accomplished by removing a portion of the layer of second dielectric material 533, where the layer also contains the first portions 542-1 and 542-2 of the conductive lines formed therein. A portion of the layer of semiconductor material 532 can also be removed. At this stage, the openings into the layers 533 (top layer), 530, 533, and 532 all have the same width as the width wl, as shown in

[0106] . Figure 5O

[0107] Figure 5P is a cross-sectional view taken along line C-C' of 5M, illustrating another stage of a method for forming a conductive line contact region having multiple multi-directional conductive lines and stepped conductive line contact structures for semiconductor devices, according to one or more embodiments of the disclosure. In this embodiment, the stack has more layers 530, 532, 533 and thus a group of layers 539. Figure 5M Figure 5M The method includes creating a first level 548-1 and a second level 548-2 that are different than the remaining portions of the layers in the vertical stack of levels 548-3.

[0108] This can be accomplished by removing a first portion of each layer in the first group of layers from the reference line 564 back a second distance 535-2 on either side, where the second distance 535-2 is greater than the first distance 535-1. And, by removing a first portion of each layer in the second group of layers from the reference line 564 back a first distance 535-1 on either side, where the second distance 535-2 is greater than the first distance 535-1. This will also form two different depths vd-2 (for the top / first level 548-1) and vd-3 (for the second level 548-2).

[0109] ​​In some embodiments, top level 548-1 can include a mask (e.g., a photoresist layer), a top second dielectric material layer 533 with portions of digit lines formed therein, a first dielectric material layer 530, a second dielectric material layer 533, and a semiconductor material layer 532, not shown in Figure 5P However, embodiments of the disclosure are not limited in this regard.

[0110] Figure 5Q Formation of a third level 548-3 including a semiconductor material layer, conductive lines, and a first dielectric material layer is illustrated. The method includes creating a first level 548-1, a second level 548-2, and a third level 548-3 that are different from the remaining portions of the layers in the vertically stacked levels 548-4. This can be accomplished by removing a portion of each layer in a first group of layers 548-1 back a third distance 535-3 from the reference line 564 on either side, where the third distance 535-3 is greater than the first distance 535-1 and the second distance 535-2. Also, by removing a portion of each layer in a second group of layers 548-2 back a second distance 535-2 from the reference line 564 on either side, where the second distance 535-2 is greater than the first distance 535-1. And, further, by removing a portion of each layer in a third group of layers 548-3 back a first distance 535-1 from the reference line 564 on either side, where the second distance 535-2 is greater than the first distance 535-1. This will also form three different depths vd-2 (for the first level 548-1), vd-3 (for the second level 548-2), and vd-4 (for the third level 548-3).

[0111] Figure 5R A top view illustrating another stage of a method of forming conductive line contact regions having multiple multi-directional conductive lines and stepped conductive line contact structures for semiconductor devices according to one or more embodiments of the disclosure is illustrated. Lines CI - CI'run along second portions 542-1 and 542-2, lines C2-C2' run along fourth portions 544-1 and 544-2, and lines C3-C3' run along second portions 551-1 and 551-2. As discussed below, each of these regions is formed differently to allow for the formation of connections to different levels of the stack.

[0112] Figure 5S Cross sections taken along lines CI - CI ', C2-C2', and C3-C3' of Figure 5R are illustrated, which illustrate different structures that can be used to access different levels of the stack. Each cross section includes the same vertical stack of layers of horizontally oriented digit lines and a first dielectric material 530, a semiconductor material 532, and a second dielectric material 533, but at different lines of sight, different stepped patterns formed in different locations within the stack are seen. As in the previous figures, the different stepped patterns are formed by removing portions of the layers in the stack to different depths.Figure 5S As explained in Figure 5S understood, the number of layers in the group of layers 548-4 can vary based on the layers to be accessed to contact the sense amplifiers or other circuitry.

[0113] In the representation on the left side of Figure 5S , the multiple levels 548-1, 548-2, and 548-3 can be accessed at depths vd-2, vd-3, and vd-4 in the stack. Further, in the representation in the middle of Figure 5S , the multiple levels 548-1, 548-2, and 548-3 can be accessed at depths vd-5, vd-6, and vd-7 in the stack, and in the representation on the left side of Figure 5S , the multiple levels 548-1, 548-2, and 548-3 can be accessed at depths vd-8, vd-9, and vd-10 in the stack. This is accomplished by vertical openings having widths 535-1, 535-2, and 535-3 that are different from the reference line 564. While three widths are illustrated, any suitable number of widths can be formed.

[0114] Using this stepped structure allows for direct vertical contact to the sense amplifiers or other circuitry, as illustrated in Figures 6A to 6C . In the embodiment illustrated in Figure 5S , this allows for contact to nine conductive lines of the sense amplifiers or other circuitry, thereby providing an increased density of conductive line contact areas that can not have been previously provided. The reader will understand that this stepped concept can be used to connect conductive lines to many (e.g., hundreds) of sense amplifiers or other circuitry.

[0115] Figure 5T A top view illustrating an example of a multiple connections and their example arrangement on a conductive line contact area having multiple multi-directional conductive lines according to one or more embodiments of the disclosure is illustrated. This figure illustrates the vertical connection areas in which contact between a digit line and a sense amplifier can be made. While as illustrated, each horizontal digit line area has three vertical connection areas in which a contact can be positioned, more or fewer areas can be provided based on the space available for connection. In the illustrated illustration, the left side of the left array has three connection areas along each horizontal conductive line portion. For example, the sites labeled 0, 1, and 2 will each connect with a second portion 542 / 642 of a different vertical level of a vertical stack, as shown in Figure 6A . Figure 5TEach array shown has nine available interconnect locations (labeled 0, 1, 2, 3, 4, 5, 6, 7, 8); however, embodiments of this disclosure may have more or fewer interconnect locations. As can be understood based on the interconnect location numbering, the regions with interconnects 876-678 and the regions with interconnect locations 210-012 are configured as valleys, such as at C1-C1' and C3-C3'. Figure 5S As shown, the regions with interconnection locations 345-543 are configured as peaks, such as at C2-C2'. Figure 5S As shown in the diagram. Providing more horizontal sections (and corresponding vertical levels) can create more connecting areas.

[0116] Figure 6A It is along Figure 5R The cross-sectional view taken from line C1-C1'. Figure 6A It is along Figure 5R The cross-sectional view taken from line C2-C2'. Figure 6C It is along Figure 5R Cross-sectional views taken along line C3-C3'. These figures illustrate other example stages of a method for forming a conductive line contact region having a plurality of multidirectional conductive lines and a stepped conductive line contact structure for a semiconductor device, according to one or more embodiments of the present disclosure.

[0117] In some embodiments and as Figures 6A to 6C As shown, a fourth dielectric material 637 may be deposited into the vertical opening 680. The fourth dielectric material 637 may be similar in composition to the first dielectric material 630. For example, in some embodiments, the first dielectric material 630 and the fourth dielectric material 680 may each comprise an oxide material.

[0118] exist Figures 6A to 6C The different levels of the numerical lines 642, 644, and 651 described herein can correspond to the following: Figure 5R The different levels of the numerical lines 542, 544, and 551 are explained in the text. For example... Figure 4C China and Figures 6A to 6C As shown, multiple sense amplifiers or other circuitry can each be coupled to a digital line via interconnect 634. Each level of the vertical stack can include digital lines 642, 644, or 651 coupled to the sense amplifiers or other circuitry via interconnect 634 on either side of reference line 664. In some embodiments, the length of each digital line portion 642, 644, and 651 in the vertical stack 601 can be greater than the length of the corresponding digital line 642, 644, or 651 above it in the vertical stack 601.

[0119] like Figures 6A to 6CAs explained in the middle, each interconnect 634 can be coupled to a conductive line portion 642, 644, or 651 at or near an end of the conductive line portion 642, 644, or 651 (i.e., near an end of a given level 648). In some embodiments, since there are two conductive lines in each array region (e.g., array region 504-1) of Figure 5C the number of interconnects 634 can be equal to twice the number of levels 648. For example, as Figure 6A explained in the middle, a three-level staircase structure can have six interconnects as shown (e.g., in a folded digit line architecture).

[0120] Figure 7 is a top-down view of a 3D memory array illustrating another embodiment of the disclosure. In this embodiment, as Figure 7 explained in the middle, conductive lines (707-1, 707-2) can be formed with a multi-pronged arrangement (as viewed from above the vertical stack, as Figure 7 explained in the middle) such that a first portion 741 (e.g., 741-1, 741-2) of the conductive lines is aligned in a first direction D1 (e.g., aligned with a side of the memory array) and a second portion 742 (e.g., each on a different level of the vertical stack) is angled (e.g., in direction D2) from the first portion. The second portion 742 is also laterally spaced apart (e.g., arranged parallel to each other) to allow a vertical interconnect to be formed for each segment 742.

[0121] In some embodiments, each secondary portion 742-1,..., 742-G can extend perpendicular to the angle of the first portion 741. In other words, the first portion 741 can extend in the D1 direction and the secondary portions 742-1,..., 742-G can each extend in the D2 direction. For example, Figure 7 illustrates four secondary portions 742-1,..., 742-G of conductive lines 707-1 and 707-2 extending in a second direction D2 that is perpendicular to a first direction D1 of first portions 741-1 and 741-2 of conductive lines 707-1 and 707-2, respectively.

[0122] For example, each secondary portion 742-1,..., 742-G can be interconnected to a sense amplifier or other circuitry contact 755 via a contact jumper 749. In some embodiments, the number of contact jumpers 749 to a sense amplifier or other circuitry coupled to each secondary portion 742-1,..., 742-G can be equal to the number of secondary portions 742-1,..., 742-G of each conductive line. Although Figure 7 illustrates four secondary portions 742-1,..., 742-G, embodiments of the disclosure can have any other suitable number of secondary portions.

[0123] Each contact jumper 749 can be coupled to a conductive line 707 through an interconnect 734. The interconnect 734 can include an interconnect to a source / drain region. In some embodiments, the source / drain region can be formed within a semiconductor material. In some embodiments, the secondary portions 742-1,..., 742-G can be approximately equally spaced apart from one another. The contact jumpers 749 coupled to the top tines of the secondary portions 742-1,..., 742-G can be aligned in columns CI, C2, C3, and C4. Another suitable arrangement is shown below in Figure 8

[0124] Figure 8 is a top view illustrating another embodiment of a multiple multi-directional conductive line structure and stepped contact configuration structure for a memory device. As illustrated in Figure 8

[0125] Figure 9 is a top view illustrating another embodiment of a multiple multi-directional conductive line structure and stepped contact configuration structure for a memory device. As illustrated in Figure 9 ​​As explained in the background, each conductive line 907 (e.g., 907-1, 907-2) can include a first portion 941 (e.g., 941-1, 941-2) that extends along an edge of the body contact. Each conductive line 907 can further include a secondary portion 942-1,..., 942-G that extends at an angle perpendicular to the first portion 941-1, 941-2. Each secondary portion 942-1,..., 942-G can be coupled to one of a plurality of contact crossbars 949 of a sense amplifier by one of a plurality of interconnects 934. Each contact crossbar 949 can be coupled to the sense amplifier at region 935 by one of a plurality of sense amplifier contacts 955. One or more of the contact crossbars 949 can include a first portion that extends in a first direction Dl, and a second portion that extends in a second direction D2 and is coupled to the secondary portions 942-1,..., 942-G of the conductive line 907 by the interconnect 934. One or more of the contact crossbars 949 can include only a first portion that extends in the first direction Dl and is coupled to the secondary portions of the conductive line 942-1,..., 942-G by the interconnect 934.

[0126] Figure 10 Figure 1 is a block diagram of an apparatus in the form of a computing system 1000 including a memory device 1003, according to embodiments of the present disclosure. As used herein, a memory device 1003, a memory array 1010, and / or a host 1002 can also be considered individually as an “apparatus,” for example. According to embodiments, a memory device 1002 can include at least one memory array 1010 having memory cells formed by conductive line contacts having a plurality of multi-directional conductive lines and stepped conductive line contact structures, according to embodiments described herein.

[0127] In this example, the system 1000 includes a host 1002 coupled to the memory device 1003 via an interface 1004. The computing system 1000 can be a personal laptop computer, a desktop computer, a digital camera, a mobile telephone, a memory card reader, or an Internet of Things (IoT) enabled device, among various other types of systems. The host 1002 can include a processing resource (e.g., one or more processors, microprocessors, or some other type of controlling circuitry) capable of accessing the memory 1003. The system 1000 can include separate integrated circuits, or both the host 1002 and the memory device 1003 can be on the same integrated circuit. For example, the host 1002 can be a system controller of a memory system that includes a plurality of memory devices 1003, where the system controller 1005 provides access to the respective memory devices 1003 by another processing resource, such as a central processing unit (CPU).

[0128] In Figure 10In the example shown, host 1002 is responsible for executing an operating system (OS) and / or various applications (e.g., processes) that can be loaded onto it (e.g., from memory device 1003 via controller 1005). The OS and / or various applications can be loaded from memory device 1003 by providing access commands from host 1002 to memory device 1003 for accessing data comprising the OS and / or various applications. Host 1002 can also access data utilized by the OS and / or various applications by providing access commands to memory device 1003 for retrieving the data utilized in executing the OS and / or various applications.

[0129] For clarity, system 1000 has been simplified to focus on features relevant to the present disclosure. Memory array 1010 can be a DRAM array including at least one memory cell having a conductive line contact region having a plurality of multi-directional conductive lines and stepped conductive line contact structures formed according to the techniques described herein. For example, memory array 1010 can be a shieldless DL 4F2 array, such as a 3D-DRAM memory array. Array 1010 can include memory cells arranged in rows coupled by word lines (which can be referred to herein as access lines or select lines) and columns coupled by digit lines (which can be referred to herein as sense lines or data lines). While a single array 1010 is shown in Figure 1 A single array 1010 is shown in the example, but embodiments are not so limited. For example, memory device 1003 can include multiple arrays 1010 (e.g., multiple banks of DRAM cells).

[0130] The memory device 1003 includes address circuitry 1006 to latch address signals provided by the interface 1004. The interface can include a physical interface employing a suitable protocol (e.g., a data bus, an address bus, and a command bus, or a combined data / address / command bus). Such a protocol can be custom or proprietary, or the interface 1004 can employ a standardized protocol, such as Peripheral Component Interconnect Express (PCIe), Gen-Z, CCIX, etc. Address signals can be received and decoded by a row decoder 1008 and a column decoder 1012 to access the memory array 1010. Data can be read from the memory array 1010 by sensing voltage and / or current changes on the sense lines with the use of sense circuitry 1011. For example, the sense circuitry 1011 can include a sense amplifier that can read and latch a page (e.g., a row) of data from the memory array 1010. I / O circuitry 1007 can be used for bidirectional data communication between the interface 1004 and the host 1002. Read / write circuitry 1013 is used to write data to and read data from the memory array 1010. As an example, the circuitry 1013 can include various drivers, latching circuitry, etc.

[0131] The control circuitry 1005 decodes signals provided by the host 1002. The signals can be commands provided by the host 1002. These signals can include chip enable signals, write enable signals, and address latch signals used to control operations performed on the memory array 1010, including data read operations, data write operations, and data erase operations. In various embodiments, the control circuitry 1005 is responsible for executing instructions from the host 1002. The control circuitry 1005 can include a state machine, a sequencer, and / or some other type of control circuitry, which can be implemented in hardware, firmware, or software, or any combination of the three. In some examples, the host 1002 can be a controller external to the memory device 1003. For example, the host 1002 can be a memory controller coupled to a processing resource of a computing device.

[0132] The term semiconductor can refer to a material, a wafer, or a substrate, and includes any base semiconductor structure, for example. A “semiconductor” should be understood to include silicon-on-sapphire (SOS) technology, silicon-on-insulator (SOI) technology, thin-film transistor (TFT) technology, doped and undoped semiconductors, epitaxial semiconductors supported by base semiconductor structures, as well as other semiconductor structures. Furthermore, when reference is made to a semiconductor, previous processing steps can have been utilized to form regions / junctions in the base semiconductor structure, and the term semiconductor can include the underlying material containing these regions / junctions.

[0133] As should be appreciated, elements from the various embodiments described herein can be added, exchanged, and / or removed to provide a number of additional embodiments of the disclosure. Still further, as will be appreciated, the proportion and the relative scale of the elements provided in the figures are intended to illustrate embodiments of the present disclosure and should not be taken in a limiting sense.

[0134] As used herein, "plurality" or "a number of" something can refer to one or more of such things. For example, a plurality or a number of memory units can refer to one or more memory units. A plurality of something intends two or more. As used herein, a plurality of actions performed simultaneously refers to actions that at least partially overlap in a particular time period. As used herein, the term "coupled" can include electrically coupled, directly coupled, and / or directly connected (e.g., through direct physical contact) without intervening elements, or indirectly coupled and / or connected with intervening elements, or coupled in a wireless manner. The term "coupled" can further include two or more elements that cooperate or interact with each other (e.g., as in a cause an effect relationship). An element coupled between two elements can be between and coupled to each of the two elements.

[0135] As used herein, the term "secondary portion" can be used synonymously with the term "second portion," meaning a portion that extends in a different direction than a "first portion" or "primary portion." For example, a first portion can extend in a first direction, and a plurality of secondary portions can extend in a second direction that is perpendicular to the first direction.

[0136] The terms "first portion" and "second portion" can be used herein to refer to two portions of a single element. For example, a "first portion" of a digit line and a "second portion" of a digit line can refer to two portions of a single digit line. It is not intended that the portions that are "first" and / or "second" have some unique meaning. It is only intended that one of the "portions" extends in a different direction than the other of the "portions."

[0137] It should be recognized that the term "vertical" accounts for variations from "perfect" vertical due to normal manufacturing, measurement, and / or assembly variations, and the meaning of the term "vertical" would be known to one of ordinary skill in the art. For example, vertical can correspond to the z-direction. As used herein, when a particular element is "adjacent" to another element, the particular element can cover the other element, can be above or lateral to the other element, and / or can be in direct physical contact with the other element. For example, lateral can refer to a horizontal direction (e.g., y-direction or x-direction) that can be perpendicular to the z-direction.

[0138] While specific embodiments have been illustrated and described herein, it will be appreciated that various modifications to the illustrated embodiments will occur to those skilled in the art. It is intended that the disclosure cover adaptations, modifications, permutations, combinations, and alterations of various embodiments of the present disclosure. It should be understood that the above descriptions have been presented only as examples and not limitation. It is intended that the scope of various embodiments of the present disclosure be limited only by the claims as set forth below and their equivalents.

Claims

1. A memory device having a vertically stacked array of memory cells, the vertically stacked array of memory cells having a plurality of multidirectional conductive lines, the memory device comprising: Vertical stacking of layers formed by repeated iterations of grouped layers. The group of layers includes: a first dielectric material layer, a semiconductor material layer, and a second dielectric material layer, the second dielectric material layer having horizontally oriented conductive lines formed therein in a horizontal plane; and The vertical stack of layers has multiple multidirectional conductive lines in an interconnect region, the interconnect region having a first portion formed in an array region and a second portion formed in a conductive line contact region spaced apart from the array region.

2. The memory device of claim 1, wherein the vertically stacked memory cell array further comprises a plurality of horizontally oriented access devices, wherein each horizontally oriented access device is electrically coupled at an end of a second portion of a plurality of multidirectional conductive lines to the second portion of the plurality of multidirectional conductive lines in the vertical stack.

3. The memory device of claim 1, wherein the length of the second portion of each of the plurality of multidirectional conductive lines is greater than the length of the second portion of the plurality of multidirectional conductive lines at the next higher level.

4. The memory device of claim 2, further comprising a vertical body contact formed to be in direct electrical contact with one or more of the plurality of horizontally oriented access devices.

5. The memory device of claim 2, wherein each of the plurality of horizontally oriented access devices is electrically coupled to the second portion of one of the plurality of multidirectional conductive lines in the vertical stack.

6. The memory device of claim 5, wherein each of the plurality of horizontally oriented access devices is electrically coupled to a sensing amplifier.

7. The memory device of claim 1, wherein each of the plurality of multidirectional conductive lines includes a first portion extending in a first horizontal direction, a second portion extending in a second horizontal direction at an angle to the first horizontal direction, and a third portion extending in the first horizontal direction.

8. The memory device according to claim 1, wherein the memory device is a three-dimensional (3D) dynamic random access memory device.

9. The memory device of claim 2, further comprising a vertical body contact formed to directly electrically contact one or more of the plurality of horizontally oriented access devices.

10. The memory device of claim 9, wherein the vertical body contact is separated from the horizontally oriented conductive line by a third dielectric.

11. The memory device of claim 10, further comprising a horizontally oriented memory node, the horizontally oriented memory node including capacitor cells.

12. The memory device of claim 9, wherein the plurality of horizontally oriented access devices comprise transistor units.

13. The memory device of claim 1, wherein the conductive line contact area has a plurality of multidirectional conductive lines, each multidirectional conductive line having a first and a second portion, and wherein the second portions are laterally spaced apart from each other.

14. A method for forming a vertically stacked array of memory cells having a plurality of multidirectional conductive lines, the method comprising: Multiple layers are formed in a vertically repeated iteration to form a vertical stack, the layers including: a first dielectric material layer, a semiconductor material layer and a second dielectric material layer, the second dielectric material layer having horizontally oriented conductive lines formed therein in a horizontal plane of the plurality of multidirectional conductive lines; The second dielectric material layer having the plurality of horizontally oriented conductive lines has a first portion extending in a first horizontal direction and a second portion extending in a second horizontal direction at an angle to the first horizontal direction, wherein the second portions of the plurality of multidirectional conductive lines are laterally spaced apart from each other to allow vertical interconnects to be attached to the second portions. A removal process is performed in repeated vertical iterations in a region containing at least one segment of the second portion of the conductive wire to form a stepped contact structure, including: The first portion of each layer in the first group of layers in the plurality of layers is selectively removed by removing the first portion of each layer in the first group of layers between the reference line and the first distance from the reference line; Selectively removing a portion of each layer in the second group of layers from the plurality of layers by removing a portion of each layer in the second group of layers between the reference line and a second distance backward from the reference line; and The second portion of each layer in the first group of layers is selectively removed by removing the second portion of each layer in the first group of layers between the reference line and a third distance backward from the reference line, wherein the third distance is greater than the second distance.

15. The method of claim 14, wherein the magnitude of the first distance is equal to the second distance.

16. The method of claim 14, further comprising the plurality of multidirectional conductive lines located in an interconnect region, the interconnect region having a first portion formed in an array region and a second portion formed in a conductive line contact region spaced apart from the array region.

17. A memory device having a vertically stacked array of memory cells, the vertically stacked array of memory cells having a plurality of multidirectional conductive lines, the memory device comprising: Vertical stacking of layers formed by repeated iterations of grouped layers. The group of layers includes: a first dielectric material layer, a semiconductor material layer, and a second dielectric material layer, the second dielectric material layer having horizontally oriented conductive lines formed therein in a horizontal plane; and The vertical stack of layers has horizontally oriented conductive lines formed therein of the plurality of multidirectional conductive lines, each of the horizontally oriented conductive lines having a first portion extending in a first horizontal direction and a second portion extending in a second horizontal direction at an angle to the first horizontal direction, wherein the second portions are laterally spaced to allow vertical interconnects to be attached to the second portions.

18. The memory device of claim 17, wherein one or more of the horizontally oriented conductive lines of the plurality of multidirectional conductive lines are horizontal digital lines.

19. The memory device of claim 17, further comprising a vertical body contact formed to directly electrically contact one or more horizontally oriented access devices, each of said one or more horizontally oriented access devices being coupled to a memory node.

20. The memory device of claim 17, wherein one or more of the horizontally oriented conductive lines of the plurality of multidirectional conductive lines are word lines.

21. The memory device of claim 17, wherein the vertically stacked array of memory cells is electrically coupled in an open digital line architecture.

22. The memory device of claim 17, wherein the vertically stacked array of memory cells is electrically coupled in a folded digital line architecture.

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