Successive approximation register (SAR) analog-to-digital converter (ADC) with noise shaping characteristics

Abstract

Certain aspects of the present disclosure provide a successive approximation register (SAR) analog-to-digital converter (ADC) implemented with a digital filter for noise shaping. For example, certain aspects provide a circuit for analog-to-digital conversion having a first digital-to-analog converter (DAC) having an output coupled to a sampling node, a comparator having an input coupled to the sampling node, SAR logic having an input coupled to an output of the comparator and at least one output coupled to an input of the first DAC, a quantizer configured to generate a first digital signal representative of a voltage at the sampling node, a digital filter configured to apply a filter to the first digital signal, and a second DAC configured to generate an analog signal representative of the filtered first digital signal and provide the analog signal to the sampling node.

Description

[0001] Cross-references to related applications

[0002] This application claims the rights and priorities of pending U.S. non-provisional application No. 17 / 062,193, filed October 2, 2020, pursuant to 35 USC §119, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Some aspects of this disclosure generally relate to electronic circuits, and more specifically to a successive approximation register (SAR) analog-to-digital converter (ADC). Background Technology

[0004] Many electronic devices include one or more analog-to-digital converters (ADCs) for converting analog signals into digital signals for further processing in the digital domain. Several types of ADCs are available, each with its own advantages and disadvantages. For example, successive approximation register (SAR) ADCs offer an area- and power-efficient architecture for low- to medium-precision analog-to-digital conversion applications. SAR ADCs use comparators and logic to approximate the digital value corresponding to the analog input. Another type of ADC is called a flash ADC, which offers much faster conversion speeds, but at the cost of exponentially increased power consumption and area requirements. Summary of the Invention

[0005] Some aspects of this disclosure generally relate to a successive approximation register (SAR) analog-to-digital converter (ADC) implemented using a digital filter for noise shaping.

[0006] Some aspects provide a circuit for analog-to-digital conversion. This circuit typically includes: a first digital-to-analog converter (DAC) having an output coupled to a sampling node; a comparator having an input coupled to the sampling node; successive approximation register (SAR) logic having an input coupled to the output of the comparator and at least one output coupled to the input of the first DAC; a quantizer configured to generate a first digital signal representing the voltage at the sampling node; a digital filter configured to apply the filter to the first digital signal; and a second DAC configured to generate an analog signal representing the filtered first digital signal and provide the analog signal to the sampling node.

[0007] Some aspects provide a method for analog-to-digital conversion. This method typically includes: comparing a sampled input voltage at a sampling node with a reference voltage via a comparator; controlling a first DAC having an output coupled to the sampling node based on the comparison via SAR logic to generate a first digital signal; generating a second digital signal representing the remaining voltage at the sampling node after the first digital signal is generated; filtering the second digital signal; and controlling a second DAC having an output coupled to the sampling node based on the filtered second digital signal.

[0008] Some aspects provide an apparatus for analog-to-digital conversion. The apparatus typically includes: means for comparing a sampled input voltage at a sampling node with a reference voltage via a comparator; means for controlling a first DAC having an output coupled to the sampling node based on the comparison via SAR logic to generate a first digital signal; means for generating a second digital signal representing the remaining voltage at the sampling node after the first digital signal is generated; means for filtering the second digital signal; and means for controlling a second DAC having an output coupled to the sampling node based on the filtered second digital signal. Attached Figure Description

[0009] To gain a more detailed understanding of the features described above, reference can be made to the various aspects briefly outlined above, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings illustrate only certain typical aspects of this disclosure and should therefore not be considered as limiting the scope of this disclosure, as other equally valid aspects may be acknowledged in the specification.

[0010] Figure 1 This is a block diagram illustrating a successive approximation register (SAR) analog-to-digital converter (ADC) implemented using residual error processing circuitry according to certain aspects of this disclosure.

[0011] Figure 2 This is a timing diagram illustrating example stages associated with a SAR ADC according to certain aspects of this disclosure.

[0012] Figure 3 The illustration shows a SAR ADC implemented using a capacitor array according to certain aspects of this disclosure for converting residual voltage into a digital signal.

[0013] Figure 4 The illustration shows a SAR DAC implemented using an oscillator according to certain aspects of this disclosure.

[0014] Figure 5 The illustration shows a SAR ADC implemented using a time-to-digital converter (TDC) according to certain aspects of this disclosure.

[0015] Figure 6 The illustration shows a SAR DAC implemented using a unit capacitor array according to certain aspects of this disclosure.

[0016] Figure 7 This is a flowchart of an example operation for analog-to-digital conversion based on certain aspects of this disclosure. Detailed Implementation

[0017] Some aspects of this disclosure generally relate to a successive approximation register (SAR) analog-to-digital converter (ADC) implemented using noise shaping.

[0018] Various aspects of this disclosure are described more fully below with reference to the accompanying drawings. However, this disclosure may be implemented in many different forms and should not be construed as limited to any particular structure or function presented throughout this disclosure. Rather, these aspects are provided so that this disclosure will be thorough and complete and will fully communicate the scope of this disclosure to those skilled in the art. Based on the teachings herein, those skilled in the art will understand that the scope of this disclosure is intended to cover any aspect of the disclosure herein, whether implemented independently or in combination with any other aspect of this disclosure. For example, any number of aspects set forth herein may be used to implement an apparatus or practice method. Furthermore, the scope of this disclosure is intended to cover an apparatus or method that is practiced using a structure, function, or structure and functionality other than or different from the aspects of the disclosure set forth herein. It should be understood that any aspect of the disclosure herein may be implemented by one or more elements of the claims.

[0019] The term “exemplary” is used in this document to mean “serving as an example, instance, or illustration.” Any aspect described as “exemplary” in this document is not necessarily to be construed as being more preferred or advantageous than other aspects.

[0020] As used herein, the term "connected with" in various tenses of the verb "connect" can refer to element A being directly connected to element B, or other elements being connected between element A and element B (i.e., element A and element B being indirectly connected). In the case of electrical components, the term "connected with" may also be used herein to refer to the electrical connection of element A and B (and any components electrically connected therebetween) using wires, traces, or other conductive materials.

[0021] Successive approximation register (SAR) analog-to-digital converters (ADCs) are commonly used in a variety of applications due to their relatively low power and area consumption resulting from the simple and efficient binary search nature of SAR ADCs. Furthermore, SAR ADCs can be implemented using switching circuitry devices that are well-suited to modern complementary metal-oxide-semiconductor (CMOS) technology.

[0022] A SAR ADC can use a capacitor array as a digital-to-analog converter (DAC), a comparator for comparing the voltage at the DAC's output with a reference voltage, and shift register logic for searching for a target voltage value at the comparator's input. Essentially, at the end of the conversion (or binary search) phase, quantization noise may remain at the capacitor array; this quantization noise is often referred to as residual error or residual voltage. In some aspects of this disclosure, residual error can also be addressed to increase the resolution associated with the SAR ADC.

[0023] One way to handle residual errors is to add subsequent stages to resolve them (e.g., convert to the digital domain). However, this technique implements a sub-ranging ADC architecture, which can have issues regarding gain alignment between the first and subsequent stages. Another approach is to have memory for storing residual information, such as memory capacitors or integrator capacitors, which can be used to implement a noise-shaping SAR ADC. However, this technique can be implemented in the analog domain, thus adversely affecting noise shaping efficiency. Certain aspects of this disclosure relate to a SAR ADC implemented within a digital filter for noise shaping.

[0024] Figure 1 This is a block diagram illustrating a SAR ADC 100 implemented according to certain aspects of the present disclosure using a residual error processing circuit arrangement. As illustrated, the SAR ADC 100 includes a capacitor array 102 (C... DACThe ADC implements a DAC (also referred to as a "DAC capacitor array"), a comparator 104 for determining whether the voltage at sampling node 106 is less than or greater than a reference voltage (such as the common-mode voltage (Vcm) in this example), and SAR logic 108 (e.g., shift register logic) for finding a target voltage value at the input of the comparator. Based on feedback from the output of comparator 104, the SAR logic successively determines each of the M bits of the digital signal to be provided to the output of the ADC 180, where M is an integer greater than 1. The SAR logic 108 can be coupled to the control input of the capacitor array 102 and can selectively couple each capacitor element of the capacitor array 102 to a positive reference voltage (Vrefp) or a negative reference voltage (Vrefn) to set the voltage at sampling node 106 during the successive approximation phase until all M bits have been resolved (e.g., determined). For example, the SAR logic can generate a digital signal (e.g., with M+1 bits) to selectively couple the capacitor elements of the capacitor array 102 to Vrefp and Vrefn.

[0025] Figure 2 This is a timing diagram illustrating an example phase associated with the SAR ADC 100 according to certain aspects of this disclosure. As illustrated, during sampling phase 202, switch 110 can be closed to sample the input voltage Vin at sampling node 106. After sampling phase 202, M bits are resolved during successive approximation phase 204. Once the M bits are resolved, a residual error voltage can remain at sampling node 106.

[0026] like Figure 1 As illustrated, a K-bit quantizer 112 can be used to convert the residual error voltage into a K-bit digital signal during the K-bit quantization phase 206. The K-bit digital signal (also referred to as the K least significant bits (LSBs)) can be provided to a digital filter 114 for noise shaping. For example, the digital filter 114 can apply a transfer function H(z) 250. In some aspects, H(z) can be a delay function. After the K-bit quantization phase 206, a delay phase 208 (labeled "IDLE") can occur, followed by another sampling phase 210 and another successive approximation phase 212, to convert the voltage sampled at sampling node 106 during the subsequent sampling phase 210 into another M-bit digital signal. After the delay associated with the transfer function H(z), a feedback DAC capacitor array (C... FBDAC )116 converts the K-bit digital signal generated during the K-bit quantization stage 206 into an analog signal and provides the analog signal to the sampling node 106, so that the successive approximation stage 212 takes into account the residual error voltage.

[0027] In other words, the K-bit digital signal can be modulated by the digital filter 114 to provide a noise shaping function. For example, the digital output (Dout) of the SAR ADC 100 (e.g., at output 180) can be represented by Vin + (1 - H(z)) × Kg × Qn, where Kg is the gain coefficient of the noise shaping function and Qn is the quantization noise associated with the generation of the M bits. In some aspects, the digital filter 114 can be implemented as a finite impulse response (FIR) filter. In some aspects, H(z) can be expressed by various z-domain expressions. -1 2*z -1 -z -2 3*z -1 +3*z -2 -z -3 In one z-domain expression or any delay order representation in the digital domain, z is a composite variable of the z-transform function. In some aspects, noise shaping can be implemented in a digital filter (such as digital filter 114). In other aspects, it can be achieved by changing the feedback capacitor element (e.g., C). FBDAC The bit weights of the capacitor array 116 can be used to implement noise shaping. For example, the capacitance of the capacitor elements of the capacitor array 116 can be set to effectively implement a digital filter for noise shaping.

[0028] Figure 3 The figure illustrates the use of capacitor array 304 (C) according to certain aspects of this disclosure. LSB The SAR ADC 300 is implemented to convert residual voltage into a digital signal. In other words, a quantizer 112 can be implemented using a capacitor array 304, which can be controlled by SAR logic 108 to generate a digital representation (e.g., a K-bit digital signal) of the residual voltage at node 330. As illustrated, the SAR ADC 300 may include a capacitor array 102 (in... Figure 3 The middle is marked as "C" MSB The SAR logic 108 can selectively couple each capacitor element in the capacitor array 102 to Vrefp and Vrefn to resolve the M bits of the digital output at output 180.

[0029] As described in this document, once the M bits are resolved, the remaining voltage at sampling node 106 can be the residual voltage. SAR logic 108 can then control capacitor array 304 to resolve the K bits of the digital signal at node 330 (e.g., convert the residual voltage into a digital signal).

[0030] As illustrated, capacitor array 304 can be connected via bridging capacitor element 320 (C B And coupled to sampling node 106. Compared with capacitor array 304, C B It can have a small capacitor so that the capacitor array 304 does not affect the voltage at sampling node 106 when the M bits of the digital signal are being parsed. Furthermore, as illustrated, capacitor element 322 (C P It can be coupled between the capacitor array 304 and the reference potential node (e.g., with Vcm).

[0031] As described, once the M bits are resolved, SAR logic 108 can selectively couple the capacitive elements of capacitor array 304 to Vrefp and Vrefn to resolve the K bits. Once the K bits are resolved, they are provided to digital filter 114, and capacitor array 116 can be controlled to convert the K bits into an analog signal at sampling node 106 before subsequent successive approximation stages (e.g., successive approximation stage 212), as described herein relative to... Figure 2 As described, the successive approximation stage 212 can be followed by another K-bit quantization stage 214 and another delay stage 216. As illustrated, the capacitor array 116 can be coupled to the sampling node 106 via bridging capacitor element 324. Furthermore, as illustrated, capacitor element 326 can be coupled between the capacitor array 116 and a reference potential node (e.g., using Vcm).

[0032] Figure 4 The illustration shows a SAR ADC 400 implemented using an oscillator 404 according to certain aspects of this disclosure. As illustrated, comparator 104 may include a transconductance (gm) amplifier 402 that converts the residual voltage at sampling node 106 into a current to be supplied to oscillator 404. For example, oscillator 404 may be a current-controlled oscillator (CCO), wherein the frequency of the output signal of oscillator 404 is controlled by the current from transconductance (gm) amplifier 402. Thus, the frequency of the output signal of oscillator 404 represents the residual voltage at sampling node 106. As illustrated, a K-bit counter or phase quantizer 407 may be used to generate a K-bit digital signal representing the frequency of the oscillator output signal. As described herein, the K-bit digital signal may be provided to a digital filter 114 for noise shaping. In other words, transconductance amplifier 402, oscillator 404, and K-bit counter or phase quantizer 407 effectively implement a quantizer (e.g., corresponding to quantizer 112) for converting the residual voltage to the digital domain.

[0033] As described herein, by configuring comparator 104 as a gm unit (e.g., gm amplifier 402), the residual voltage can be converted into a residual current to control the frequency of the CCO. In some aspects, oscillator 404 can be implemented as a voltage-controlled oscillator (VCO) and can be directly controlled using the residual voltage (or an amplified version thereof) at sampling node 106. The signal swing associated with the residual voltage can be small enough to allow the residual voltage to be linearly converted to the time domain by oscillator 406. In some aspects, comparator 104 can include latch 408 between the output of gm amplifier 402 and SAR logic 108.

[0034] Figure 5 The illustration shows a SAR ADC 500 implemented using a time-to-digital converter (TDC) according to certain aspects of this disclosure. For example, the SAR ADC 500 may include logic 502 (e.g., an AND gate) having an input coupled to the output of comparator 104. Another input of logic 502 may be controlled via a TDC_start signal, or the TDC_start signal may be provided to a K-bit TDC circuit 504. As described herein, after M bits are resolved, residual voltage may remain at sampling node 106. As illustrated in Figure 520, the TDC_start signal may transition from logic low to logic high, thereby activating the counter of the TDC circuit 504. Logic 502 may be used to control a current source 530 configured to sink current (labeled "Idischarge") from sampling node 106, thereby effectively reducing the voltage at sampling node 106. For example, when the TDC_start signal transitions to logic high, current source 530 can begin to draw current from sampling node 106, causing the voltage at sampling node 106 to decrease. Once the voltage at sampling node 106 reaches zero volts (e.g., Vcm), the output voltage of comparator 104 (cmp_out signal) transitions to logic high. TDC 504 detects the time difference between the rising edge of the TDC_start signal and the rising edge of the cmp_out signal and provides a digital signal representing this time difference. Therefore, as described herein, the digital signal from TDC circuit 504 represents the residual voltage and can be provided to digital filter 114 for noise shaping. Thus, current source 530, logic 502, and TDC circuit 504 effectively implement a quantizer (e.g., corresponding to quantizer 112) for converting the residual voltage to the digital domain.

[0035] Figure 6 The figure illustrates the use of a unit capacitor array 603 (C) according to certain aspects of this disclosure. U,ArrayThe SAR ADC 600 is implemented as shown. As illustrated, the SAR ADC 600 may include a level-shifting circuit 602 (e.g., implemented using one or more capacitive elements), which may be controlled by a level-shifting bit of logic 604 to increase the voltage at sampling node 106. After M bits of the digital output signal of the SAR ADC 600 are resolved, the voltage at sampling node 106 can be positive or negative. For example, as illustrated in Figure 680, the voltage at sampling node 106 (labeled "Vx") can be negative during time period 682. Therefore, as illustrated, after M bits are resolved, the voltage at sampling node 106 can be increased via the level-shifting circuit 602 to make the voltage at sampling node 106 positive.

[0036] The TDC_start signal can then transition to logic high, at which point the TDC circuit 504 can begin incrementing the K-bit digital signal at its output. This K-bit digital signal can be used to control the unit capacitor array 603. For example, the capacitive elements of the capacitor array 603 can be selectively coupled to Vrefp and Vrefn, thereby progressively decreasing the voltage at sampling node 106 in LSB-sized units (e.g., step units associated with K bits). As illustrated, once the voltage at sampling node 106 reaches zero volts (e.g., Vcm), the cmp_out signal transitions to logic high. As described herein, when the cmp_out signal transitions to logic high, the K-bit digital signal at the output of the TDC circuit 504 can represent the residual voltage and can be provided to the digital filter 114 for noise shaping.

[0037] In other words, a TDC-based quantizer can be used to parse a K-bit digital signal. The current source 530 of the SAR ADC 500 is replaced with a unit array DAC (e.g., unit capacitor array 603) to implement the digital slope while discharging the voltage at sampling node 106. After M bits are parsed, the voltage at sampling node 106 is first level-shifted via level shift circuit 602, and the unit capacitor array 603 begins to progressively decrease the voltage at sampling node 106 based on the digital signal generated by the TDC circuit 504. As described herein, comparator 104 is configured as a continuous comparator to monitor zero-volt crossovers of the voltage at sampling node 106. The TDC circuit 504 is quantizing the steps to generate a K-bit digital signal.

[0038] Certain aspects of this disclosure provide techniques for quantizing the residual voltage after an M-bit analog-to-digital conversion stage. K-bit digital information representing the residual voltage can be provided to a digital filter used for noise shaping, which can be any type of filter, such as a finite impulse response (FIR) or infinite impulse response (IIR) filter. The modulated K-bit digital signal can be applied to a feedback DAC (e.g., capacitor array 116) to achieve quantization noise cancellation in subsequent conversion stages. In some aspects, any gain error between the M-bit and K-bit conversions can have little impact on performance because the K-bit digital signal is used only for noise shaping. Therefore, the gain error can affect only the noise shaping applied via digital filter 114 without harming the performance of the SAR ADC. Digital filter 114 can be managed to achieve N-order noise shaping to effectively improve the signal-to-noise ratio associated with the SAR ADC.

[0039] Figure 7 This is a flowchart of an example operation 700 for analog-to-digital conversion according to certain aspects of this disclosure. Operation 700 can be performed by a SAR ADC (such as SAR ADC 100, 300, 400, 500 and 600).

[0040] Operation 700 can begin at block 702, where the SAR ADC compares a sampled input voltage at a sampling node (e.g., sampling node 106) with a reference voltage (e.g., via comparator 104). At block 704, the SAR ADC can control (e.g., via SAR logic 108) a first DAC (e.g., capacitor array 102) having an output coupled to the sampling node based on the comparison to generate a first digital signal (e.g., an M-bit digital signal), and at block 706, after the first digital signal is generated, a second digital signal (e.g., a K-bit digital signal) representing the remaining voltage (e.g., residual voltage) at the sampling node is generated. At block 708, the SAR ADC can filter the second digital signal (e.g., via digital filter 114), and at block 710, a second DAC (e.g., capacitor array 116) having an output coupled to the sampling node is controlled based on the filtered second digital signal.

[0041] In some aspects, generating a second digital signal at block 706 may include generating an oscillation signal based on the voltage at the sampling node (e.g., via oscillator 406), and the second digital signal is generated based on the oscillation signal (e.g., via counter or phase quantizer 407). In some cases, the SAR ADC may also convert the remaining voltage at the sampling node (e.g., via transconductance amplifier 402) into current, and the oscillation signal is generated based on the current.

[0042] In some aspects, generating the second digital signal may include drawing current from the sampling node (e.g., via current source 530) to begin reducing the remaining voltage at the sampling node, and determining (e.g., via TDC circuit 504) a time period from the start of the voltage reduction to when the voltage at the sampling node reaches a reference voltage, based on which the second digital signal is generated.

[0043] In some aspects, generating the second digital signal may include reducing (e.g., via capacitor array 116) the voltage at the sampling node and determining (e.g., via TDC circuit 504) a time period from the start of the reduction in voltage at the sampling node to the point when the voltage at the sampling node reaches a reference voltage, based on which the second digital signal is generated.

[0044] The various operations described above can be performed by any suitable component capable of performing the corresponding function. This component can include various hardware and / or (one or more) modules, including but not limited to circuits, application-specific integrated circuits (ASICs), or processors. Typically, in the presence of operations illustrated in the figures, those operations can have corresponding paired component-plus-function components with similar numbering. For example, a component for comparison can include a comparator, such as comparator 104. A component for control can include SAR logic, such as SAR logic 108. A component for generation can include a quantizer, such as quantizer 112. A component for filtering can include a digital filter, such as digital filter 114. A component for control can include a capacitor array, such as capacitor array 116.

[0045] As used herein, the term "determine" encompasses a variety of actions. For example, "determine" can include calculating, computing, processing, deriving, investigating, searching (e.g., looking in a table, database, or other data structure), ascertaining, etc. Furthermore, "determine" can include receiving (e.g., receiving information), accessing (e.g., accessing data in memory), etc. Additionally, "determine" can include parsing, selecting, choosing, creating, etc.

[0046] As used herein, the phrase “at least one of…” in a list of items refers to any combination of these items, including a single member. For example, “at least one of a, b, or c” is intended to cover: a, b, c, ab, ac, bc, and abc, as well as any combination with multiple identical elements (e.g., aa, aaa, aab, aac, abb, acc, bb, bbb, bbc, cc, and ccc, or any other order of a, b, and c).

[0047] The various illustrative logic blocks, modules, and circuits described herein can be implemented or performed using general-purpose processors, digital signal processors (DSPs), ASICs, field-programmable gate arrays (FPGAs) or other programmable logic devices (PLDs), discrete gate or transistor logic, discrete hardware components, or any combination thereof designed to perform the functions described herein. The general-purpose processor may be a microprocessor, but alternatively, the processor may be any commercially available processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a DSP and a microprocessor, multiple microprocessors, one or more microprocessors together with a DSP core, or any other such configuration.

[0048] The methods disclosed herein include one or more steps or actions for implementing the described methods. Method steps and / or actions may be interchanged without departing from the scope of the claims. In other words, unless a specific order of steps or actions is specified, the order and / or use of particular steps and / or actions may be modified without departing from the scope of the claims.

[0049] It should be understood that the claims are not limited to the precise configuration and components described above. Various modifications, alterations, and variations may be made to the arrangement, operation, and details of the above-described methods and apparatus without departing from the scope of the claims.

Claims

1. A circuit for analog-to-digital conversion, comprising: a first digital-to-analog converter (DAC) having an output coupled to a sampling node; a comparator having an input coupled to the sampling node; successive approximation register (SAR) logic having an input coupled to an output of the comparator and at least one output coupled to an input of the first DAC; a quantizer configured to generate a first digital signal representative of a voltage at the sampling node, wherein the quantizer comprises: an oscillator having a control input coupled to the sampling node; and a counter or phase quantizer configured to generate the first digital signal based on an output signal of the oscillator; a digital filter configured to filter the first digital signal; and a second DAC configured to generate an analog signal representative of the filtered first digital signal and to provide the analog signal to the sampling node.

2. The circuit of claim 1, wherein the first DAC, the comparator, and the SAR logic are configured to generate a second digital signal representative of a sampled voltage at the sampling node, and wherein the first digital signal is representative of a residual voltage at the sampling node after generation of the second digital signal.

3. The circuit of claim 1, wherein the digital filter and the second DAC are implemented using a capacitor array.

4. The circuit of claim 1, wherein the quantizer is coupled between the sampling node and the digital filter.

5. The circuit of claim 1, wherein the quantizer comprises a capacitor array coupled to the sampling node, a control input of the capacitor array being coupled to the at least one output of the SAR logic.

6. The circuit of claim 1, further comprising a transconductance amplifier having an input coupled to the sampling node, wherein the oscillator comprises a current-controlled oscillator, a control input of the current-controlled oscillator being coupled to an output of the transconductance amplifier.

7. The circuit of claim 1, wherein the first DAC comprises a DAC capacitor array, and wherein the second DAC comprises a feedback (FB) DAC capacitor array.

8. The circuit of claim 1, wherein the SAR logic is configured to generate the first digital signal.

9. A circuit for analog-to-digital conversion, comprising: a first digital-to-analog converter (DAC) having an output coupled to a sampling node; a comparator having an input coupled to the sampling node; successive approximation register (SAR) logic having an input coupled to an output of the comparator and at least one output coupled to an input of the first DAC; a quantizer configured to generate a first digital signal representative of a voltage at the sampling node, wherein the quantizer comprises: a current source configured to sink current from the sampling node to begin reducing the voltage at the sampling node; and a digital filter configured to filter the first digital signal; and a second DAC configured to generate an analog signal representative of the filtered first digital signal and to provide the analog signal to the sampling node. a time-to-digital converter (TDC) configured to determine a time period from when the reduction of the voltage at the sampling node begins and when the voltage at the sampling node reaches a reference voltage, the TDC further configured to generate the first digital signal based on the time period; a digital filter configured to filter the first digital signal; and a second DAC configured to generate an analog signal representing the filtered first digital signal and to provide the analog signal to the sampling node.

10. The circuit of claim 9, wherein the quantizer further comprises logic configured to begin the reduction of the voltage at the sampling node based on a TDC start signal.

11. A circuit for analog-to-digital conversion, comprising: a first digital-to-analog converter (DAC) having an output coupled to a sampling node; a comparator having an input coupled to the sampling node; successive approximation register (SAR) logic having an input coupled to an output of the comparator and at least one output coupled to an input of the first DAC; a quantizer configured to generate a first digital signal representing a voltage at the sampling node, wherein the quantizer comprises: a capacitor array configured to reduce the voltage at the sampling node; and a time-to-digital converter (TDC) configured to determine a time period from when the reduction of the voltage at the sampling node begins and when the voltage at the sampling node reaches a reference voltage, the TDC further configured to generate the first digital signal based on the time period; a digital filter configured to filter the first digital signal; and a second DAC configured to generate an analog signal representing the filtered first digital signal and to provide the analog signal to the sampling node.

12. The circuit of claim 11, wherein the TDC is configured to control the capacitor array to reduce the voltage at the sampling node via the first digital signal.

13. The circuit of claim 11, wherein the quantizer further comprises a level shifting circuit configured to increase the voltage at the sampling node prior to the capacitor array reducing the voltage at the sampling node.

14. The circuit of claim 13, wherein the level shifting circuit comprises one or more capacitive elements coupled to the sampling node.

15. The circuit of claim 11, wherein the first DAC comprises a DAC capacitor array, and wherein the second DAC comprises a feedback (FB) DAC capacitor array.

16. The circuit of claim 11, wherein the SAR logic is configured to generate the first digital signal.

17. A method for analog-to-digital conversion, comprising: comparing, via a comparator, a sampled input voltage at a sampling node to a reference voltage; controlling, via successive approximation register (SAR) logic, a first DAC having an output coupled to the sampling node based on the comparison to generate a first digital signal; generating a second digital signal representing a voltage remaining at the sampling node after the first digital signal is generated, wherein generating the second digital signal includes generating, via an oscillator, an oscillating signal based on the voltage at the sampling node, the second digital signal being generated based on the oscillating signal via a counter or a phase quantizer; filtering the second digital signal; and controlling a second DAC having an output coupled to the sampling node based on the filtered second digital signal.

18. The method of claim 17, further comprising: converting, via a transconductance amplifier, a voltage remaining at the sampling node into a current, the oscillating signal being generated based on the current.

19. A method for analog-to-digital conversion, comprising: comparing, via a comparator, a sampled input voltage at a sampling node to a reference voltage; controlling, via successive approximation register (SAR) logic, a first DAC having an output coupled to the sampling node based on the comparison to generate a first digital signal; generating a second digital signal representing a voltage remaining at the sampling node after the first digital signal is generated, wherein generating the second digital signal includes: absorbing, via a current source, current from the sampling node to begin reducing the voltage remaining at the sampling node; and determining, via a time-to-digital converter (TDC), a time period from when the reduction of the voltage begins and when the voltage at the sampling node reaches the reference voltage, the second digital signal being generated based on the time period; filtering the second digital signal; and controlling a second DAC having an output coupled to the sampling node based on the filtered second digital signal.

20. A method for analog-to-digital conversion, comprising: comparing, via a comparator, a sampled input voltage at a sampling node to a reference voltage; controlling, via successive approximation register (SAR) logic, a first DAC having an output coupled to the sampling node based on the comparison to generate a first digital signal; generating a second digital signal representing a voltage remaining at the sampling node after the first digital signal is generated, wherein generating the second digital signal includes: reducing, via a capacitor array, the voltage at the sampling node; and determining, via a TDC, a time period from when the reduction of the voltage at the sampling node begins and when the voltage at the sampling node reaches the reference voltage, the second digital signal being generated based on the time period; filtering the second digital signal; and controlling a second DAC having an output coupled to the sampling node based on the filtered second digital signal.

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