Solid-state imaging elements and imaging devices

Abstract

A solid-state imaging element includes a comparator for each column, wherein the comparator's responsiveness is improved. An input transistor outputs a potential from its drain that ranges from one of a pair of output potentials to the other, depending on whether an input potential input to the source and a predetermined reference potential input to the gate are approximately matched. A first current source provides a uniform current. A capacitor is inserted between the source of the input transistor and the first current source. A cutoff switch disconnects the drain of the input transistor from the connection node for the capacitor and the first current source during a predetermined period for initializing a connection node to the lower of the pair of output potentials, and connects the connection node and the drain of the input transistor outside the predetermined period.

Description

Technical Field

[0001] This technology relates to solid-state imaging elements. Specifically, this technology relates to solid-state imaging elements and imaging devices equipped with comparators and counters. Background Technology

[0002] In the prior art, single-slope analog-to-digital converters (ADCs) are commonly used for analog-to-digital (AD) conversion in solid-state imaging elements due to their simple structure. A single-slope ADC typically includes a comparator and a counter that performs counting based on the comparison result of the comparator. A solid-state imaging element has been proposed in which, for example, a p-channel metal-oxide-semiconductor (pMOS) transistor, a current source, and logic gates (such as inverters) are arranged in the comparator (see, for example, Patent Document 1). The pMOS transistor compares the pixel signal from the pixel circuit with a reference signal and outputs the comparison result from the drain via the inverter. The comparison result is initialized to a low level by inputting a high-level reference voltage before the counter begins counting.

[0003] Reference List

[0004] Patent documents

[0005] Patent Document 1: U.S. Patent Application Publication No. 2018 / 0103222 Summary of the Invention

[0006] The problem to be solved by the present invention

[0007] In the aforementioned solid-state imaging element, the current of the pixel circuit is shared by the comparator, thus reducing power consumption compared to a configuration where the current source is also located in the comparator separate from the pixel circuit. However, in the aforementioned solid-state imaging element, it is difficult to increase the speed at which the output transitions from a high level to a low level during initialization (in other words, the comparator's responsiveness is improved). When the value of the reference voltage is sufficiently increased to improve responsiveness, the leakage current of the pMOS transistor in the cutoff state decreases, but the power consumption increases.

[0008] This technique was developed in light of this situation, and its purpose is to improve the responsiveness of comparators in solid-state imaging elements that have comparators set for each column.

[0009] Solution to the problem

[0010] This technology has been developed to address the aforementioned problems, and according to a first aspect of this technology, a solid-state imaging element is provided, comprising: an input transistor configured to output a potential from its drain in a range from one to the other of a pair of output potentials based on whether an input potential input to the source and a predetermined reference potential input to the gate are substantially aligned with each other; a first current source configured to supply a constant current; a capacitor inserted between the source of the input transistor and the first current source; and a first cut-off switch configured to disconnect the drain of the input transistor from the connection node during a predetermined period for initializing a connection node between the capacitor and the first current source to the lower of the pair of output potentials, and to connect the connection node to the drain of the input transistor outside the predetermined period. This results in improved responsiveness.

[0011] Furthermore, in the first aspect, the first cut-off switch may include an N-type transistor and a P-type transistor connected in parallel between the drain of the input transistor and the first current source. Therefore, comparison operation can be performed regardless of the cut-off switch.

[0012] Furthermore, in the first aspect, the first shut-off switch may include an N-type transistor. This results in a reduction in the number of transistors.

[0013] Furthermore, in the first aspect, a first output transistor may also be provided, configured to output a potential from its drain in a range from a predetermined potential lower than the input potential to the input potential, based on whether the difference between the input potential at the input to the source and the potential at the connection node at the input to the gate exceeds a predetermined threshold voltage; and an output-side short-circuit switch configured to short-circuit the source and drain of the first output transistor for a predetermined period of time. This results in improved responsiveness.

[0014] Furthermore, in the first aspect, an auto-zero transistor may also be provided, configured to connect the gate and drain of the input transistor during an auto-zero period prior to the predetermined period, and the output-side short-circuit switch may short-circuit the source and drain of the first output transistor during both the auto-zero period and the predetermined period. This results in the suppression of oscillations during the auto-zero period.

[0015] Furthermore, in the first aspect, the output-side short-circuit switch may include an N-type transistor and a P-type transistor connected in parallel between the source and drain of the first output transistor. This results in the source and drain of the first output transistor being short-circuited when the level of the comparison result is approximately the midpoint of the power supply potential.

[0016] Alternatively, in the first aspect described above, the output-side short-circuit switch may include an N-type transistor. This results in a reduction in the number of transistors.

[0017] Alternatively, in the first aspect described above, the output-side short-circuit switch may include a P-type transistor. This results in a reduction in the number of transistors.

[0018] Furthermore, in the first aspect, a second output transistor may also be provided, configured to output a voltage from its drain that falls within the range from the predetermined potential to the input potential, based on whether the difference between the input potential (input to the source) and the drain of the first output transistor (input to the gate) exceeds a predetermined threshold voltage. Therefore, the comparator gain is increased, and thus the linearity is improved.

[0019] Furthermore, in the first aspect, an input-side short-circuit switch can also be provided, configured to short-circuit the drain and source of the input transistor for a predetermined period of time. This results in the suppression of performance degradation.

[0020] Furthermore, in the first aspect, a level offset circuit may also be provided, configured to output an output signal having a pair of offset potentials having a potential difference greater than a predetermined potential and an input potential based on the potential of the drain of the first output transistor; and a logic gate configured to determine whether the output signal is higher than a predetermined threshold between the pair of offset potentials and output a determination result. This results in increased design freedom.

[0021] Furthermore, in the first aspect, one of the pair of offset potentials can be a power supply potential higher than the input potential, and the other of the pair of offset potentials can be a reference potential lower than a predetermined potential. The level offset circuit can include: an N-type transistor having a gate connected to a vertical signal line connected to the input potential and a source connected to the drain of a first output transistor; a power supply-side precharge transistor configured to initialize the drain potential of the N-type transistor to the power supply potential; a P-type transistor having a gate connected to the drain of the N-type transistor and a drain connected to the logic gate; and a reference-side precharge transistor configured to initialize the drain potential of the P-type transistor to the reference potential. This results in the voltage circuit being extended by four transistors.

[0022] Furthermore, in the first aspect, the following may also be provided: a first output transistor configured to output a potential from its drain in a range from a predetermined potential lower than the input potential to the input potential, based on whether the difference between the input potential at the input to the source and the potential at the connection node at the input to the gate exceeds a predetermined threshold voltage; a second current source configured to supply a constant current; a second cut-off switch configured to disconnect the drain of the first output transistor from the second current source before the reference potential stabilizes, and to connect the drain of the first output transistor to the second current source for a specific period of time from the start of the timing; a clamping transistor, the drain of which is connected to the second current source; and a control switch configured to connect the source of the first output transistor to the source of the clamping transistor before the start of the timing, and to disconnect the source of the first output transistor from the source of the clamping transistor for a specific period of time from the start of the timing. This provides an effect of suppressing backlash.

[0023] Furthermore, in the first aspect, a level offset circuit can also be provided, which is configured to output a pair of offset potentials with a potential difference greater than a predetermined potential and an input potential based on the potential of the connection node between the control switch and the clamping transistor. This results in increased design freedom.

[0024] Furthermore, in the first aspect, an input capacitor switching circuit can also be provided, which is configured to switch the number of input capacitors connected in parallel with the gate of the input transistor. This results in noise reduction.

[0025] Furthermore, according to a second aspect of the present invention, a solid-state imaging element is provided, comprising: an input transistor configured to output a drain potential corresponding to the input potential from its drain when an input potential input to the source and a predetermined reference potential input to the gate are substantially consistent with each other; a first output transistor configured to output a potential from its drain in a range from a predetermined potential to the input potential based on whether the difference between the input potential input to the source and the drain potential input to the gate exceeds a predetermined threshold voltage; and an output-side short-circuit switch configured to short-circuit the source and drain of the first output transistor for a predetermined period of time for initializing the drain of the first output transistor to the input potential. This results in improved responsiveness.

[0026] Furthermore, according to a third aspect of the present invention, a solid-state imaging element is provided, comprising: an input transistor configured to output a predetermined clamping potential from its drain when an input potential input to the source and a predetermined reference potential input to the gate are substantially aligned with each other; and an input-side short-circuit switch configured to short-circuit the source and drain of the input transistor for a predetermined period of time for initializing the drain potential to a high level higher than the clamping potential. This results in improved responsiveness.

[0027] Furthermore, according to a fourth aspect of the present technology, an imaging apparatus is provided, comprising: an input transistor configured to output a potential from its drain in a range from one of a pair of output potentials to the other, based on whether an input potential input to the source and a predetermined reference potential input to the gate are substantially consistent with each other; a current source configured to supply a constant current; a capacitor inserted between the source of the input transistor and the current source; a cut-off switch configured to disconnect the drain of the input transistor from the connection node during a predetermined period for initializing the connection node between the capacitor and the current source to the lower of the pair of output potentials, and to connect the connection node to the drain of the input transistor outside the predetermined period; and a counter configured to count a value over a period of time until the potential of the connection node is reversed. This results in improved responsiveness.

[0028] Furthermore, according to a fifth aspect of the present technology, a solid-state imaging element is provided, comprising: a vertical signal line connected to a pixel; a transistor including a source connected to the vertical signal line and a gate for receiving a signal based on a predetermined reference potential; a current source configured to supply a constant current; a capacitor inserted between the source of the transistor and the current source; and a switch connected to a connection node between the capacitor and the current source and drain of the transistor.

[0029] Furthermore, according to a sixth aspect of the present technology, a solid-state imaging element is provided, comprising: a vertical signal line connected to a pixel; a first transistor including a source connected to the vertical signal line and a gate for receiving a signal based on a predetermined reference potential; a current source configured to supply a constant current; a second transistor including a source connected to the vertical signal line and a gate connected to the current source; and a switch connected to the source and drain of the second transistor. Attached Figure Description

[0030] Figure 1 This is a block diagram illustrating a configuration example of an imaging apparatus according to a first embodiment of the present technology.

[0031] Figure 2 This is a diagram illustrating an example of a stacked structure of a solid-state imaging element according to a first embodiment of the present technology.

[0032] Figure 3 This is a block diagram illustrating a configuration example of a solid-state imaging element according to a first embodiment of the present technology.

[0033] Figure 4 This is a circuit diagram illustrating a configuration example of a pixel circuit according to a first embodiment of the present technology.

[0034] Figure 5 This is a block diagram illustrating a configuration example of a column signal processing unit according to a first embodiment of the present technology.

[0035] Figure 6 This is a circuit diagram illustrating a configuration example of a comparator according to a first embodiment of the present technology.

[0036] Figure 7 This is a circuit diagram illustrating an example configuration of a cut-off switch and an inverter according to a first embodiment of the present technology.

[0037] Figure 8 This is a diagram used to illustrate the improved responsiveness of the first embodiment of the present technology.

[0038] Figure 9 This is a timing diagram illustrating an example of the operation of a solid-state imaging element according to a first embodiment of the present technology.

[0039] Figure 10 This is an example of a timing diagram in the case of inputting a black level during the signal level transition period according to the first embodiment of this technology.

[0040] Figure 11 This is an example of a timing diagram in the case of inputting a white level during the signal level transition period according to the first embodiment of this technology.

[0041] Figure 12 This is a flowchart illustrating an example of the operation of a solid-state imaging element according to a first embodiment of the present technology.

[0042] Figure 13 This is a circuit diagram illustrating a configuration example of a comparator according to a first variation of the first embodiment of the present technology.

[0043] Figure 14 This is a circuit diagram illustrating a configuration example of a comparator according to a second variation of the first embodiment of the present technology.

[0044] Figure 15 This is a circuit diagram illustrating a configuration example of a comparator according to a second embodiment of the present technology.

[0045] Figure 16This is a timing diagram illustrating an example of the operation of a solid-state imaging element according to a second embodiment of the present technology.

[0046] Figure 17 This is an example of a timing diagram for the case where a black level is input during the signal level transition period according to the second embodiment of this technology.

[0047] Figure 18 This is an example of a timing diagram for the case where a white level is input during the signal level transition period according to the second embodiment of this technology.

[0048] Figure 19 This is a circuit diagram illustrating a configuration example of a comparator according to a first variation of the second embodiment of the present technology.

[0049] Figure 20 This is a circuit diagram illustrating a configuration example of a comparator according to a second variation of the second embodiment of the present technology.

[0050] Figure 21 This is a circuit diagram illustrating a configuration example of a comparator according to a third embodiment of the present technology.

[0051] Figure 22 This is a timing diagram illustrating an example of the operation of a solid-state imaging element according to a third embodiment of the present technology.

[0052] Figure 23 This is a circuit diagram illustrating a configuration example of a comparator according to a fourth embodiment of the present technology.

[0053] Figure 24 This is a circuit diagram illustrating a configuration example of a comparator according to a fifth embodiment of the present technology.

[0054] Figure 25 This is a circuit diagram illustrating a configuration example of a comparator according to a sixth embodiment of the present technology.

[0055] Figure 26 This is a circuit diagram illustrating a configuration example of a level offset circuit according to a sixth embodiment of the present technology.

[0056] Figure 27 This is a timing diagram illustrating an example of the operation of a solid-state imaging element according to a sixth embodiment of the present technology.

[0057] Figure 28 This is a circuit diagram illustrating a configuration example of a comparator according to a seventh embodiment of the present technology.

[0058] Figure 29 This is a timing diagram illustrating an example of the operation of a solid-state imaging element according to a seventh embodiment of the present technology.

[0059] Figure 30 This is a circuit diagram illustrating a configuration example of a comparator according to a first variation of the seventh embodiment of the present technology.

[0060] Figure 31 This is a circuit diagram illustrating a configuration example of a comparator according to a second variation of the seventh embodiment of the present technology.

[0061] Figure 32 This is a block diagram illustrating a configuration example of a comparator according to a third variation of the seventh embodiment of the present technology.

[0062] Figure 33 This is a circuit diagram illustrating a configuration example of the comparison circuit of a third variation of the seventh embodiment of the present technology.

[0063] Figure 34 This is a block diagram illustrating a configuration example of a comparator according to a third variation of the seventh embodiment of the present technology.

[0064] Figure 35 This is a timing diagram illustrating an example of the operation of a solid-state imaging element according to a third variation of the seventh embodiment of the present technology.

[0065] Figure 36 This is a circuit diagram showing a construction example of a comparator based on a comparison instance.

[0066] Figure 37 This is a timing diagram illustrating an example of the operation of a solid-state imaging element based on a comparative example.

[0067] Figure 38 This is a circuit diagram illustrating a configuration example of a comparator according to the eighth embodiment of the present technology.

[0068] Figure 39 This is a timing diagram illustrating an example of the operation of a solid-state imaging element according to an eighth embodiment of the present technology.

[0069] Figure 40 This is a circuit diagram illustrating a configuration example of a comparator with an added N-type clamping transistor according to the eighth embodiment of the present technology.

[0070] Figure 41 This is a circuit diagram illustrating a configuration example of a comparator according to a first variation of the eighth embodiment of the present technology.

[0071] Figure 42 This is a timing diagram illustrating an example of the operation of a solid-state imaging element according to a first variation of the eighth embodiment of the present technology.

[0072] Figure 43 This is a circuit diagram illustrating a configuration example of a comparator according to a second variation of the eighth embodiment of the present technology.

[0073] Figure 44 This is a circuit diagram illustrating a configuration example of an input capacitor switching circuit according to a second variation of the eighth embodiment of the present technology.

[0074] Figure 45 This is a block diagram illustrating a schematic configuration example of a vehicle control system.

[0075] Figure 46 This is an explanatory diagram showing an example of the mounting position of the imaging unit. Detailed Implementation

[0076] The following describes the modes of implementing this technology (hereinafter referred to as implementation methods). The descriptions will be given in the following order.

[0077] 1. First Implementation Method (Example of Increasing Response Speed ​​by Cut-off Switch)

[0078] 2. Second Implementation Method (Example of Increasing Response Speed ​​via Short-Circuit Switch)

[0079] 3. Third Implementation Method (Example of increasing response speed by using a cut-off switch and an output-side short-circuit switch)

[0080] 4. Fourth Implementation (Example of increasing response speed by adding a third-stage transistor and using a cutoff switch and an output-side short-circuit switch)

[0081] 5. Fifth Implementation (Example of increasing response speed by adding an input-side short-circuit switch and by using a cut-off switch and an output-side short-circuit switch)

[0082] 6. Sixth Implementation (Example of increasing response speed by setting up a level offset circuit and using a cutoff switch and an output-side short-circuit switch)

[0083] 7. Seventh Implementation (An example corresponding to ramp signals with different waveforms and increasing response speed by using a short-circuit switch)

[0084] 8. Eighth Implementation (Example of suppressing backlash by cutting off switch, clamping transistor and control switch)

[0085] 9. Examples of applications of moving bodies

[0086] <1. First Implementation Method>

[0087] [Imaging device configuration]

[0088] Figure 1This is a block diagram illustrating a configuration example of an imaging apparatus 100 according to a first embodiment of the present technology. The imaging apparatus 100 is a device for capturing image data and includes an optical unit 110, a solid-state imaging element 200, and a digital signal processing (DSP) circuit 120. The imaging apparatus 100 further includes a display unit 130, an operation unit 140, a bus 150, a frame memory 160, a storage unit 170, and a power supply unit 180. As an imaging apparatus 100, consider a camera installed in a smartphone, a vehicle camera, etc.

[0089] Optical unit 110 focuses light from the object and directs the light to solid-state imaging element 200. Solid-state imaging element 200 generates image data through photoelectric conversion. Solid-state imaging element 200 provides the generated image data to DSP circuit 120 via signal line 209.

[0090] The DSP circuit 120 performs predetermined signal processing on the image data. The DSP circuit 120 outputs the processed image data to the frame memory 160, etc., via the bus 150.

[0091] Display unit 130 displays image data. For example, a liquid crystal panel or an organic electroluminescent (EL) panel may be considered as display unit 130. Operation unit 140 generates operation signals based on user input.

[0092] Bus 150 is a common path for the optical unit 110, solid-state imaging element 200, DSP circuit 120, display unit 130, operation unit 140, frame memory 160, storage unit 170 and power supply unit 180 to exchange data with each other.

[0093] Frame memory 160 stores image data. Storage unit 170 stores various data such as image data. Power supply unit 180 supplies power to solid-state imaging element 200, DSP circuit 120, display unit 130, etc.

[0094] Figure 2 This is a diagram illustrating an example of a stacked structure of a solid-state imaging element 200 according to a first embodiment of the present technology. The solid-state imaging element 200 includes a circuit chip 202 and a light-receiving chip 201 stacked on the circuit chip 202. These chips are electrically connected via connection portions such as vias. Note that in addition to vias, connections can also be made via Cu-Cu bonding or bumps.

[0095] [Configuration Examples of Solid-State Imaging Elements]

[0096] Figure 3This is a block diagram illustrating a configuration example of a solid-state imaging element 200 according to a first embodiment of the present technology. The solid-state imaging element 200 includes a vertical scanning circuit 210, a timing control unit 220, a digital-to-analog converter (DAC) 230, a pixel array unit 240, a column signal processing unit 260, and a horizontal scanning circuit 270. In the pixel array unit 240, a plurality of pixel circuits 250 are arranged in a two-dimensional lattice shape.

[0097] For example, pixel array unit 240 is disposed on light receiving chip 201 and the remaining circuitry is disposed on circuit chip 202. Note that the circuitry disposed in each chip is not limited to the circuitry shown in the figure.

[0098] The vertical scanning circuit 210 sequentially selects and drives rows in the pixel array unit 240.

[0099] The timing control unit 220 controls the operation timing of the vertical scanning circuit 210, DAC 230, column signal processing unit 260 and horizontal scanning circuit 270 synchronously with the vertical synchronization signal VSYNC.

[0100] DAC 230 generates a sawtooth ramp signal and provides the generated ramp signal to column signal processing unit 260 as a reference signal.

[0101] Each pixel circuit 250 generates an analog pixel signal through photoelectric conversion under the control of the vertical scanning circuit 210. The pixel circuits 250 of each column output the pixel signal to the column signal processing unit 260 via a vertical signal line (not shown).

[0102] In the column signal processing unit 260, an ADC (not shown) is configured for each column of the pixel circuit 250. Each ADC, under the control of the horizontal scanning circuit 270, converts the pixel signal of the corresponding column into a digital signal and outputs the digital signal to the DSP circuit 120.

[0103] The horizontal scanning circuit 270 controls the column signal processing unit 260 and outputs digital signals sequentially.

[0104] [Pixel Circuit Configuration Example]

[0105] Figure 4 This is a circuit diagram illustrating a configuration example of a pixel circuit 250 according to a first embodiment of the present technology. The pixel circuit 250 includes a photoelectric conversion element 251, a transmission transistor 252, a reset transistor 253, a floating diffusion layer 254, an amplification transistor 255, and a selection transistor 256. Furthermore, in the pixel array unit 240, vertical signal lines 259 are routed to each column along the vertical direction.

[0106] Photoelectric conversion element 251 photoelectrically converts incident light to generate charge. Transfer transistor 252 transfers charge from photoelectric conversion element 251 to floating diffusion layer 254 according to drive signal TRG from vertical scanning circuit 210.

[0107] The reset transistor 253 extracts charge from the floating diffusion layer 254 and initializes the extracted charge according to the drive signal RST from the vertical scan circuit 210.

[0108] The floating diffusion layer 254 accumulates charge and generates a voltage corresponding to the amount of charge. The amplifying transistor 255 amplifies the voltage of the floating diffusion layer 254.

[0109] Select transistor 256 outputs the amplified voltage signal as a pixel signal to column signal processing unit 260 via vertical signal line 259 based on the drive signal SEL from vertical scanning circuit 210.

[0110] [Configuration Example of a Column Signal Processing Unit]

[0111] Figure 5 This is a block diagram illustrating a configuration example of a column signal processing unit 260 according to a first embodiment of the present technology. In the column signal processing unit 260, a comparator 300, a counter 261, and a latch 262 are provided for each column. When the number of columns is N (N is an integer), N comparators 300, N counters 261, and N latches 262 are arranged.

[0112] Comparator 300 compares the reference signal from DAC 230 with the pixel signal from the corresponding column. In the following text, the potential of the reference signal is referred to as the reference potential V. RMP And the potential of the vertical signal line 259 used to transmit pixel signals is called the input potential V. VSL Comparator 300 provides the output signal VCO, indicating the comparison result, to the counter 261 of the corresponding column.

[0113] Furthermore, in the following text, the pixel signal level (i.e., input potential V) when the pixel circuit 250 is initialized... VSL The level is referred to as the "reset level", and the level of the pixel signal when charge is transferred to the floating diffusion layer 254 is referred to as the "signal level".

[0114] Counter 261 counts the value over a period of time until the output signal VCO is inverted. For example, counter 261 performs a decrementing count operation over a period of time until the output signal VCO corresponding to the reset level is inverted, and performs an incrementing count operation over a period of time until the output signal VCO corresponding to the signal level is inverted. Thus, correlated double sampling (CDS) processing is implemented to obtain the difference between the reset level and the signal level.

[0115] Then, counter 261 causes latch 262 to hold a digital signal indicating the count value. The analog pixel signal is converted into a digital signal via A / D conversion, implemented by comparator 300 and counter 261. That is, comparator 300 and counter 261 function as an ADC. An ADC using the comparator and counter described above is generally referred to as a single-slope ADC.

[0116] Note that CDS processing is implemented through up-counting and down-counting operations, but is not limited to this configuration. Counter 261 can be configured to perform only either up-counting or down-counting operations, and subsequent circuitry can perform CDS processing to obtain the difference.

[0117] Latch 262 holds the digital signal. Under the control of horizontal scanning circuit 270, latch 262 outputs the held digital signal.

[0118] [Comparator Configuration Example]

[0119] Figure 6 This is a circuit diagram illustrating a configuration example of a comparator 300 according to a first embodiment of the present technology. The comparator 300 includes an input capacitor 311, an input transistor 312, an auto-zero transistor 313, a cutoff switch 330, a current source 314, a band-limiting capacitor 315, and a clamping transistor 316. Furthermore, the comparator 300 includes an output transistor 317, a current source 318, a clamping transistor 319, and inverters 340 and 350.

[0120] Input capacitor 311 is inserted between DAC 230 and the gate of input transistor 312.

[0121] The source of the input transistor 312 is connected to the vertical signal line 259, and serves as the input potential V of the vertical signal line 259. VSL It is input to the source. Additionally, the reference potential V... RMP The input voltage V is applied to the gate of the input transistor 312 via the input capacitor 311. When the input voltage V is applied to the source of the input transistor 312... VSL and the reference potential V input to the gate of the input transistor 312 RMPWhen they are essentially in agreement, the input transistor 312 outputs from its drain corresponding to the input potential V. VSL and reference potential V RMP The drain voltage. Here, "substantially identical" means that the potentials of the comparison targets are exactly the same or the difference is within a predetermined allowable value. This allowable value is set as the threshold voltage Vt of the input transistor 312. As the input transistor 312, for example, a P-channel metal-oxide-semiconductor (pMOS) transistor is used.

[0122] The auto-zero transistor 313 causes a short circuit between the gate and drain of the input transistor 312 according to the control signal AZSW from the timing control unit 220. For example, a pMOS transistor is used as the auto-zero transistor 313.

[0123] Current source 314 provides a constant current. Current source 314 is implemented using an n-channel MOS (nMOS) transistor, etc.

[0124] A band-limiting capacitor 315 is inserted between the vertical signal line 259 (i.e., the source of the input transistor) and the current source 314. The band-limiting capacitor 315 is provided, and thus a predetermined frequency band, such as a low-frequency band below the cutoff frequency, can be limited. Note that the band-limiting capacitor 315 is an example of the capacitor described in the claims.

[0125] The cut-off switch 330 opens and closes the path between the connection node 329 between the band-limited capacitor 315 and the current source 314 and the drain of the input transistor 312 according to the control signals XPAC1 and PAC1 from the timing control unit 220. When the cut-off switch 330 is closed, the drain voltage of the input transistor 312 is output from the connection node 329 as a comparison result CMP1.

[0126] A clamping transistor 316 is inserted between the source of the input transistor 312 and the connection node 329. An n-channel MOS (pMOS) transistor is used as the clamping transistor 316, and the gate of the clamping transistor 316 is short-circuited to the drain. Furthermore, it is desirable that the back gate and source of the clamping transistor 316 be short-circuited. The clamping transistor 316 can suppress the decrease in drain voltage when the input transistor 312 is turned off. In the following text, the input potential V... VSL The drain-source voltage potential of the low-clamped transistor 316 is called the "clamping potential V". CLP ".

[0127] The source of output transistor 317 is connected to vertical signal line 259, and the input potential V VSLThe input is connected to the source of the output transistor 317. Furthermore, the gate of the output transistor 317 is connected to the drain of the input transistor 312, and the comparison result CMP1 is input. For example, a pMOS transistor is used as the output transistor 317. Furthermore, it is desirable that the back gate and source of the output transistor 317 be short-circuited.

[0128] The output transistor 317 outputs an indicator V from the drain to the source, indicating the input potential V. VSL The signal indicating whether the difference between the comparison result CMP1 and the input comparison result CMP2 exceeds a predetermined threshold voltage is used as the comparison result CMP2. The comparison result CMP2 is input to the inverter 340. Note that the output transistor 317 is an example of the second output transistor described in the claims.

[0129] Here, when the pixel signal and the reference signal are substantially in sync, the drain voltage of the input transistor 312 (i.e., the comparison result CMP1) varies according to the level of the pixel signal. Therefore, when the comparison result CMP1 is input to a subsequent circuit, for example, one with a fixed threshold based on ground potential, the timing of the inverted drain voltage may deviate from the ideal timing where the pixel signal and the reference signal are substantially in sync.

[0130] Using the connections shown in the figure, the drain-source voltage of the input transistor 312 is input as the gate-source voltage of the output transistor 317. Since the change in the drain voltage of the input transistor 312 is equal to the change in the pixel signal voltage, the comparison result CMP2 from the output transistor 317 is inverted during ideal timing, where the pixel signal and the reference signal are substantially synchronized. When the comparison result CMP2 is connected to a subsequent circuit with a fixed threshold based on ground potential, similar to the comparison result CMP1, the comparison result CMP2 varies according to the pixel signal level. However, since the gain is higher than that of the comparison result CMP1, errors are unlikely to be observed. As described above, the inversion timing error can be suppressed by adding the output transistor 317.

[0131] A current source 318 is inserted between the drain of the output transistor 317 and the reference potential VSSB, and provides a constant current. The current source 318 is implemented using an nMOS transistor or the like.

[0132] A clamping transistor 319 is inserted between the source and drain of the output transistor 317. An n-channel MOS (pMOS) transistor is used as the clamping transistor 319, and the gate of the clamping transistor 319 is short-circuited to the drain. Furthermore, it is desirable that the back gate and source of the clamping transistor 319 be short-circuited. The clamping transistor 319 suppresses the decrease in drain voltage when the output transistor 317 is in the off state. The clamping potential corresponding to the clamping transistor 319 is substantially the same as the clamping potential corresponding to the clamping transistor 316.

[0133] Note that clamping transistor 316, output transistor 317, and clamping transistor 319 are provided in comparator 300, but at least one of clamping transistor 316, output transistor 317, or clamping transistor 319 may not be provided. Without output transistor 317, current source 318 and clamping transistor 319 are unnecessary.

[0134] Reference potential V RMP It is set to a potential higher than the auto-zero level at the start of the AD conversion and decreases as time passes during the AD conversion period. Here, the AD conversion period is the period during which counter 261 performs counting. At the beginning of the AD conversion period, the input transistor 312 of the first stage is cut off, current flows through clamping transistor 316, and a current lower than the input potential V is output from connection node 329 via cutoff switch 330. VSL clamping potential V CLP As a comparison result, CMP1. The output transistor 317 of the second stage is turned on, and the output input potential V is output. VSL CMP2 was the comparison result.

[0135] Then, when the reference potential V RMP The gate potential of the input transistor 312, which is reduced and is in the above-described substantially consistent state, is reduced by the decrease in the voltage from the input potential V. VSL When the value obtained by subtracting the threshold Vt of the input transistor 312 is subtracted, the first-stage input transistor 312 transitions to the on state, and the comparison result CMP1 is inverted to the input potential V. VSL The output transistor 317 of the second stage transitions to the cutoff state, and the comparison result CMP2 is inverted to the clamping potential V. CLP .

[0136] As described above, the potential of the comparison result CMP1 is at the clamping potential V. CLP to input potential V VSL The value is within the range. Furthermore, the comparison result CMP1 output from connection node 329 changes from a low level (clamping potential V) during the counting period of counter 261 (i.e., the AD conversion period). CLP Transition to high level (input potential V) VSL Therefore, the potential of connection node 329 needs to be initialized to low level immediately before the AD conversion period. Timing control unit 220 controls cut-off switch 330 to open during a predetermined pulse period when it is initialized to low level. Therefore, connection node 329 is disconnected from the drain of input transistor 312. Furthermore, except during the pulse period, when cut-off switch 330 is closed, connection node 329 is connected to the drain of input transistor 312.

[0137] Note the clamping potential V output from input transistor 312.CLP and input potential V VSL This represents an example of a pair of output potentials described in the claims.

[0138] Inverter 340 inverts the comparison result CMP2 and provides the inverted signal to inverter 350. Inverter 350 inverts the inverted signal provided by inverter 340 and provides the inverted signal as the output signal VCO to counter 261.

[0139] Note that instead of inverters 340 and 350, other logic gates such as buffers and NOR gates can be provided. Inverters 340 and 350 are examples of the logic gates described in the claims.

[0140] [Configuration example of a cut-off switch and inverter]

[0141] Figure 7 This is a circuit diagram illustrating an example configuration of the cut-off switch 330 and inverters 340 and 350 according to a first embodiment of the present technology. In the figures, a is a circuit diagram illustrating an example configuration of the cut-off switch 330. In the figures, b is a circuit diagram illustrating an example configuration of the inverters 340 and 350.

[0142] As shown in Figure a, the cutoff switch 330 includes an nMOS transistor 331 and a pMOS transistor 332, which are connected in parallel between the drain of the input transistor 312 and the current source 314. A control signal XPAC1 is input to the gate of the nMOS transistor 331, and a control signal PAC1 is input to the gate of the pMOS transistor 332. The control signal XPAC1 is a signal with a phase difference of 180 degrees from the control signal PAC1.

[0143] Furthermore, nMOS transistor 331 is an example of an N-type transistor as described in the claims, and pMOS transistor 332 is an example of a P-type transistor as described in the claims.

[0144] Furthermore, as shown in Figure b, inverter 340 includes pMOS transistor 341 and nMOS transistor 342. Inverter 350 includes pMOS transistor 351 and nMOS transistor 352.

[0145] In inverter 340, pMOS transistor 341 and nMOS transistor 342 are connected in series between the power supply potential VDDC and the reference potential VSSC. The comparison result CMP2 is input to the gates of pMOS transistor 341 and nMOS transistor 342. The inverting signal INV is output from the connection node between pMOS transistor 341 and nMOS transistor 342 to inverter 350. Here, the power supply potential VDDB is a different power supply potential than the power supply potential VDDA of pixel circuit 250. Furthermore, the reference potential VSSC is a different potential than the reference potential VSSB of comparator 300.

[0146] In inverter 350, pMOS transistor 351 and nMOS transistor 352 are connected in series between the power supply potential VDDC and the reference potential VSSC. The inverting signal INV is input to the gates of pMOS transistor 351 and nMOS transistor 352. The output signal VCO is output from the connection node between pMOS transistor 351 and nMOS transistor 352 to counter 261.

[0147] Inverters 340 and 350 can convert the power supply potential VDDB of the preceding stage to a low power supply potential VDDC.

[0148] Figure 8 These are diagrams illustrating the improved responsiveness of the first embodiment of the present invention. In the figures, a is a circuit diagram showing a configuration example of the comparator 300 without the cut-off switch 330. In the figures, b is a circuit diagram showing a configuration example of the comparator 300 according to the first embodiment of the present invention.

[0149] As shown in Figure a, consider a comparative example with a configuration where the cutoff switch 330 is not provided and the drain of the input transistor 312 is connected to the connection node 329. In this comparative example, to make the potential of the connection node 329 start from a high level (input potential V), VSL Transition to low level (clamping potential V) CLP ), equal to or higher than the input potential V VSL High-level reference potential V RMP It is input to input transistor 312.

[0150] When a high-level reference potential V is input RMP At this time, input transistor 312 switches to the cutoff state, and the comparison result CMP1 switches from high to low. However, due to the reference potential V... RMP and input potential V VSL The difference between them is relatively small, so the input transistor 312 does not completely cut off the current, but only slightly. Therefore, leakage current flows between the drain and source of the input transistor 312.

[0151] Furthermore, since current source 314 provides a constant current, band-limited capacitor 315 discharges through the differential current between the leakage current of input transistor 312 and the constant current provided by current source 314. The thin arrows in Figure a indicate the differential current and leakage current. The thick arrows represent the constant current.

[0152] The comparison result shows that the speed at which CMP1 transitions to a low level based on the input (i.e., the response speed) is determined by the slew rate and settling time. The slew rate of the first stage represents the rate at which the potential of connection node 329 decreases when the band-limited capacitor 315 is discharged through the discharge current. The settling time of the first stage means the time until the potential of connection node 329 transitions to a low level, considering the RC circuit including the output impedance of the input transistor 312 and the band-limited capacitor 315. As the discharge current increases, the slew rate increases and the response speed increases. Furthermore, the settling time becomes longer, and the response speed decreases as the capacitance of the band-limited capacitor 315 increases.

[0153] Specifically, because the input transistor 312 is source-grounded, when the drain conductance is set to g ds When the output impedance is 1 / g ds The response speed is relatively high. Furthermore, in Figure a, since discharge is performed through the differential current (thin arrow) between the leakage current and the constant current, the discharge current becomes smaller than the discharge current without leakage current, and the response speed decreases. Additionally, because the drain-source parasitic capacitor of the input transistor 312 acts as part of the band-limited capacitor 315, its capacitance value becomes larger than in the case without parasitic capacitors, and the response speed decreases. The capacitors indicated by dashed lines in the figure represent parasitic capacitors.

[0154] On the other hand, as shown in Figure b, when the cutoff switch 330 is set and open, the leakage current is cut off, so the discharge current becomes larger than the discharge current of the comparative example. Furthermore, since the input transistor 312 is open, the capacitance value decreases, resulting in a lower drain-source parasitic capacitance. Therefore, compared to the comparative example, the response speed and responsiveness are improved.

[0155] [Operational Examples of Solid-State Imaging Elements]

[0156] Figure 9 This is a timing diagram illustrating an example of the operation of a solid-state imaging element 200 according to a first embodiment of the present technology. The alternating long and short dashed lines in the diagram represent the potential (input potential V) of the vertical signal line 259. VSL ).

[0157] During the automatic zeroing period from timing T0 to timing T1, DAC 230 will set the reference potential V. RMP Set to automatic zeroing potential VAZ Furthermore, the timing control unit 220 sets the control signal AZSW to a low level. Therefore, the comparison results CMP1 and CMP2 become the auto-zeroing potential V. AZ Furthermore, control signal PAC1 is controlled to a low level, and control signal XPAC1 is controlled to a high level. Therefore, cut-off switch 330 is closed.

[0158] The timing control unit 220 sets the control signal AZSW to a high level during timing T1 to timing T8. Furthermore, during timing T1, the timing control unit 220 sets the control signal PAC1 to a high level and the control signal XPAC1 to a low level for a predetermined pulse period. Therefore, the cut-off switch 330 is open.

[0159] During the time period from timing T1 to timing T2, DAC 230 will reference potential V RMP The voltage is set to a level higher than the auto-zero time. Therefore, input transistor 312 is cut off, and the output clamping potential V is output. CLP The comparison result is CMP1. At this point, the clamping potential is higher than the clamping potential corresponding to the signal level, and this potential is set to V. CLPH During this period, output transistor 317 is turned on and outputs a reset level V. VSLL The comparison result is CMP2. Furthermore, inverter 350 outputs a high-level output signal VCO.

[0160] Here, the comparison results CMP1 and CMP2, as well as the output signal VCO, do not actually transition instantaneously from one high level to the other, but require a predetermined time corresponding to a time constant, etc., until the transition is complete. However, in the accompanying figures, for ease of description, the waveforms are shown as an instantaneous transition.

[0161] Then, during the time period from timing T2 to timing T4, DAC 230 decreases the reference potential V as time passes. RMP This period corresponds to the AD conversion period at the reset level. Assume the reference potential V... RMP and input potential V VSL The difference between them is less than the threshold voltage Vt of the input transistor 312 at timing T3 during that period. At this time, the input transistor 312 switches to the on state, and the comparison result CMP1 is inverted to the reset level Vt. VSLL The output transistor 317 transitions to the cutoff state, and the comparison result CMP2 is inverted to the clamping potential V. CLPH The output signal VCO is inverted to a low level.

[0162] At time T5, the timing control unit 220 sets the control signal PAC1 to a high level and the control signal XPAC1 to a low level during a predetermined pulse period. Therefore, the cut-off switch 330 is turned off.

[0163] Furthermore, during the time period from timing T5 to timing T6, DAC 230 will reference potential V RMP The voltage is set to a level higher than the auto-zero time. Therefore, input transistor 312 is cut off, and the output clamping potential V is output. CLP The comparison result is CMP1. At this point, the clamping potential is lower than the clamping potential corresponding to the black level, and this potential is set to V. CLPL During this period, output transistor 317 is turned on and outputs signal level V. VSLL The comparison result is CMP2. Furthermore, inverter 350 outputs a high-level output signal VCO.

[0164] Then, during the time period from timing T6 to timing T8, DAC 230 decreases the reference potential V as time passes. RMP This period corresponds to the AD conversion period of the signal level. Assume a reference potential V. RMP and input potential V VSL The difference between them is less than the threshold voltage Vt of timing T7 during that period. At this time, the comparison result CMP1 is inverted to the signal level V. VSLL The comparison result shows that CMP2 is inverted to the clamping potential V. CLPL The output signal VCO is inverted to a low level.

[0165] As shown in the figure, the timing control unit 220 controls the cut-off switch 330 to disconnect during the predetermined pulse period of timing T1 and timing T5, which immediately precede the AD conversion period.

[0166] Figure 10 This is an example of a timing diagram showing a black level input during the signal level transition period according to the first embodiment of this technology. In the figure, a shows the potential (input potential V) of the vertical signal line 259. VSL ) and reference potential V RMP The figures show examples of waveforms. In the figures, b is an example of the waveform of the comparison result CMP1 in the comparison example without the cut-off switch 330. In the figures, c is an example of the waveform of the comparison result CMP1 in the first embodiment with the cut-off switch 330.

[0167] As shown by the alternating long and short dashed lines in the figure, the black level, which is basically the same as the reset level, is input as the signal level.

[0168] As shown in Figure b, in the comparison example without the cutoff switch 330, the slope of the comparison result CMP1 transitioning from high to low is gentle, and the time until the comparison result CMP1 transitions to low becomes longer. The thick line in the figure represents the trajectory during the transition from high to low. Furthermore, immediately after timing T2 or timing T6, since the transition to high begins before the clamping potential decreases, the amplitude of the transition from low to high differs between the reset level transition time and the signal level transition time. The arrows between opposite ends in the figure indicate the magnitude of the amplitude. Therefore, the characteristics of comparator 300 deteriorate.

[0169] On the other hand, as shown in Figure c, when the cutoff switch 330 is provided, the slope of the transition from high to low level becomes abrupt due to the cutoff of leakage current and parasitic capacitor, and the time until the transition to low level is shortened. Furthermore, since the transition to high level begins after decreasing to the clamping potential, the amplitude from low to high level is the same between the reset level transition time and the signal level transition time. Therefore, the degradation of the comparator 300's characteristics can be suppressed.

[0170] Figure 11 This is an example of a timing diagram showing a white input level during a signal level transition period according to the first embodiment of this technology. In the figure, a shows the potential (input potential V) of the vertical signal line 259. VSL ) and reference potential V RMP The figures show examples of waveforms. In the figures, b is an example of the waveform of the comparison result CMP1 in the comparison example without the cut-off switch 330. In the figures, c is an example of the waveform of the comparison result CMP1 in the first embodiment with the cut-off switch 330.

[0171] As shown by the dashed line in Figure a, the input signal level is a white level lower than the reset level.

[0172] As shown in Figure b, in the comparison example without the cutoff switch 330, the time until the comparison result CMP1 transitions to a low level becomes longer. Furthermore, the amplitude of the low-to-high level transition differs between the reset level transition time and the signal level transition time.

[0173] On the other hand, as shown in Figure c, when the cutoff switch 330 is provided, the time until the transition to a low level is shortened due to the cutoff of leakage current and parasitic capacitor. Furthermore, the amplitude from low to high level is the same between the reset level transition time and the signal level transition time.

[0174] Figure 12This is a flowchart illustrating an example of the operation of a solid-state imaging element 200 according to a first embodiment of the present technology. For example, the operation begins when a predetermined application for capturing image data is executed.

[0175] Vertical scan circuit 210 selects and exposes the read row (step S911). Cut-off switch 330 disconnects input transistor 312 from connection node 329 during the pulse period (step S912). Column signal processing unit 260 performs AD conversion on the reset level of each column (step S913). Cut-off switch 330 disconnects input transistor 312 from connection node 329 during the pulse period (step S914). Column signal processing unit 260 performs AD conversion on the signal level of each column (step S915). Then, vertical scan circuit 210 determines whether the read row is the last row (step S916).

[0176] If the line being read is not the last line (step S916: No), the solid-state imaging element 200 repeats step S911 and subsequent steps. On the other hand, if the line being read is the last line (step S916: Yes), the solid-state imaging element 200 terminates the imaging operation.

[0177] It is important to note that, in Figure 9 The operation of the timing diagram shown corresponds to in Figure 12 Steps S912 to S915 in the process.

[0178] When multiple image data are captured continuously, steps S911 to S916 are repeated in sync with the vertical synchronization signal.

[0179] As described above, according to the first embodiment of this technology, since the cut-off switch 330 disconnects the input transistor 312 from the connection node 329, the leakage current of the input transistor 312 can be cut off and the parasitic capacitor can be disconnected from the connection node 329. Therefore, the responsiveness of the comparator 300 can be improved.

[0180] [First Variation]

[0181] In the first embodiment described above, a cutoff switch 330, comprising an nMOS transistor 331 and a pMOS transistor 332, is configured in each column. However, in this configuration, the number of transistors increases compared to the case where the cutoff switch 330 is implemented by a single transistor. The solid-state imaging element 200 of the first variation of the first embodiment differs from the solid-state imaging element of the first embodiment in that it uses a cutoff switch 330 comprising only an nMOS transistor 331.

[0182] Figure 13This is a circuit diagram illustrating a configuration example of a comparator 300 according to a first variation of the first embodiment of the present technology. The comparator 300 of the first variation of the first embodiment differs from the comparator of the first embodiment in that it is arranged with only a cutoff switch 330 comprising an nMOS transistor 331. The waveform of the control signal XPAC1 used to control the nMOS transistor 331 is similar to that of the first embodiment.

[0183] By implementing the cutoff switch 330 using only the nMOS transistor 331, the number of transistors can be reduced compared to using a pair of transistors (nMOS transistor 331 and pMOS transistor 332).

[0184] As described above, in the first variation of the first embodiment of the present technology, since a cutoff switch 330 consisting only of an nMOS transistor 331 is used, the number of transistors can be reduced compared to the case where a pair of transistors are used.

[0185] [Second variation]

[0186] In the first embodiment described above, a cutoff switch 330, comprising an nMOS transistor 331 and a pMOS transistor 332, is configured in each column. However, in this configuration, the number of transistors increases compared to the case where the cutoff switch 330 is implemented by a single transistor. The solid-state imaging element 200 of the second variation of the first embodiment differs from the solid-state imaging element of the first embodiment in that it uses a cutoff switch 330 comprising only a pMOS transistor 332.

[0187] Figure 14 This is a circuit diagram illustrating a configuration example of a comparator 300 according to a second variation of the first embodiment of the present technology. The comparator 300 of the second variation of the first embodiment differs from the comparator of the first embodiment in that it includes a cutoff switch 330 comprising only a pMOS transistor 332. The waveform of the control signal PAC1 used to control the pMOS transistor 332 is similar to that of the first embodiment.

[0188] By implementing the cutoff switch 330 using only the pMOS transistor 332, the number of transistors can be reduced compared to using a pair of transistors (nMOS transistor 331 and pMOS transistor 332).

[0189] like Figure 14 and Figure 15As shown, the cutoff switch 330 can be implemented using only nMOS transistor 331 or only pMOS transistor 332. When the level of the comparison result CMP1 in the first stage is relatively low, nMOS transistor 331 is used. On the other hand, when the level of the comparison result CMP1 in the first stage is relatively high, pMOS transistor 332 is used. Furthermore, when the level of the comparison result CMP2 is approximately the midpoint of the power supply potential VDDB, both nMOS transistor 331 and pMOS transistor 332 are used, as in the first embodiment.

[0190] As described above, in the second variation of the first embodiment of the present technology, since a cutoff switch 330 consisting only of a pMOS transistor 332 is used, the number of transistors can be reduced compared to the case where a pair of transistors are used.

[0191] <2. Second Embodiment>

[0192] In the first embodiment described above, the cutoff switch 330 shortens the time until the comparison result CMP1 transitions to a low level. However, the response speed until the comparison result CMP2 of the second stage is at a high level may not be sufficiently increased by the cutoff switch 330. The solid-state imaging element 200 of the second embodiment differs from the solid-state imaging element of the first embodiment in that the responsiveness is improved by short-circuiting the source and drain of the output transistor 317.

[0193] Figure 15 This is a circuit diagram illustrating a configuration example of a comparator 300 according to a second embodiment of the present technology. The comparator 300 of the second embodiment differs from the comparator of the first embodiment in that an output-side short-circuit switch 360 is provided instead of a cut-off switch 330. Furthermore, the drain of the input transistor 312 in the second embodiment is connected to a connection node 329.

[0194] The output-side short-circuit switch 360 opens and closes the path between the source (in other words, the vertical signal line 259) and the drain of the output transistor 317 according to the control signals XPAC2 and PAC2 from the timing control unit 220.

[0195] The output-side short-circuit switch 360 includes, for example, an nMOS transistor 361 and a pMOS transistor 362 connected in parallel between the source and drain of the output transistor 317. A control signal PAC2 is input to the gate of the nMOS transistor 361, and a control signal XPAC2 is input to the gate of the pMOS transistor 362. The control signal XPAC2 is a signal with a phase difference of 180 degrees from the control signal PAC2.

[0196] Note that nMOS transistor 361 is an example of an N-type transistor described in the claims, while pMOS transistor 362 is an example of a P-type transistor described in the claims.

[0197] The second-level comparison result shows that the potential of CMP2 is at the clamping potential V. CLP to input potential V VSL The value is within the range. Furthermore, the comparison result CMP2 from the drain of the output transistor 317 changes from a high level (input potential V) during the counting period of the counter 261 (i.e., the AD conversion period). VSL Transition to low level (clamping potential V) CLP Therefore, the drain of the output transistor 317 needs to be initialized to a high level immediately before the AD conversion period.

[0198] Here, the speed at which the comparison result CMP2 transitions to a high level based on the input is determined by the slew rate and settling time (i.e., the response speed). The slew rate of the second stage represents the rate of rise of the drain when the parasitic capacitor on the drain side of the output transistor 317 is charged using the charging current from the output transistor 317. The settling time of the second stage means the time until the drain potential transitions to a high level, taking into account the RC circuit including the output impedance of the output transistor 317 and the parasitic capacitor. The capacitor represented by the dashed line in the figure represents the parasitic capacitor.

[0199] Furthermore, the comparison result CMP2 of the second stage is interlocked with the comparison result CMP1 of the first stage, and the response speed of the second stage also decreases when the response speed of the first stage decreases.

[0200] When the timing control unit 220 initializes to a high level, it controls the output-side short-circuit switch 360 to close during a predetermined pulse period. Therefore, the source (vertical signal line 259) and drain of the output transistor 317 are short-circuited. Since the potential of the vertical signal line 259 is at a high level (input potential V),... VSL Therefore, the speed at which the comparison result CMP2 transitions to a high level can be increased due to the short circuit. Furthermore, during automatic zeroing, the short-circuit switch 360 on the control output side is closed.

[0201] Figure 16 This is a timing diagram illustrating an example of the operation of a solid-state imaging element 200 according to a second embodiment of the present technology.

[0202] From timing T0 to timing T1, during the automatic zeroing period, timing control unit 220 sets control signal PAC2 to a high level and control signal XPAC2 to a low level. Therefore, cut-off switch 330 is closed.

[0203] Then, the timing control unit 220 sets control signal PAC2 high and control signal XPAC2 low until a pulse period has elapsed since timing T1. After the pulse period, control signal PAC2 is controlled low and control signal XPAC2 is controlled high. Therefore, the cut-off switch 330 is opened.

[0204] During the reset level transition period at timing T5, the timing control unit 220 sets the control signal PAC2 high and the control signal XPAC1 low within a predetermined pulse period. This closes the output-side short-circuit switch 360. After the pulse period, the control signal PAC2 is controlled to low and the control signal XPAC1 is controlled to high. Therefore, the cut-off switch 330 opens.

[0205] As shown in the figure, the timing control unit 220 controls the output-side short-circuit switch 360 to close during predetermined pulse periods at timings T1 and T5 before the AD conversion. Therefore, the speed at which the comparison result CMP2 transitions to a high level (response speed) can be increased.

[0206] Furthermore, the timing control unit 220 also controls the output-side short-circuit switch 360 to close during the auto-zeroing period from timing T0 to timing T1. The loop circuit is formed by the first-stage input transistor 312, the second-stage output transistor 317, and the vertical signal line 259, and there is a possibility that the loop circuit will oscillate during the auto-zeroing period. However, by controlling the closing of the output-side short-circuit switch 360 during the auto-zeroing period, oscillations during auto-zeroing can be suppressed.

[0207] Figure 17 This is an example of a timing diagram showing a black level input during the signal level transition period according to the second embodiment of this technology. In the figure, a shows the potential of the vertical signal line 259 (input potential V). VSL ) and reference potential V RMP The figures show examples of waveforms. In the figure, b is an example of the waveform of the comparison result CMP2 in the comparison example without the output-side short-circuit switch 360. In the figure, c is an example of the waveform of the comparison result CMP2 in the second embodiment with the output-side short-circuit switch 360 provided.

[0208] As shown in Figure a, the black level, which is basically the same as the reset level, is input as the signal level.

[0209] As shown in Figure b, in the comparison example without the output-side short-circuit switch 360, the slope of the comparison result CMP2 transitioning from low to high is gentle, and the time until the comparison result CMP2 transitions to high becomes longer. The thick line in the figure represents the trajectory during the transition from low to high.

[0210] Furthermore, immediately following timing T6, the transition to a low level begins before reaching the reset level. Therefore, the amplitude of the high-to-low transition differs between the reset level transition time and the signal level transition time. Consequently, the characteristics of comparator 300 deteriorate.

[0211] On the other hand, as shown in Figure c, when the output-side short-circuit switch 360 is set, the time until the transition to a high level is shortened due to the short circuit between the source (vertical signal line 259) and drain of the output transistor 317. Furthermore, since the transition to a low level begins after the reset level is reached, the amplitude from high to low is the same between the reset level transition time and the signal level transition time. Therefore, the degradation of the comparator 300's characteristics can be suppressed.

[0212] Figure 18 This is an example of a timing diagram showing a white input level during the signal level transition period according to the second embodiment of this technology. In the figure, a shows the potential (input potential V) of the vertical signal line 259. VSL ) and reference potential V RMP The figures show examples of waveforms. In the figure, b is an example of the waveform of the comparison result CMP2 in the comparison example without the output-side short-circuit switch 360. In the figure, c is an example of the waveform of the comparison result CMP2 in the second embodiment with the output-side short-circuit switch 360 provided.

[0213] As shown in Figure a, the input is a white level lower than the reset level, which serves as the signal level.

[0214] As shown in Figure b, in the comparison example without an output-side short-circuit switch 360, the time until the comparison result CMP2 transitions to a high level becomes longer. Furthermore, the amplitude of the transition from high to low level differs between the reset level transition time and the signal level transition time.

[0215] On the other hand, as shown in Figure c, when the output-side short-circuit switch 360 is provided, the time until the transition to the high level is shortened due to the short circuit. Furthermore, the amplitude from high to low level is the same between the reset level transition time and the signal level transition time.

[0216] As described above, according to the second embodiment of this technology, since the output-side short-circuit switch 360 short-circuits the source and drain of the output transistor 317, the speed at which the comparison result CMP2 transitions to the source potential (high level) can be improved. Therefore, responsiveness can be improved.

[0217] [First Variation]

[0218] In the second embodiment described above, an output-side short-circuit switch 360, comprising an nMOS transistor 361 and a pMOS transistor 362, is configured in each column. However, in this structure, the number of transistors increases compared to the case where the output-side short-circuit switch 360 is implemented by a single transistor. The solid-state imaging element 200 according to the first variation of the second embodiment differs from the solid-state imaging element of the first embodiment in that it uses an output-side short-circuit switch 360 comprising only an nMOS transistor 361.

[0219] Figure 19 This is a circuit diagram illustrating a configuration example of a comparator 300 according to a first variation of the second embodiment of the present technology. The comparator 300 of the first variation of the second embodiment differs from the comparator of the second embodiment in that it includes an output-side short-circuit switch 360 comprising only an nMOS transistor 361. The waveform of the control signal PAC2 used to control the nMOS transistor 361 is similar to that of the second embodiment.

[0220] By implementing the output-side short-circuit switch 360 using only the nMOS transistor 361, the number of transistors can be reduced compared to using a pair of transistors (nMOS transistor 361 and pMOS transistor 362).

[0221] As described above, in the first variation of the second embodiment of the present technology, since an output-side short-circuit switch 360 consisting only of an nMOS transistor 361 is used, the number of transistors can be reduced compared to the case where a pair of transistors are used.

[0222] [Second variation]

[0223] In the second embodiment described above, an output-side short-circuit switch 360, comprising an nMOS transistor 361 and a pMOS transistor 362, is configured in each column. However, in this structure, the number of transistors increases compared to the case where the output-side short-circuit switch 360 is implemented by a single transistor. The solid-state imaging element 200 of the second variation of the second embodiment differs from the solid-state imaging element of the first embodiment in that it uses an output-side short-circuit switch 360 comprising only a pMOS transistor 362.

[0224] Figure 20 This is a circuit diagram illustrating a configuration example of a comparator 300 according to a second modification of the second embodiment of the present invention. The comparator 300 of the second modification of the second embodiment differs from the comparator of the second embodiment in that it includes only an output-side short-circuit switch 360 for the pMOS transistor 362. The waveform of the control signal XPAC2 used to control the pMOS transistor 362 is similar to that of the second embodiment.

[0225] By implementing the output-side short-circuit switch 360 using only the pMOS transistor 362, the number of transistors can be reduced compared to using a pair of transistors (nMOS transistor 361 and pMOS transistor 362).

[0226] like Figure 19 and Figure 20 As shown, the output-side short-circuit switch 360 can be implemented using only nMOS transistor 361 or only pMOS transistor 362. When the level of the comparison result CMP2 in the second stage is relatively low, nMOS transistor 361 is used. On the other hand, when the level of the comparison result CMP2 in the second stage is relatively high, pMOS transistor 362 is used. Furthermore, when the level of the comparison result CMP2 is approximately the midpoint of the power supply potential VDDB, both nMOS transistor 361 and pMOS transistor 362 are used, as in the second embodiment.

[0227] As described above, in the second variation of the second embodiment of the present technology, since an output-side short-circuit switch 360 consisting only of a pMOS transistor 362 is used, the number of transistors can be reduced compared to the case where a pair of transistors are used.

[0228] <3. Third Implementation Method>

[0229] In the first embodiment described above, the cutoff switch 330 shortens the time until the comparison result CMP1 transitions to a low level. However, the response speed until the comparison result CMP2 of the second stage is at a high level may not be sufficiently increased by the cutoff switch 330 alone. The solid-state imaging element 200 of the third embodiment differs from the solid-state imaging element of the first embodiment in that it further improves responsiveness by adding a switch for short-circuiting the source and drain of the output transistor 317.

[0230] Figure 21 This is a circuit diagram illustrating a configuration example of a comparator 300 according to a third embodiment of the present technology. The comparator 300 of the third embodiment differs from the comparator of the first embodiment in that it further includes an output-side short-circuit switch 360. Similar to the second variation of the second embodiment, the output-side short-circuit switch 360 is implemented solely by a pMOS transistor 362. The third embodiment is obtained by applying the second variation of the second embodiment to the first embodiment.

[0231] By adding an output-side short-circuit switch 360, the speed at which the output of the second stage transitions to a high level can be increased, and the responsiveness of the comparator 300 can be further improved.

[0232] Note that both nMOS transistor 331 and pMOS transistor 332 are provided in the cut-off switch 330, but only one of nMOS transistor 331 and pMOS transistor 332 may be provided.

[0233] Furthermore, the output-side short-circuit switch 360 is implemented solely by the pMOS transistor 362, but this disclosure is not limited to this configuration. Both the nMOS transistor 361 and the pMOS transistor 362 may be provided in the output-side short-circuit switch 360, but only the nMOS transistor 361 may be provided.

[0234] Figure 22 This is a timing diagram illustrating an example of the operation of a solid-state imaging element 200 according to a third embodiment of the present technology. The timing control unit 220 further provides a control signal XPAC2 to control the output-side short-circuit switch 360. The waveform of the control signal XPAC2 is similar to that of the second variation of the second embodiment.

[0235] As described above, according to the third embodiment of this technology, since the output-side short-circuit switch 360 short-circuits the source and drain of the output transistor 317, the speed at which the comparison result CMP2 transitions to the source potential (high level) can be improved. Therefore, the responsiveness can be further improved.

[0236] <4. Fourth Embodiment>

[0237] In the third embodiment described above, two transistors, input transistor 312 and output transistor 317, are provided; however, a third-stage transistor with the same configuration as output transistor 317 can be added. The solid-state imaging element 200 of the fourth embodiment differs from the solid-state imaging element of the third embodiment in that a third-stage transistor is added.

[0238] Figure 23 This is a circuit diagram illustrating a configuration example of a comparator 300 according to a fourth embodiment of the present technology. The comparator 300 of the fourth embodiment differs from the comparator of the third embodiment in that it includes an output transistor 320, a current source 321, and a clamping transistor 322, but does not include an inverter 340.

[0239] The source of the output transistor 320 is connected to the vertical signal line 259, and the input potential V VSL The input is given to the source of output transistor 320. Furthermore, the gate of output transistor 320 is connected to the drain of the second-stage output transistor 317, and the comparison result CMP2 is input. For example, a pMOS transistor is used as the third-stage output transistor 320. Additionally, it is desirable that the back gate and source of output transistor 320 be short-circuited.

[0240] The output transistor 320 outputs an indicator voltage V from the drain to the source. VSL The signal indicating whether the difference between the comparison result CMP2 and the comparison result CMP3 input to the gate exceeds a predetermined threshold voltage is used as the comparison result CMP3. The comparison result CMP3 is input to the inverter 350. Note that the output transistor 320 is an example of the second output transistor described in the claims.

[0241] A current source 321 is inserted between the drain of the output transistor 320 and the reference potential VSSB, and provides a constant current. The current source 321 is implemented using an nMOS transistor or the like.

[0242] A clamping transistor 322 is inserted between the source and drain of the output transistor 320. A pMOS transistor is used as the clamping transistor 322, and the gate of the clamping transistor 322 is short-circuited to the drain. Furthermore, it is desirable that the back gate and source of the clamping transistor 322 be short-circuited.

[0243] When the output-side short-circuit switch 360 of the second stage transitions to the on state immediately before the AD conversion, the gate-source voltage of the third stage approaches zero, the output transistor 320 is forcibly turned off, and the comparison result CMP3 transitions to the clamping potential. Therefore, unlike the first stage, the cutoff switch 330 is unnecessary in the third stage.

[0244] As shown in the figure, since the output transistor 320 is added to the third stage, the inverter 340 is removed.

[0245] Furthermore, although both the cut-off switch 330 and the output-side short-circuit switch 360 are configured, it is also possible to configure only one of the cut-off switch 330 and the output-side short-circuit switch 360. Additionally, both nMOS transistors and pMOS transistors can be provided in each of the cut-off switch 330 and the output-side short-circuit switch 360, or only one of the nMOS transistors and pMOS transistors can be provided.

[0246] In addition, transistors equivalent to output transistor 320 can be added to create four or more stages. In this case, a switch equivalent to output-side short-circuit switch 360 can also be provided in even-numbered stages after the fourth stage, but not in odd-numbered stages.

[0247] As described above, in the fourth embodiment of this technology, since the input potential V is determined... VSL The output transistor 320, which determines whether the difference between the comparison result CMP2 and the output transistor exceeds a predetermined threshold voltage, is added to the third stage. This increases the gain of the comparator 300 and improves its linearity.

[0248] <5. Fifth Implementation Method>

[0249] In the third embodiment described above, just before the AD conversion, the cutoff switch 330 disconnects the drain of the input transistor 312 from the connection node 329, and the input transistor 312 transitions to an off state. However, in this configuration, the drain of the input transistor 312 in the off state becomes a high-impedance node. Since the potential of a high-impedance node is easily changed due to capacitive coupling, the potential of the gate of the input transistor 312 changes due to this change, and there is a possibility of degradation of the comparator 300's characteristics. The solid-state imaging element 200 of the fifth embodiment differs from the solid-state imaging element of the third embodiment in that performance degradation is suppressed by short-circuiting the source and drain of the input transistor 312.

[0250] Figure 24 This is a circuit diagram illustrating a configuration example of a comparator 300 according to a fifth embodiment of the present technology. The comparator 300 of the fifth embodiment further includes an input-side short-circuit switch 370.

[0251] The input-side short-circuit switch 370 opens and closes the path between the source (vertical signal line 259) and drain of the input transistor 312 according to the control signals PAC1 and XPAC1.

[0252] Furthermore, the input-side short-circuit switch 370 includes, for example, an nMOS transistor 371 and a pMOS transistor 372, which are connected in parallel between the source and drain of the input transistor 312. A control signal PAC1 is input to the gate of the nMOS transistor 371, and a control signal XPAC1 is input to the gate of the pMOS transistor 372.

[0253] According to control signals PAC1 and XPAC1, when the cut-off switch 330 is open, the input-side short-circuit switch 370 closes, short-circuiting the source and drain of the input transistor 312. Therefore, it prevents the drain of the input transistor 312 from becoming a high-impedance node and suppresses characteristic degradation.

[0254] Note that although both the cut-off switch 330 and the output-side short-circuit switch 360 are arranged, only one of them may be arranged. Alternatively, both nMOS transistors and pMOS transistors may be provided in the cut-off switch 330, the output-side short-circuit switch 360, and the input-side short-circuit switch 370, but only one of them may be provided. Furthermore, the fourth embodiment can also be applied to the fifth embodiment.

[0255] As described above, according to the fifth embodiment of this technology, since the input-side short-circuit switch 370 short-circuits the source and drain of the input transistor 312, the drain of the input transistor 312 can be prevented from being in a high-impedance state. Therefore, the degradation of the characteristics of the comparator 300 can be suppressed.

[0256] <6. Sixth Implementation Method>

[0257] In the third embodiment described above, the output transistor 317 inputs the comparison result CMP2 to the inverter 340. However, when the voltage range is narrow, there is a possibility of malfunction and leakage current in the inverter 340. The solid-state imaging element 200 of the sixth embodiment differs from the solid-state imaging element of the third embodiment in that a level offset circuit for extending the voltage range is added.

[0258] Figure 25 This is a circuit diagram illustrating a configuration example of the comparator 300 according to the sixth embodiment of the present technology. The comparator 300 of the sixth embodiment differs from the comparator of the third embodiment in that a level offset circuit 380 is further provided without the inverter 340.

[0259] The level offset circuit 380, based on the comparison result CMP2, will have a voltage greater than the input potential V. VSL and clamp potential V CLP Either of a pair of potentials (in other words, high level and low level) is output as an output signal to inverter 350. For example, the high level is set to be higher than the input potential V. VSL The power supply potential. A low level is, for example, set to the clamping potential V. CLP A low reference potential. Note the input potential V. VSL and clamp potential V CLP Examples of a pair of output potentials described in the claims. Power supply potential and reference potential indicate examples of a pair of offset potentials described in the claims.

[0260] By providing the level offset circuit 380, the voltage range on the input side of the inverter 350 can be expanded compared to the third embodiment. Due to the expanded voltage range, the difference between the lower or upper limit of this range and the threshold voltage of the inverter 350 becomes sufficiently large, preventing faults and leakage current in the inverter 350. Therefore, design constraints for preventing faults and leakage current in the inverter 350 are alleviated, and design freedom is increased. Note that the level offset circuit 380 expands the voltage range on both the power supply side and the ground side, but it is possible to expand the voltage range on only one side.

[0261] Furthermore, although both the cut-off switch 330 and the output-side short-circuit switch 360 are arranged, it is also possible to arrange only one of the cut-off switch 330 and the output-side short-circuit switch 360. Additionally, nMOS transistors and pMOS transistors may be respectively provided in the cut-off switch 330, the output-side short-circuit switch 360, and the input-side short-circuit switch 370, but it is also possible to provide only one of the nMOS transistors and pMOS transistors. Moreover, the fourth and fifth embodiments can also be applied to the sixth embodiment.

[0262] Figure 26 This is a circuit diagram showing a configuration example of the level offset circuit 380 according to the sixth embodiment of the present technology.

[0263] The level offset circuit 380 includes a precharge transistor 381, an nMOS transistor 382, ​​a pMOS transistor 384, and a precharge transistor 385. For example, a pMOS transistor is used as the precharge transistor 381. For example, an nMOS transistor is used as the precharge transistor 385.

[0264] The source of the precharge transistor 381 is connected to the power supply potential VDDB, and the control signal PreChg1 from the timing control unit 220 is input to its gate. The drain of the precharge transistor 381 is connected to the drain of the nMOS transistor 382. Here, the power supply potential VDDB is a different potential from the power supply potential VDDA of the pixel circuit 250 and the power supply potential VDDC of the inverter.

[0265] Furthermore, the gate of nMOS transistor 382 is connected to vertical signal line 259, and the comparison result CMP2 from output transistor 317 is input to the source of nMOS transistor 382. Additionally, the connection node between precharge transistor 381 and nMOS transistor 382 is connected to the gate of pMOS transistor 384, and the output signal nOUT is output from this connection node. The back gate and source of nMOS transistor 382 are short-circuited.

[0266] The source of pMOS transistor 384 is connected to the power supply potential VDDB, and the gate of pMOS transistor 384 is connected to the connection node between precharge transistor 381 and nMOS transistor 382. The output signal pOUT is output from the connection node between pMOS transistor 384 and precharge transistor 381. The drain of pMOS transistor 384 is connected to the drain of precharge transistor 385.

[0267] The source of the precharge transistor 385 is connected to the reference potential VSSB, and the control signal PreChg2 is input to the gate of the precharge transistor 385. Furthermore, the connection node between the pMOS transistor 384 and the precharge transistor 385 is connected to the inverter 350, and the output signal pOUT is output from the connection node between the pMOS transistor 384 and the precharge transistor 385.

[0268] Note that precharge transistor 381 is an example of the power supply-side precharge transistor described in the claims. nMOS transistor 382 is an example of the N-type transistor described in the claims. pMOS transistor 384 is an example of the P-type transistor described in the claims. Precharge transistor 385 is an example of the reference-side precharge transistor described in the claims.

[0269] The timing control unit 220 immediately turns on pre-charge transistors 381 and 385 using control signals PreChg1 and PreChg2 before the AD conversion period. Pre-charge transistor 381, in the on state, pre-charges parasitic capacitor 383 and initializes the drain of nMOS transistor 382 to the power supply potential VDDB. Furthermore, pre-charge transistor 385, in the on state, pre-charges parasitic capacitor 386 and initializes the drain of nMOS transistor 382 to the reference potential VSSB. During the AD conversion period, pre-charge transistors 381 and 385 are controlled to be cut off.

[0270] At the start of the A / D conversion, the comparison result CMP2 changes to the input potential V. VSL (High level). At this time, nMOS transistor 382 is turned off, and the power supply potential VDDB of the pre-charged parasitic capacitor 383 is output as the output signal nOUT. According to the output signal nOUT, pMOS transistor 384 is turned off, and the reference potential VSSB of the pre-charged parasitic capacitor 386 is output as the output signal pOUT.

[0271] Then, the comparison result CMP2 is inverted to the clamping potential V. CLP When the voltage is low, the nMOS transistor 382 transitions to the on state, and the potential of the output signal nOUT is inverted to the clamping potential V. CLP Then, based on the output signal nOUT, the pMOS transistor 384 transitions to the on state, and the potential of the output signal pOUT is inverted to the power supply potential VDDB.

[0272] Note that it can be configured so that pMOS transistor 384 and precharge transistor 385 are not provided. In this case, inverter 340 is added, and the output signal nOUT is output to inverter 340. Furthermore, the back gate of nMOS transistor 382 can be grounded.

[0273] Figure 27 This is a timing diagram illustrating an example of the operation of a solid-state imaging element 200 according to a sixth embodiment of the present technology.

[0274] The timing control unit 220 sets the control signal PreChg1 low and the control signal PreChg2 high during the period from timing T0 to the timing immediately following timing T1 (when a pulse period has elapsed since timing T1). Therefore, precharge transistors 381 and 385 perform precharge. Until after timing T5, the control signal PreChg1 is controlled high and the control signal PreChg2 is controlled low.

[0275] Furthermore, the timing control unit 220 sets the control signal PreChg1 low and the control signal PreChg2 high during the time period from time T5 to the pulse period, so that the precharge transistors 381 and 385 perform precharge. Until after timing T8, the control signal PreChg1 is controlled to be high and the control signal PreChg2 is controlled to be low.

[0276] During the auto-zeroing period from time T0 to time T1 in the diagram, the output of the second stage (comparison result CMP2) is the auto-zeroing potential V. AZ Therefore, when the output-side short-circuit switch 360 is open during auto-zeroing, a potential difference is generated between the gate and source of the nMOS transistor 382. There is a possibility that, due to this potential difference, the nMOS transistor 382 will turn on, and leakage current will flow from the power supply potential VDDB to the pre-charge transistor 381, the nMOS transistor 382, ​​and the current source 318. However, as shown, during auto-zeroing, the output-side short-circuit switch 360 is closed by the control signal XPAC2, thus turning off the nMOS transistor 382. As described above, by closing the output-side short-circuit switch 360 during the auto-zeroing period, leakage current is prevented in addition to suppressing oscillation.

[0277] As described above, according to the sixth embodiment of this technology, since the output of the level offset circuit 380 has a greater potential than the input potential V... VSL and clamp potential V CLP The voltage difference can be either one of a pair of potentials, thus expanding the voltage range on the input side of the inverter 350. Due to this expanded voltage range, the difference between the lower or upper limit of this range and the threshold of the inverter 350 becomes sufficiently large, preventing faults and leakage current in the inverter 350. Therefore, the design constraints on the supply voltage or threshold for preventing faults and leakage current are eased, and design freedom is increased.

[0278] <7. Seventh Implementation Method>

[0279] In the first embodiment described above, its level (reference potential V) is used. RMP The ramp signal gradually decreases during the AD conversion period, but a ramp signal with a gradually increasing level can also be used. The solid-state imaging element 200 of the seventh embodiment differs from the solid-state imaging element of the first embodiment in that it uses a ramp signal with a gradually increasing level.

[0280] Figure 28 This is a circuit diagram illustrating a configuration example of the comparator 300 according to the seventh embodiment of the present technology. The comparator 300 of the seventh embodiment differs from the comparator of the first embodiment in that an input-side short-circuit switch 370 is further provided without providing the cut-off switch 330 and the inverter 350.

[0281] The input-side short-circuit switch 370 opens and closes the path between the source (vertical signal line 259) and drain of the input transistor 312 according to the control signals PAC1 and XPAC1.

[0282] Furthermore, the input-side short-circuit switch 370 includes, for example, an nMOS transistor 371 and a pMOS transistor 372, which are connected in parallel between the source and drain of the input transistor 312. A control signal PAC1 is input to the gate of the nMOS transistor 371, and a control signal XPAC1 is input to the gate of the pMOS transistor 372.

[0283] Figure 29 This is a timing diagram illustrating an example of the operation of a solid-state imaging element 200 according to a seventh embodiment of the present technology.

[0284] During the automatic zeroing period from timing T0 to timing T1, DAC 230 will set the reference potential V. RMP Set to automatic zeroing potential V AZ Furthermore, the timing control unit 220 sets the control signal AZSW to a low level. Therefore, the comparison results CMP1 and CMP2 become the auto-zero potential V. AZ Furthermore, control signal PAC1 is controlled to a low level, and control signal XPAC1 is controlled to a high level. Consequently, the input-side short-circuit switch 370 is opened.

[0285] The timing control unit 220 sets the control signal AZSW to a high level during timing T1 to timing T8. Furthermore, during timing T1, the timing control unit 220 sets the control signal PAC1 to a high level and the control signal XPAC1 to a low level within a predetermined pulse period. This causes the input-side short-circuit switch 370 to close.

[0286] During the time period from timing T1 to timing T2, DAC 230 will reference potential V RMP The voltage is set below the auto-zero time. Therefore, input transistor 312 is turned on and operates at the reset level V. VSLH The comparison result CMP1 is output. During this period, the output transistor 317 is cut off, and the clamping potential V is output. CLPH The comparison result is CMP2. Furthermore, inverter 350 outputs a high-level output signal VCO.

[0287] Then, during the time period from timing T2 to timing T4, DAC 230 increases the reference potential V as time passes. RMP This period corresponds to the AD conversion period when the device is at the reset level. Assume the reference potential V... RMP and input potential V VSL The difference between them is less than the threshold voltage Vt of the input transistor 312 at timing T3 during that period. At this time, the input transistor 312 transitions to the cutoff state, and the comparison result CMP1 is inverted to the clamping potential V. CLPH The output transistor 317 transitions to the ON state, and the comparison result CMP2 is inverted to the reset level V. VSLH The output signal VCO is inverted to a low level.

[0288] At time T5, the timing control unit 220 sets the control signal PAC1 to a high level and the control signal XPAC1 to a low level within a predetermined pulse period. As a result, the input-side short-circuit switch 370 closes.

[0289] Furthermore, during the time period from timing T5 to timing T6, DAC 230 will reference potential V. RMP The voltage is set below the auto-zero time. Therefore, input transistor 312 is turned on and operates at signal level V. VSLL The comparison result CMP1 is output. During this period, the output transistor 317 is cut off, and the clamping potential V is output. CLPL The comparison result is CMP2. Furthermore, inverter 350 outputs a high-level output signal VCO.

[0290] Then, during the time period from timing T6 to timing T8, DAC 230 increases the reference potential V as time passes. RMP This period corresponds to the AD conversion period at the signal level. Assume a reference potential V. RMP and input potential V VSL The difference between them is less than the threshold voltage Vt of timing T7 during that period. At this time, the comparison result CMP1 is inverted to the clamping potential V. CLPL The comparison result CMP2 is inverted to signal level V. VSLLThe output signal VCO is inverted to a low level.

[0291] As shown in the figure, when using a ramp signal with a gradually increasing level, it is necessary to increase the speed at which the output of the first stage transitions to a high level. Therefore, an input-side short-circuit switch 370 is provided in the first stage. In this case, a cutoff switch 330 used to increase the speed of transition to a low level is unnecessary.

[0292] As described above, according to the seventh embodiment of this technology, since a ramp signal with gradually increasing level is used, the responsiveness can be improved by using the input-side short-circuit switch 370.

[0293] [First Variation]

[0294] In the seventh embodiment described above, an input-side short-circuit switch 370, comprising an nMOS transistor 371 and a pMOS transistor 372, is arranged in each column. However, in this structure, the number of transistors increases compared to the case where the input-side short-circuit switch 370 is implemented with a single transistor. The solid-state imaging element 200 according to the first variation of the seventh embodiment differs from the solid-state imaging element of the seventh embodiment in that it uses an input-side short-circuit switch 370 comprising only an nMOS transistor 371.

[0295] Figure 30 This is a circuit diagram illustrating a configuration example of a comparator 300 according to a first variation of the seventh embodiment of the present technology. The comparator 300 of the first variation of the seventh embodiment differs from the comparator of the first embodiment in that it includes an input-side short-circuit switch 370 comprising only an nMOS transistor 371. The waveform of the control signal PAC1 controlling the nMOS transistor 371 is the same as in the seventh embodiment.

[0296] As described above, according to the first variation of the seventh embodiment of the present technology, since an input-side short-circuit switch 370 consisting only of an nMOS transistor 371 is used, the number of transistors can be reduced compared to the case where a pair of transistors are used.

[0297] [Second variation]

[0298] In the seventh embodiment described above, an input-side short-circuit switch 370, comprising an nMOS transistor 371 and a pMOS transistor 372, is arranged in each column. However, in this structure, the number of transistors increases compared to the case where the input-side short-circuit switch 370 is implemented with a single transistor. The solid-state imaging element 200 of the second variation of the seventh embodiment differs from the solid-state imaging element of the first embodiment in that it uses an input-side short-circuit switch 370 comprising only a pMOS transistor 372.

[0299] Figure 31This is a circuit diagram illustrating a configuration example of a comparator 300 according to a second variation of the seventh embodiment of the present technology. The comparator 300 of the second variation according to the seventh embodiment differs from the comparator 300 of the seventh embodiment in that it includes an input-side short-circuit switch 370 comprising only a pMOS transistor 372. The waveform of the control signal XPAC1 used to control the pMOS transistor 372 is similar to that of the seventh embodiment.

[0300] As described above, in the second variation of the seventh embodiment of the present technology, since an input-side short-circuit switch 370 consisting only of a pMOS transistor 372 is used, the number of transistors can be reduced compared to the case where a pair of transistors are used.

[0301] [Third variation]

[0302] In the seventh embodiment described above, two transistors, an input transistor 312 and an output transistor 317, are provided. However, a third-stage transistor with the same configuration as the output transistor 317 can be added. The solid-state imaging element 200 of the third variation of the seventh embodiment differs from the solid-state imaging element of the seventh embodiment in that a third-stage transistor is added.

[0303] Figure 32 This is a block diagram illustrating a configuration example of a comparator 300 according to a third variation of the seventh embodiment of the present technology. The comparator 300 according to the third variation of the seventh embodiment includes a comparator circuit 310 and inverters 340 and 350.

[0304] Figure 33 This is a circuit diagram illustrating a configuration example of the comparator circuit 310 according to a third variation of the seventh embodiment of the present technology. The comparator circuit 310 includes, in its first stage, an input capacitor 311, an input transistor 312, an auto-zero transistor 313, an input-side short-circuit switch 370, a current source 314, a band-limiting capacitor 315, and a clamping transistor 316. Furthermore, in its second stage, the comparator circuit 310 includes an output transistor 317, a current source 318, and a clamping transistor 319. In its third stage, the comparator circuit 310 includes an output transistor 320, a current source 321, a clamping transistor 322, and an output-side short-circuit switch 360.

[0305] Figure 33 The circuit configuration of the first and second stages in the middle and in Figure 31 Those shown in the image are similar. Furthermore, Figure 33 The third-level circuit structure and Figure 23The structure of the output-side short-circuit switch 360 added to the third stage is the same. The output-side short-circuit switch 360 opens and closes the path between the source (vertical signal line 259) and drain of the output transistor 320 according to the control signal XPAC3. The waveform of the control signal XPAC3 is similar to that of the control signal XPAC1. Furthermore, the output-side short-circuit switch 360 can be implemented by any of the following: nMOS transistors only, pMOS transistors only, or both nMOS and pMOS transistors.

[0306] Note that the comparator circuit 310 has three stages, but it can have four or more stages. In this case, short-circuit switches can be provided in the odd-numbered stages.

[0307] As described above, according to the third variation of the seventh embodiment of this technology, since the output-side short-circuit switch 360 short-circuits the source and drain of the output transistor 317, the speed at which the comparison result CMP3 transitions to the source potential (high level) can be improved. Therefore, the responsiveness can be further improved.

[0308] [Fourth variation]

[0309] In the seventh embodiment described above, the comparison result CMP2 is input to the inverter 340. However, when the voltage range is narrow, there is a possibility of inverter 340 malfunctioning and leakage current. The solid-state imaging element 200 of the fourth variation of the seventh embodiment differs from the solid-state imaging element of the seventh embodiment in that a level offset circuit for extending the voltage range is added.

[0310] Figure 34 This is a block diagram illustrating a configuration example of the comparator 300 according to a fourth variation of the seventh embodiment of the present technology. The comparator 300 according to a third variation of the seventh embodiment includes a comparator circuit 310, a level offset circuit 380, and an inverter 340. The configuration of the comparator circuit 310 is similar to... Figure 33 The configuration shown is similar. The circuit configuration of the level offset circuit 380 is similar to that shown. Figure 26 Similar to what is shown.

[0311] Figure 35 This is a timing diagram illustrating an example of the operation of a solid-state imaging element 200 according to a fourth variation of the seventh embodiment of the present technology.

[0312] The waveforms of control signals AZSW and XPAC1 are similar to Figure 29 The waveforms shown are as follows. The timing control unit 220 sets the control signal XPAC3 low for a period of time immediately following timing T1, before the control signal XPAC1 is high. This causes the output-side short-circuit switch 360 to close.

[0313] The timing control unit 220 sets the control signal XPAC3 high at a timing point immediately following timing T1 when the control signal XPAC1 is high. This causes the output-side short-circuit switch 360 to open. Furthermore, at timing T5, the timing control unit 220 sets the control signal XPAC1 low for a predetermined pulse period.

[0314] The first-level comparison result shows the waveform of CMP1 and... Figure 29 The waveforms shown are similar. During the time period up to timing T3, the comparison result CMP2 of the second stage becomes the auto-zero potential V. AZ The waveform of CMP2, the comparison result after timer T3, is similar to... Figure 29 The waveform shown.

[0315] The waveforms of control signals PreChg1 and PreChg2 are similar to Figure 27 Similar to those shown. The waveform of the output signal VCO is similar to that in... Figure 29 The waveforms shown are similar.

[0316] As described above, according to the fourth variation of the seventh embodiment of this technology, since the output of the level offset circuit 380 has a greater potential than the input potential V... VSL and clamp potential V CLP The voltage range on the input side of the inverter 340 can be expanded by using either of the potential differences between the two potentials.

[0317] <8. Eighth Implementation>

[0318] In the third embodiment described above, the source and drain of the output transistor 317 are short-circuited by the output-side short-circuit switch 360. However, in this configuration, there is an input potential V. VSL The possibility of change during a period of stability. From Figure 21 The circuit of the third embodiment shown is configured with the clamping transistor 319 and inverters 340 and 350 removed as a comparative example.

[0319] Figure 36 This is a circuit diagram showing a configuration example of comparator 300 according to the comparison example. The parasitic capacitance of the output node of the first-stage comparison result CMP1 is set to 402, and the parasitic capacitance of the output node of the second-stage comparison result CMP2 is set to 403.

[0320] Figure 37 This is a timing diagram illustrating an example of the operation of the solid-state imaging element 200 according to a comparative example. First, during the auto-zeroing period from timing T0 to timing T1, the DAC 230 sets the reference potential V... RMP Set to neutral auto-zero potential V AZ After that, the reference potential VRMP The timing T1 rises once at the POF edge and then enters the reference potential V. RMP The P-phase ramp period gradually decreases. At the POF terminal, the reference potential V is maintained. RMP The reason for the one-step increase is to ensure that an inverted action is generated on the ramp side by reversing the direction. The count value is counted over a period of time until the output signal VCO of the pixel circuit 250 is inverted during the P-phase ramp time period when it is reset.

[0321] After that, the input potential V VSL As the amount of signal charge transmitted by the transmission transistor 252 decreases, the reference potential V... RMP The voltage rises once at the POF edge timing T5, and then enters the reference potential V. RMP The D-phase ramp period gradually decreases. The count is performed over a period of time until the output signal VCO, during signal charge transfer, is inverted within the D-phase ramp period. The net signal charge is obtained as a digital value by subtracting the count during the P-phase ramp period from the count during the D-phase ramp period in CDS processing. Note that in this diagram, the signal charge is zero, and the input potential V... VSL It does not decrease.

[0322] In the operation of this circuit, when the reference potential V RMP When the comparison result CMP1 of the first stage is increased at the POF or DOF edge, it begins to decrease and stops decreasing when the clamping transistor 316 transitions to the on state. In order to make the comparison result CMP1 of the first stage decrease earlier, the timing control unit 220 uses the control signal XPAC1 to set the cut-off switch 330 to be in the off state (on state) for a short period of time starting from timing T1 and timing T5.

[0323] On the other hand, the output-side short-circuit switch 360 of the second stage is at the reference potential V. RMP When the voltage reaches the auto-zero time, the circuit is switched on, and the comparison result CMP2 of the second stage is fixed as the input voltage V. VSL This is because the circuit oscillates according to the conditions under which the second-stage amplifier is activated in the neutral state.

[0324] In the circuit of this comparative example, there exists a potential (input potential V) of the vertical signal line 259, with the POF edge and DOF edge as the starting points. VSL The problem of potential change (recoil) occurring in the input. To address the input potential V caused by recoil. VSLAfter the deviation stabilizes and shifts to the ramp period, it is necessary to extend the stabilization period before the P-phase ramp and D-phase ramp periods (timing T1 to timing T2, and timing T5 to timing T6). This leads to an increase in AD conversion time, and consequently a decrease in frame rate and an increase in average power consumption. Furthermore, when the recoil stability is insufficient, the count values ​​within the P-phase ramp or D-phase ramp periods deviate due to stabilization errors, but due to mismatches between the P-phase and D-phase or between columns, a certain level of stabilization error cannot be removed in CDS processing. As a result, image quality degradation occurs, such as shifts or vertical stripes.

[0325] The reason for the recoil is as follows. First, when the potential of the first-stage comparison result CMP1 decreases due to the POF or DOF edge, the parasitic capacitor of the first stage ( Figure 36 Discharge occurs at 401). Since a portion of the current drawn by the first-stage current source 314 is used for discharge, the current drawn from the vertical signal line 259 decreases for a short period. At this time, a portion of the charge continuing to flow from the pixel side loses its destination and charges the parasitic capacitor of the vertical signal line 259, thus increasing the potential (V) of the vertical signal line 259. VSL A temporary rise (i.e., a rebound occurs).

[0326] Figure 38 This is a circuit diagram illustrating a configuration example of the comparator 300 according to an eighth embodiment of the present technology. To suppress backlash, a cutoff switch 410, a control switch 420, and a clamping transistor 430 are added in the eighth embodiment.

[0327] A cutoff switch 410 is inserted between the output transistor 317 and the current source 318. The cutoff switch 410 transitions to an open or closed state based on control signals XPAC2A and PAC2A from the timing control unit 220. The cutoff switch 410 includes, for example, an nMOS transistor 411 and a pMOS transistor 412 connected in parallel between the output transistor 317 and the current source 318. Control signal XPAC2A is input to the gate of nMOS transistor 411, and control signal PAC2A is input to the gate of pMOS transistor 412. Note that the cutoff switch 410 may include only one of the nMOS transistor 411 and pMOS transistor 412.

[0328] Clamping transistor 430 is P-type and has a gate and drain connected to current source 318 and a source connected to control switch 420. Control switch 420 is inserted between the source of output transistor 317 and the source of clamping transistor 430. Control switch 420 transitions to an off state or an on state according to control signal XPAC2. Furthermore, control switch 420 includes, for example, a pMOS transistor 422. Note that control switch 420 may include an nMOS transistor instead of pMOS transistor 422, or may include both nMOS transistor 422 and pMOS transistor.

[0329] It should be noted that cut-off switch 330 is an example of the first cut-off switch described in the claims, and cut-off switch 410 is an example of the second cut-off switch described in the claims. Current source 314 is an example of the first current source described in the claims, and current source 318 is an example of the second current source described in the claims.

[0330] Figure 39 This is a timing diagram illustrating an example of the operation of a solid-state imaging element 200 according to an eighth embodiment of the present technology. To suppress recoil, in the eighth embodiment, the comparison result CMP2 of the second stage is at a reference potential V. RMP The value decreases before the stable period. Furthermore, at the POF and DOF edges, the first-level comparison result CMP1 decreases, while the second-level comparison result CMP2 increases simultaneously.

[0331] Cut-off switch 410 and control switch 420 operate independently, such that either cut-off switch 410 or control switch 420 is turned on. Before a steady-state period (such as timer T1 to timer T2), control switch 420 is turned on, so current flows from the second-stage current source 318 to the second-stage clamping transistor 430. Then, the potential of the second-stage comparison result CMP2 changes from the input potential V. VSL The gate-source voltage of clamping transistor 430 is reduced. During the steady-state period and the subsequent ramp period, cut-off switch 410 is turned on, so current from the second-stage current source 318 flows to the input side of the second stage, and the potential of the second-stage comparison result CMP2 changes to the output of the inverting amplifier based on the first-stage comparison result CMP1. During the steady-state period, since the potential of the first-stage comparison result CMP1 decreases, the second-stage comparison result CMP1 increases.

[0332] Therefore, at the POF and DOF edges, the parasitic capacitor 401 of the first stage discharges, while the parasitic capacitor 402 of the second stage charges simultaneously, and these charging and discharging currents cancel each other out. This suppresses changes in the current drawn from the vertical signal line 259. Consequently, backlash can be suppressed. Since the potential at which the potential of the comparison result CMP2 of the second stage decreases can be adjusted by changing the size of the clamping transistor 430 of the second stage, the design can be optimized to maximize the cancellation effect.

[0333] By suppressing backlash, the settling time of the P-phase ramp signal and the D-phase ramp signal can be shortened. Therefore, the increase in AD conversion time can be avoided, and the decrease in frame rate and the increase in average power consumption can be suppressed.

[0334] Note that, as Figure 40 As shown, N-type clamping transistors 441 and 442 can be further added. Clamping transistor 441 is connected in parallel with P-type clamping transistor 316. Clamping transistor 442 is connected in parallel with control switch 420 and clamping transistor 430.

[0335] The clamping transistor 441 of the first stage is configured to prevent the drain potential of the current source 314 of the first stage from dropping excessively, and when the input potential V VSL The current value changes when the input exceeds the dynamic range. Similarly, the clamping transistor 442 of the second stage also serves to protect the current source 318 of the second stage, but the clamping transistor 442 is configured to lower the potential of the clamping transistor, and after the comparison result CMP2 of the second stage is inverted, the transistor of the current source 318 does not transition to the linear region.

[0336] As described above, according to the eighth embodiment of the present technology, recoil can be suppressed because of the addition of the cut-off switch 410, the control switch 420 and the clamping transistor 430.

[0337] [First Variation]

[0338] In the eighth embodiment described above, the output transistor 317 outputs the comparison result CMP2. However, when the voltage range is narrow, there is a possibility of malfunction and leakage current in the logic gates of subsequent stages (such as inverters). The solid-state imaging element 200 of the first variation of the eighth embodiment differs from the solid-state imaging element of the third embodiment in that a level offset circuit for expanding the voltage range is added.

[0339] Figure 41This is a circuit diagram illustrating a configuration example of the comparator 300 according to the first modification of the eighth embodiment of the present technology. The comparator 300 of the first modification of the eighth embodiment differs from the comparator of the eighth embodiment in that it further includes a level offset circuit 380 and a NAND gate 450. The circuit configuration of the level offset circuit 380 is similar to that in... Figure 26 The circuit shown is similar. The output signal pOUT of the NAND gate 450 output level offset circuit 380 and the NAND enable signal EN are used as the output signal VCO. Note that the NAND gate 450 is an example of the logic gate described in the claims of this disclosure.

[0340] However, in Figure 41 In this circuit, the node connected to the source of the third-stage nMOS transistor 382 is not the node of the comparison result CMP2 from the second stage, but rather the connection node between the control switch 420 and the clamping transistor 430. The output of this connection node is CMP2'. The reason for this connection is that when the source is connected to the node of the comparison result CMP2, the potential of the comparison result CMP2 decreases before the steady-state period of the ramp signal, and therefore... Figure 26 The potential difference between the gate and source of the nMOS transistor 382 in the middle expands and the nMOS transistor 382 turns on.

[0341] Because the stable period is Figure 26 The pre-charge transistor 381 of the third stage is shown to be on for a short period of time, thus causing a through current to flow in the third stage, which leads to a fault. By connecting the connection node between the control switch 420 and the clamping transistor 430 to the source of the nMOS transistor 382, ​​the nMOS transistor 382 of the third stage can be properly turned off before the stabilization period.

[0342] Note that N-type clamping transistors 441 and 442 can be further added.

[0343] Figure 42 This is a timing diagram illustrating an example of the operation of a solid-state imaging element according to a first variation of the eighth embodiment of the present technology. The thick, alternating long and short dashed lines in the diagram represent the changes in the output CMP2' of the connection node between the control switch 420 and the clamping transistor 430. The enable signal EN is controlled to be low (disabled) until the end of the settling period (timing T2 or timing T6), and is controlled to be high (enabled) from the end of the settling period to the end of the ramp period. As shown, recoil is suppressed.

[0344] As described above, according to the first variation of the eighth embodiment of this technology, since the output of the level offset circuit 380 has a greater potential than the input potential V... VSL and clamp potential V CLPIt can be either one of a pair of potentials with a potential difference, so the voltage range on the input side can be expanded.

[0345] [Second variation]

[0346] In the first variation of the eighth embodiment described above, an input capacitor 311 is inserted between the DAC 230 and the gate of the input transistor 312; however, with this configuration, noise cannot be sufficiently attenuated. The comparator 300 of the second variation of the eighth embodiment differs from the comparator of the first variation of the eighth embodiment in that an input capacitor switching circuit 470 is added.

[0347] Figure 43 This is a circuit diagram illustrating a configuration example of the comparator 300 in a second variation of the eighth embodiment of the present invention. The comparator 300 in the second variation of the eighth embodiment differs from the comparator in the first variation of the eighth embodiment in that it further includes a buffer 460 and an input capacitor switching circuit 470. The buffer 460 is inserted between the DAC 230 and the input capacitor switching circuit 470.

[0348] Figure 44 This is a circuit diagram illustrating a configuration example of an input capacitor switching circuit 470 according to a second variation of the eighth embodiment of the present technology. The input capacitor switching circuit 470 includes input capacitors 471 to 474 and switches 475 to 478.

[0349] One end of each of input capacitors 471 to 474 is connected to the gate of input transistor 312. The other end of input capacitor 471 is connected to the output terminal of buffer 460. Switch 475, under the control of timing control unit 220, opens and closes the path between the other ends of input capacitors 471 and 474. Switch 476, under the control of timing control unit 220, opens and closes the path between the other ends of input capacitors 472 and 473. Switch 477, under the control of timing control unit 220, opens and closes the path between the other ends of input capacitors 473 and 474. Switch 478, under the control of timing control unit 220, opens and closes the path between the other end of input capacitor 474 and ground potential.

[0350] The input capacitor switching circuit 470, as shown in the accompanying drawings, can switch the number of input capacitors connected in parallel to the gate of the input transistor 312 to any one of 1 to 4. This reduces noise in the ramp signal in the buffer 460 and noise on the column-shared ramp signal. In this case, it is desirable to increase the slope of the ramp signal by the attenuation caused by the capacitive voltage division.

[0351] Note that the number of input capacitors is not limited to four. When the number of input capacitors is M (M is an integer), M-1 switches are provided. Furthermore, an input capacitor switching circuit 470 can be added to... Figure 38 The circuit does not include a level offset circuit 380. Furthermore, N-type clamping transistors 441 and 442 can be added.

[0352] As described above, in the second variation of the eighth embodiment of the present technology, noise can be further reduced because an input capacitor switching circuit 470 is added.

[0353] <9. Examples of applications of moving objects>

[0354] The technology disclosed herein (the Technology) can be applied to a variety of products. For example, the Technology disclosed herein can be implemented as a device installed on any type of mobile body (such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, aircraft, drones, ships, or robots).

[0355] Figure 45 A block diagram illustrating a schematic configuration example of a vehicle control system is provided, which serves as an example of a mobile body control system to which the technology according to this disclosure can be applied.

[0356] The vehicle control system 12000 includes multiple electronic control units interconnected via a communication network 12001. Figure 45 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. Furthermore, as examples of the functional structure of the integrated control unit 12050, a microcomputer 12051, an audio / image output unit 12052, and an in-vehicle network interface (I / F) 12053 are shown.

[0357] The drive system control unit 12010 controls the operation of devices related to the vehicle's drive system according to various programs. For example, the drive system control unit 12010 is used as a control device for drive force generating devices (such as internal combustion engines, drive motors, etc.) that generate drive force for the vehicle, drive force transmission mechanisms that transmit drive force to the wheels, steering mechanisms that adjust the vehicle's steering angle, and braking devices that generate braking force for the vehicle.

[0358] The body system control unit 12020 controls the operation of various devices installed on the vehicle body according to various programs. For example, the body system control unit 12020 serves as a control device for keyless entry systems, smart key systems, power windows, or various lights such as headlights, taillights, brake lights, turn signals, fog lights, etc. In this case, radio waves or signals from various switches, which are alternatives to buttons, can be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals and controls the vehicle's door locks, power windows, lights, etc.

[0359] The exterior information detection unit 12030 detects exterior information, including information from outside the vehicle, which is part of the vehicle control system 12000. For example, an imaging unit 12031 is connected to the exterior information detection unit 12030. The exterior information detection unit 12030 causes the imaging unit 12031 to capture images of the exterior of the vehicle and receives these captured images. Furthermore, the exterior information detection unit 12030 can also perform processing based on the received images, such as detecting people, vehicles, obstacles, signs, text on the road surface, etc., or detecting their distances.

[0360] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 can output an electrical signal as an image, or it can output an electrical signal as information about the measured distance. Furthermore, the light received by the imaging unit 12031 can be visible light, or it can be invisible light such as infrared light.

[0361] The in-vehicle information detection unit 12040 detects information about the interior of the vehicle. The in-vehicle information detection unit 12040 is connected, for example, to a driver state detection unit 12041 that detects the driver's state. The driver state detection unit 12041 includes, for example, a camera that captures images of the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue level or concentration level, or determine whether the driver is dozing off.

[0362] The microcomputer 12051 can calculate target control values ​​for the drive force generation device, steering mechanism, or braking device based on information about the vehicle's interior or exterior obtained from the external information detection unit 12030 or the internal information detection unit 12040, and output control commands to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control designed to implement functions of an advanced driver assistance system (ADAS), including collision avoidance or shock absorption for the vehicle, following driving based on following distance, maintaining vehicle speed, collision warning, lane departure warning, etc.

[0363] In addition, the microcomputer 12051 controls the drive force generating device, steering mechanism, braking device, etc., based on information about the outside or inside of the vehicle obtained by the external information detection unit 12030 or the internal information detection unit 12040, and can perform cooperative control for autonomous driving, which enables the vehicle to drive automatically without relying on the driver's operation.

[0364] Additionally, the microcomputer 12051 can output control commands to the body system control unit 12020 based on the external information obtained by the external information detection unit 12030. For example, the microcomputer 12051 can control the headlights to switch from high beam to low beam based on the position of the vehicle in front or oncoming vehicle detected by the external information detection unit 12030, thereby performing cooperative control aimed at preventing glare.

[0365] The sound / image output unit 12052 sends an output signal of at least one of sound and image to an output device capable of visually or audibly notifying the vehicle occupants or the outside of the vehicle of information. Figure 45 In this example, audio speaker 12061, display unit 12062, and dashboard 12063 are shown as output devices. For example, display unit 12062 may include at least one of an on-board display and a head-up display.

[0366] Figure 46 This is an illustration of an example of the mounting position of the imaging unit 12031.

[0367] exist Figure 46 In this embodiment, imaging units 12101, 12102, 12103, 12104 and 12105 are provided as imaging units 12031.

[0368] Imaging units 12101, 12102, 12103, 12104, and 12105 are, for example, located on the front nose, side mirrors, rear bumper, and rear door of vehicle 12100, and on the upper part of the windshield inside the vehicle. Imaging unit 12101 located on the front nose inside the vehicle and imaging unit 12105 located on the upper part of the windshield primarily acquire images of the front of vehicle 12100. Imaging units 12102 and 12103 located on the side mirrors primarily acquire images of the sides of vehicle 12100. Imaging unit 12104 located on the rear bumper or rear door primarily acquires images of the rear of vehicle 12100. Imaging unit 12105 located on the upper part of the windshield inside the vehicle is primarily used to detect vehicles, pedestrians, obstacles, signals, traffic signs, lanes, etc., ahead.

[0369] It should be noted that Figure 46Examples of the imaging ranges of imaging units 12101 to 12104 are shown. Imaging range 12111 represents the imaging range of imaging unit 12101 installed at the front nose. Imaging ranges 12112 and 12113 represent the imaging ranges of imaging units 12102 and 12103 installed at the side mirrors, respectively. Imaging range 12114 represents the imaging range of imaging unit 12104 installed at the rear bumper or rear door. For example, a bird's-eye view of the vehicle 12100 viewed from above is obtained by overlaying image data captured by imaging units 12101 to 12104.

[0370] At least one of the imaging units 12101 to 12104 may have the function of obtaining distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of multiple imaging elements, or may be an imaging element having pixels for phase difference detection.

[0371] For example, the microcomputer 12051 can determine the distance to each three-dimensional object within the imaging range 12111 to 12114 and the time change of that distance (relative speed relative to the vehicle 12100) based on distance information obtained from the imaging units 12101 to 12104, and thereby extract the nearest three-dimensional object as the vehicle ahead. This nearest three-dimensional object specifically exists on the driving path of the vehicle 12100 and travels in substantially the same direction as the vehicle 12100 at a predetermined speed (e.g., equal to or greater than 0 km / h). Furthermore, the microcomputer 12051 can preset a following distance to stay ahead of the vehicle ahead and execute automatic braking control (including follow-stop control), automatic acceleration control (including follow-start control), etc. Thus, coordinated control for autonomous driving, enabling the vehicle to drive automatically without relying on driver operation, is possible.

[0372] For example, the microcomputer 12051 can classify three-dimensional object data related to three-dimensional objects into three-dimensional object data such as two-wheeled vehicles, standard vehicles, large vehicles, pedestrians, utility poles, and other three-dimensional objects based on distance information obtained from imaging units 12101 to 12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around vehicle 12100 as obstacles that the driver of vehicle 12100 can visually recognize and obstacles that the driver of vehicle 12100 cannot visually recognize. Then, the microcomputer 12051 determines a collision risk indicating the risk of collision with each obstacle. If the collision risk is equal to or higher than a set value and therefore there is a possibility of collision, the microcomputer 12051 outputs a warning to the driver via audio speaker 12061 or display unit 12062, and executes forced deceleration or evasive steering via driving system control unit 12010. The microcomputer 12051 can thereby assist driving to avoid collisions.

[0373] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared light. The microcomputer 12051 can identify a pedestrian, for example, by determining whether a pedestrian exists in the images captured by the imaging units 12101 to 12104. This pedestrian identification is performed, for example, by extracting feature points from the images captured by the imaging units 12101 to 12104, which are infrared cameras, and by performing pattern matching processing on a series of feature points representing the outline of an object to determine whether it is a pedestrian. When the microcomputer 12051 determines that a pedestrian exists in the images captured by the imaging units 12101 to 12104 and thus identifies the pedestrian, the sound / image output unit 12052 controls the display unit 12062 such that a square outline for emphasis is displayed superimposed on the identified pedestrian. The sound / image output unit 12052 can also control the display unit 12062 such that an icon representing the pedestrian is displayed at a desired location.

[0374] Examples of vehicle control systems to which the technology according to this disclosure can be applied have been described above. For example, the technology according to this disclosure can be applied to the imaging unit 12031 in the above configuration. Specifically, Figure 1 The imaging device 100 can be applied to the imaging unit 12031. By applying the technology according to this disclosure to the imaging unit 12031, the responsiveness of the comparator 300 can be improved, the frame rate can be increased, and moving images that are easier to view can be obtained. Therefore, driver fatigue can be reduced.

[0375] It should be noted that the above embodiments describe examples embodying the present technology, and the matters in the embodiments correspond to the matters specified in the claims. Similarly, the matters specified in the claims correspond to the matters in the embodiments of the present technology represented by the same names as the matters specifying the present invention. However, the present technology is not limited to the embodiments, and can be embodied by various modifications to the embodiments without departing from its spirit.

[0376] It should be noted that the effects described in this specification are merely illustrative and not limited, and other effects may be provided.

[0377] It should be noted that this technology may also have the following configurations.

[0378] (1) A solid-state imaging element, comprising:

[0379] The input transistor is configured to output a potential from the drain that ranges from one of a pair of output potentials to the other, based on whether the input potential from the source to the source and the predetermined reference potential from the gate are substantially consistent with each other.

[0380] The first current source is configured to supply a constant current;

[0381] A capacitor, said capacitor being inserted between the source of the input transistor and the first current source; and

[0382] A first cutoff switch is configured to disconnect the drain of the input transistor from the connection node during a predetermined period of time for initializing the connection node between the capacitor and the first current source to the lower of the output potential pair, and to connect the connection node to the drain of the input transistor outside the predetermined period of time.

[0383] (2) According to the solid-state imaging element described in (1),

[0384] The first cut-off switch includes an N-type transistor and a P-type transistor connected in parallel between the drain of the input transistor and the first current source.

[0385] (3) The solid-state imaging element according to (1),

[0386] The first disconnect switch includes an N-type transistor.

[0387] (4) The solid-state imaging element according to (1),

[0388] The first disconnect switch includes a P-type transistor.

[0389] (5) The solid-state imaging element according to any one of (1) to (4) further comprises:

[0390] A first output transistor is configured to output a potential from its drain in a range from a predetermined potential lower than the input potential to the input potential, based on whether the difference between the input potential from the input to the source and the potential of the connection node from the input to the gate exceeds a predetermined threshold voltage; and

[0391] An output-side short-circuit switch is configured to short-circuit the source and drain of the first output transistor during the predetermined time period.

[0392] (6) The solid-state imaging element according to (5) further includes an auto-zero transistor, the auto-zero transistor being configured to connect the gate and drain of the input transistor during an auto-zeroing period prior to the predetermined period.

[0393] The output-side short-circuit switch short-circuites the source and drain of the first output transistor during the automatic zeroing period and the predetermined period.

[0394] (7) The solid-state imaging element according to (5),

[0395] The output-side short-circuit switch includes an N-type transistor and a P-type transistor connected in parallel between the source and drain of the first output transistor.

[0396] (8) The solid-state imaging element according to (5),

[0397] The output-side short-circuit switch includes an N-type transistor.

[0398] (9) The solid-state imaging element according to any one of (5) to (8) further includes

[0399] The second output transistor is configured to output a voltage from the drain in the range from the predetermined potential to the input potential based on whether the difference between the input potential from the input to the source and the drain of the first output transistor from the input to the gate exceeds a predetermined threshold voltage.

[0400] (10) The solid-state imaging element according to any one of (5) to (9) further includes an input-side short-circuit switch configured to short-circuit the drain and source of the input transistor for a predetermined period of time.

[0401] (11) The solid-state imaging element according to any one of (5) to (10) further comprises:

[0402] A level offset circuit is configured to output a pair of offset potentials and an input potential with a potential difference greater than a predetermined potential, based on the drain potential of a first output transistor; and

[0403] A logic gate is configured to determine whether the output signal is above a predetermined threshold between the pair of offset potentials and output a determination result.

[0404] (12) The solid-state imaging element according to (11), wherein one of the pair of offset potentials is a power supply potential higher than the input potential, and the other of the pair of offset potentials is a reference potential lower than a predetermined potential, and

[0405] The level offset circuit includes:

[0406] An N-type transistor has its gate connected to a vertical signal line of the input potential and its source connected to the drain of the first output transistor.

[0407] A power supply-side precharge transistor is configured to initialize the drain potential of the N-type transistor to the power supply potential.

[0408] A P-type transistor, the P-type transistor having a gate connected to the drain of the N-type transistor and a drain connected to the logic gate; and

[0409] A reference-side precharge transistor is configured to initialize the drain potential of the P-type transistor to the reference potential.

[0410] (13) The solid-state imaging element according to (1) further comprises:

[0411] The first output transistor is configured to output a potential from the drain in a range from a predetermined potential lower than the input potential to the input potential, based on whether the difference between the input potential from the input to the source and the potential of the connection node from the input to the gate exceeds a predetermined threshold voltage.

[0412] The second current source is configured to supply a constant current.

[0413] The second cut-off switch is configured to disconnect the drain of the first output transistor from the second current source before the start timing when the reference potential is stable, and to connect the drain of the first output transistor to the second current source for a specific period of time from the start timing.

[0414] A clamping transistor, the drain of which is connected to the second current source; and

[0415] A control switch is configured to connect the source of the first output transistor to the source of the clamping transistor before the start timing begins, and to disconnect the source of the first output transistor from the source of the clamping transistor for a specific period of time starting from the start timing.

[0416] (14) The solid-state imaging element according to (13) further includes: a level offset circuit configured to output an output signal having a potential difference greater than a predetermined potential between an offset potential and an input potential based on the potential of the connection node between the control switch and the clamping transistor.

[0417] (15) The solid-state imaging element according to (13) or (14) further includes an input capacitor switching circuit configured to switch the number of input capacitors connected in parallel to the gate of the input transistor.

[0418] (16) A solid-state imaging element, comprising:

[0419] The input transistor is configured to output a drain potential corresponding to the input potential from the drain when the input potential input to the source and the predetermined reference potential input to the gate are substantially the same.

[0420] A first output transistor is configured to output a potential from its drain that is within a range from a predetermined potential to the input potential, based on whether the difference between the input potential (input to source) and the drain potential (input to gate) exceeds a predetermined threshold voltage; and

[0421] An output-side short-circuit switch is configured to short-circuit the source and drain of the first output transistor for a predetermined period of time for initializing the drain of the first output transistor to the input potential.

[0422] (17) A solid-state imaging element, comprising:

[0423] An input transistor is configured to output a predetermined clamping potential from its drain when the input potential input to the source and the predetermined reference potential input to the gate are substantially coincident; and

[0424] An input-side short-circuit switch is configured to short-circuit the source and drain of the input transistor for a predetermined period of time for initializing the drain potential to the input potential.

[0425] (18) An imaging device, comprising:

[0426] The input transistor is configured to output a potential from the drain that ranges from one of a pair of output potentials to the other, based on whether the input potential from the source to the source and the predetermined reference potential from the gate are substantially consistent with each other.

[0427] The current source is configured to supply a predetermined constant current;

[0428] A capacitor, which is inserted between the source of the input transistor and the current source;

[0429] A cut-off switch is configured to disconnect the drain of the input transistor from the connection node during a predetermined period of time for initializing the connection node between the capacitor and the current source to the lower of the output potential pair, and to connect the connection node to the drain of the input transistor outside the predetermined period of time; and

[0430] A counter is configured to count a value over a period of time until the potential of the connection node reverses.

[0431] (19) A solid-state imaging element, comprising:

[0432] Vertical signal lines connected to pixels;

[0433] A transistor, including a source connected to the vertical signal line and a gate for receiving a signal based on a predetermined reference potential;

[0434] The current source is configured to supply a constant current.

[0435] A capacitor is inserted between the source of a transistor and the current source; and

[0436] A switch is connected to the connection node between the capacitor and the source and drain of the transistor.

[0437] (20) A solid-state imaging element, comprising:

[0438] Vertical signal lines connected to pixels;

[0439] The first transistor includes a source connected to the vertical signal line and a gate for receiving a signal based on a predetermined reference potential;

[0440] The current source is configured to supply a constant current.

[0441] The second transistor includes a source connected to the vertical signal line and a gate connected to the current source; and

[0442] A switch is connected to the source and drain of the second transistor.

[0443] List of reference numerals

[0444] 100 Imaging Device

[0445] 110 optical units

[0446] 120 DSP circuit

[0447] 130 display units

[0448] 140 operating units

[0449] 150 bus

[0450] 160-frame memory

[0451] 170 storage units

[0452] 180 power supply unit

[0453] 200 solid-state imaging elements

[0454] 201 Optical Receiver Chip

[0455] 202 Circuit Chip

[0456] 210 Vertical Scanning Circuit

[0457] 220 Timing Control Unit

[0458] 230DAC

[0459] 240 pixel array unit

[0460] 250 pixel circuit

[0461] 251 Photoelectric conversion element

[0462] 252 Transmission Transistors

[0463] 253 Reset Transistor

[0464] 254 Floating Diffusion Layer

[0465] 255 Amplifying Transistor

[0466] 256 Select Transistors

[0467] 260 signal processing units

[0468] 261 Counter

[0469] 262 latch

[0470] 270 Horizontal Scanning Circuit

[0471] 300 comparator

[0472] 310 Comparator Circuit

[0473] Input capacitors 311, 471 to 474

[0474] 312 input transistor

[0475] 313 Automatic Zeroing Transistor

[0476] 314, 318, 321 current sources

[0477] 315 band-limited capacitor

[0478] Clamping transistors 316, 319, 322, 430, 441, 442

[0479] 317, 320 output transistors

[0480] 330, 410 Cut-off Switch

[0481] 331, 342, 352, 361, 371, 382, ​​411 nMOS transistors

[0482] 332, 341, 351, 362, 372, 384, 412, 422 pMOS transistors

[0483] 340, 350 inverters

[0484] 360° Output side short circuit switch

[0485] 370 Input-side short-circuit switch

[0486] 380-level offset circuit

[0487] 381, 385 precharge transistors

[0488] Parasitic capacitors 383, 386, 401, 402

[0489] 420 control switch

[0490] 450NAND gate

[0491] 460 buffer

[0492] 470 Input Capacitor Switching Circuit

[0493] Switches 475 to 478

[0494] 12031 Imaging Unit.

Claims

1. A solid-state imaging element, comprising: An input transistor is configured to output a potential from the drain that ranges from one of a pair of output potentials to the other, based on whether the input potential from the source to the source and the predetermined reference potential from the gate are substantially consistent with each other. The first current source is configured to supply a constant current; A capacitor, the capacitor being inserted between the source of the input transistor and the first current source; as well as A first shut-off switch is configured to disconnect the drain of the input transistor from the connection node during a predetermined period of time for initializing the connection node between the capacitor and the first current source to the lower of the pair of output potentials, and to connect the connection node to the drain of the input transistor outside the predetermined period of time.

2. The solid-state imaging element according to claim 1, in, The first cut-off switch includes an N-type transistor and a P-type transistor connected in parallel between the drain of the input transistor and the first current source.

3. The solid-state imaging element according to claim 1, in, The first cut-off switch includes an N-type transistor.

4. The solid-state imaging element according to claim 1, in, The first cut-off switch includes a P-type transistor.

5. The solid-state imaging element according to claim 1, further comprising: The first output transistor is configured to output a potential from the drain in a range from a predetermined potential lower than the input potential to the input potential, based on whether the difference between the input potential from the source and the potential of the connection node from the gate exceeds a predetermined threshold voltage. as well as An output-side short-circuit switch is configured to short-circuit the source and drain of the first output transistor during the predetermined time period.

6. The solid-state imaging element of claim 5, further comprising an auto-zero transistor configured to connect the gate and drain of the input transistor during an auto-zero period prior to the predetermined period. in, The output-side short-circuit switch short-circuites the source and drain of the first output transistor during the automatic zeroing period and the predetermined period.

7. The solid-state imaging element according to claim 5, in, The output-side short-circuit switch includes an N-type transistor and a P-type transistor connected in parallel between the source and drain of the first output transistor.

8. The solid-state imaging element according to claim 5, in, The output-side short-circuit switch includes an N-type transistor.

9. The solid-state imaging element according to claim 5, further comprising: The second output transistor is configured to output a voltage from its drain that is within the range from the predetermined potential to the input potential, based on whether the difference between the input potential from the input to the source and the drain of the first output transistor from the input to the gate exceeds a predetermined threshold voltage.

10. The solid-state imaging element according to claim 5, further comprising: An input-side short-circuit switch is configured to short-circuit the drain and source of the input transistor during the predetermined time period.

11. The solid-state imaging element according to claim 5, further comprising: A level offset circuit is configured to output a pair of offset potentials with a potential difference greater than the predetermined potential and the input potential, based on the potential of the drain of the first output transistor. as well as The logic gate is configured to determine whether the output signal is higher than a predetermined threshold between the pair of offset potentials and output the determination result.

12. The solid-state imaging element according to claim 11, wherein, One of the pair of offset potentials is a power supply potential higher than the input potential, and the other of the pair of offset potentials is a reference potential lower than the predetermined potential. The level offset circuit includes: An N-type transistor, wherein the gate of the N-type transistor is connected to the vertical signal line of the input potential, and the source of the N-type transistor is connected to the drain of the first output transistor; A power supply-side precharge transistor is configured to initialize the drain potential of the N-type transistor to the power supply potential. A P-type transistor, wherein the gate of the P-type transistor is connected to the drain of the N-type transistor, and the drain of the P-type transistor is connected to the logic gate; and A reference-side precharge transistor is configured to initialize the drain potential of the P-type transistor to the reference potential.

13. The solid-state imaging element according to claim 1, further comprising: The first output transistor is configured to output a potential from the drain in a range from a predetermined potential below the input potential to the input potential based on whether the difference between the input potential from the source and the potential of the connection node from the gate exceeds a predetermined threshold voltage. The second current source is configured to supply a constant current. The second cut-off switch is configured to disconnect the drain of the first output transistor from the second current source before the start timing when the reference potential is stable, and to connect the drain of the first output transistor to the second current source for a certain period of time from the start timing. A clamping transistor, the drain of which is connected to the second current source; as well as A control switch is configured to connect the source of the first output transistor to the source of the clamping transistor before the start timing begins, and to disconnect the source of the first output transistor from the source of the clamping transistor for a certain period of time from the start timing begins.

14. The solid-state imaging element according to claim 13, further comprising: The level offset circuit is configured to output an output signal having a pair of offset potentials with a potential difference greater than the predetermined potential and the input potential, based on the potential of the connection node between the control switch and the clamping transistor.

15. The solid-state imaging element according to claim 13, further comprising: An input capacitor switching circuit is configured to switch the number of input capacitors connected in parallel to the gate of the input transistor.

16. An imaging device, comprising: An input transistor is configured to output a potential from the drain that ranges from one of a pair of output potentials to the other, based on whether the input potential from the source to the source and the predetermined reference potential from the gate are substantially consistent with each other. The current source is configured to supply a predetermined constant current; A capacitor, which is inserted between the source of the input transistor and the current source; A cut-off switch is configured to disconnect the drain of the input transistor from the connection node during a predetermined period of time for initializing the connection node between the capacitor and the current source to the lower of the pair of output potentials, and to connect the connection node to the drain of the input transistor outside the predetermined period of time. as well as The counter is configured to count the value over a period of time until the potential of the connection node reverses.

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