Wafer test effectiveness control method and apparatus, computer device, and storage medium

Abstract

The application relates to a wafer test effectiveness control method and device, computer equipment and a storage medium. The method comprises the following steps: obtaining wafer test information obtained by performing wafer test on chips on a wafer; comparing the wafer test information with set test information corresponding to the wafer to obtain a comparison result; judging whether the wafer is dislocated during the wafer test according to the comparison result; and determining that test data of the wafer test is valid if the wafer is not dislocated during the wafer test. The wafer test dislocation can be found in time, and the detection accuracy is improved.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a method, apparatus, computer equipment, and storage medium for controlling the effectiveness of wafer testing. Background Technology

[0002] After wafer mass production, each chip on the wafer is typically tested. In subsequent packaging processes, valid chips are packaged based on the test results, while defective chips are discarded and not packaged. However, during the manufacturing process, external abnormalities such as personnel, equipment, and environment can introduce new problems, thus requiring the assurance of the effectiveness of wafer testing.

[0003] Traditional wafer testing effectiveness control methods mainly rely on test yield and test wafer images for judgment. However, they cannot rule out situations such as errors in test wafer image generation or retrieval during the testing process. As a result, abnormal chip mixes from wafer testing cannot be effectively screened, which will have a huge impact on quality and has the disadvantage of low detection accuracy. Summary of the Invention

[0004] Therefore, it is necessary to provide a wafer testing effectiveness control method, apparatus, computer equipment, and storage medium that can improve the accuracy of detection in response to the above problems.

[0005] A method for controlling the validity of wafer testing includes:

[0006] Obtain wafer test information obtained from wafer testing of chips on a wafer;

[0007] The wafer test information is compared with the set test information corresponding to the wafer to obtain the comparison result;

[0008] Based on the comparison results, determine whether misalignment occurred during the wafer testing process;

[0009] If no test misalignment occurs during the wafer testing process, the test data of the wafer test is determined to be valid.

[0010] In one embodiment, the wafer test information includes test results of wafer tests on chips at multiple specified locations, and the set test information includes target test results; determining whether misalignment occurred during wafer testing based on the comparison results includes:

[0011] If the comparison result shows that the test result is consistent with the target test result, then no test misalignment occurred during the wafer testing process.

[0012] If the comparison result shows that the test result is inconsistent with the target test result, then the wafer has been misaligned during the wafer testing process.

[0013] In one embodiment, the wafer test information includes test results of wafer tests of chips at multiple first specified locations, wherein the chips at the first specified locations are chips determined based on the location information of the experimental design chip; the target test result includes a first target test result, which is the test result determined by the experimental design chip through circuit design.

[0014] In one embodiment, the wafer test information includes test results of wafer tests for chips at multiple second specified locations, wherein the chips at the second specified locations are chips located at the sub-edge position of the wafer; the target test result includes a second target test result, wherein the second target test result is that the chips at the second specified locations have no entire rows or columns of failures.

[0015] In one embodiment, the test results are information characterizing whether the chip is effective or not.

[0016] In one embodiment, when the test result indicates chip failure, the test result is also used to indicate chip failure mode.

[0017] In one embodiment, the wafer testing information includes a wafer testing station diagram, and the set testing information includes a preset standard testing station diagram; determining whether misalignment occurred during wafer testing based on the comparison result includes:

[0018] If the comparison result shows that the test station information of the chip is inconsistent with the standard station information, then the wafer has been misaligned during the wafer testing process.

[0019] If the comparison result shows that the test station information of all chips is consistent with the standard station information, then no test misalignment occurred during the wafer testing process.

[0020] A wafer testing validity control device, comprising:

[0021] The information acquisition module is used to acquire wafer test information obtained from wafer testing of chips on the wafer;

[0022] The data comparison module is used to compare the wafer test information with the set test information corresponding to the wafer to obtain the comparison result;

[0023] The data analysis module is used to determine whether misalignment occurred during the wafer testing process based on the comparison results; if no misalignment occurred during the wafer testing process, the test data of the wafer test is determined to be valid.

[0024] A computer device includes a memory and a processor, the memory storing a computer program, the processor executing the computer program to implement the steps of the method described above.

[0025] A computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method described above.

[0026] The aforementioned wafer testing validity control method, apparatus, computer equipment, and storage medium acquire wafer testing information obtained from wafer testing of chips on a wafer, compare this wafer testing information with the corresponding set test information for the wafer, and obtain a comparison result. Based on the comparison result, it is determined whether misalignment occurred during the wafer testing process. If no misalignment occurred during the wafer testing process, the wafer testing data is determined to be valid. This allows for timely detection of wafer misalignment during testing, improving detection accuracy. Attached Figure Description

[0027] Figure 1 This is a flowchart of a wafer testing validity control method in one embodiment;

[0028] Figure 2 This is a flowchart in one embodiment for determining whether misalignment has occurred during wafer testing based on comparison results;

[0029] Figure 3 This is a flowchart in another embodiment for determining whether misalignment has occurred during wafer testing based on comparison results;

[0030] Figure 4 This is a structural block diagram of a wafer testing validity control device in one embodiment;

[0031] Figure 5 This is an internal structural diagram of a computer device in one embodiment. Detailed Implementation

[0032] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0033] In one embodiment, such as Figure 1 As shown, a wafer testing validity control method is provided, including:

[0034] Step S110: Obtain wafer test information obtained by performing wafer testing on the chips on the wafer.

[0035] The specific content of wafer testing for chips on a wafer is not unique; it can include electrical parameter testing and functional testing. After completing the wafer testing, the test results can be bound and stored with the chip identification information for subsequent traceability of chip information. That is, there is a correspondence between the chip identification information and the test results; the test results for the chip can be obtained through the chip identification information. The type of chip identification information is not unique and may include wafer batch number, wafer serial number, the chip's X / Y coordinates on the wafer, and the test date, etc.

[0036] Wafer test information refers to information related to the wafer testing of chips. Specifically, wafer test information can be the test results of chips at multiple specified locations on the wafer. These specified locations can be chips at the edge, sub-edge, or center positions on the wafer, with sub-edge chips referring to chips adjacent to the edge chips. Wafer test information can also be a wafer test station diagram during wafer testing, which includes test station information for each chip during wafer testing. It is understood that in other embodiments, wafer test information can be other types of information, and the specific settings can be tailored to the actual situation.

[0037] Step S120: Compare the wafer test information with the corresponding set test information of the wafer to obtain the comparison result.

[0038] It's understandable that the specific test information for a wafer will vary depending on the wafer test information. For example, if the wafer test information consists of test results for chips at multiple specified locations on the wafer, then the test information will be related to whether the chip at those specified locations is actually valid or not. If the wafer test information is a wafer test workstation diagram, then the test information will be a standard test workstation diagram, which includes standard workstation information for each chip. After obtaining the wafer test information from the chip's wafer testing, the wafer test information is compared with the corresponding specific test information to analyze whether they are consistent and obtain the comparison result.

[0039] Step S130: Determine whether misalignment occurred during wafer testing based on the comparison results.

[0040] After comparing the wafer test information with the corresponding set test information, the consistency between the two is used to determine whether misalignment occurred during the wafer testing process. It's understandable that the method for determining whether misalignment occurred during wafer testing will differ depending on the specific wafer test information and the set test information.

[0041] Step S140: If no test misalignment occurs during the wafer testing process, the test data of the wafer test is deemed valid.

[0042] If no misalignment occurs during wafer testing, the test data is considered valid, and a valid data message will be output to inform the operator that no misalignment occurred and the test data is valid. The operator can then use this valid test data to select the chips on the wafer for subsequent packaging processes.

[0043] Furthermore, if a wafer misalignment occurs during wafer testing, the test data will be unreliable and unusable. Additionally, an invalid data message can be output to inform the operator that a misalignment has occurred during wafer testing and the test data is invalid, allowing the operator to investigate the cause of the misalignment.

[0044] The aforementioned wafer testing validity control method involves acquiring wafer testing information obtained from testing the chips on the wafer, comparing this information with the corresponding pre-defined testing information, and obtaining a comparison result. Based on the comparison result, it is determined whether misalignment occurred during the wafer testing process. If no misalignment occurred, the wafer testing data is deemed valid. This method allows for timely detection of testing misalignment during wafer testing, preventing defective products from flowing into the next process and causing quality problems, thus improving testing accuracy.

[0045] In one embodiment, wafer test information includes test results of wafer tests on chips at multiple specified locations, and the test information includes target test results. The test results characterize whether a chip is valid or not; that is, the test results are used to indicate whether a chip is valid or not. If the test result of a chip indicates validity, then the chip is a valid chip, or a good chip. If the test result of a chip indicates failure, then the chip is a failed chip, or a defective chip. Specifically, the test results can be represented by Bin Code values; that is, Bin Code values ​​can be used to indicate whether the corresponding chip is valid or not. For example, when the test result of a chip is Bin 1, it indicates that the chip is a valid chip.

[0046] Furthermore, when the test result indicates chip failure, it is also used to indicate the chip failure mode. The specific types of chip failure modes are not unique and may include, but are not limited to, functional failure, leakage failure, power consumption failure, and open / short circuit failure (O / S failure). Again, using Bin Code values ​​to represent test results as an example, if a chip's test result is Bin 5, it indicates that the chip is a failed chip, and the failure mode is open / short circuit failure.

[0047] Correspondingly, in one embodiment, such as Figure 2 As shown, step S130 includes steps S132 and S134.

[0048] Step S132: If the comparison result is consistent with the target test result, then no test misalignment occurred during the wafer testing process.

[0049] Step S134: If the comparison result is inconsistent with the target test result, then the wafer has been misaligned during the wafer testing process.

[0050] Specifically, by comparing the test results of wafer tests at multiple specified locations with the corresponding target test results, if the comparison results are consistent, the wafer has not been misaligned during the wafer testing process; if the comparison results are inconsistent, the wafer has been misaligned during the wafer testing process.

[0051] It is understandable that the methods for determining multiple chips at specified locations may vary depending on actual needs. In one embodiment, wafer test information includes the test results of wafer tests for multiple chips at first specified locations, where the chips at the first specified locations are determined based on the location information of the experimentally designed chip; the target test results include first target test results, which are the test results of the experimentally designed chip determined through circuit design.

[0052] Specifically, multiple chips at various locations on a wafer are manufactured as experimental design chips, distinct from mass-produced design chips. The locations determined based on the positional information of these experimental design chips are designated as the first specified locations. By acquiring the wafer testing results of the chips at these first specified locations, the test results are compared with the first target test results. The comparison results determine whether test misalignment occurred during the wafer testing process. Specifically, the experimental design chips can be designed as either effective or ineffective. The test results of the wafer testing of the chips at these first specified locations are then compared with the actual results determined by the circuit design of the experimental design chips to determine whether test misalignment occurred during the wafer testing process.

[0053] After each wafer test, test data can be obtained. This data may include the chip's test results and its X / Y coordinates on the wafer, as well as the wafer batch number and wafer serial number. Additionally, a Golden Map file can be imported before or after each wafer test. This file contains information about a first specified location; that is, the Golden Map file allows you to obtain the X / Y coordinates of the chip on the wafer at that first specified location, and then retrieve the test results for that corresponding chip.

[0054] In this embodiment, the first target test result can be a failure result for the chip at the first specified location. Again, taking the chip test result represented by a Bin Code value as an example, for instance, a Bin Code value of Bin 6 indicates that the chip is an experimental design chip for determining test misalignment. The experimental design chip at the first specified location is designed so that the Bin Code value obtained during wafer testing is Bin 6. If no misalignment occurs during wafer testing, the test result obtained based on the first specified location should be the test result of the experimental design chip, i.e., it should be Bin 6; if a misalignment occurs, the test result obtained based on the first specified location is the test result of a mass-production design chip, and the Bin Code value is not Bin 6.

[0055] In this embodiment, by designing experimental design chips that are different from mass-produced design chips at multiple first designated locations on the wafer, the test results obtained based on the first designated locations are compared with the test results determined by the experimental design chips through circuit design, so as to accurately determine whether the wafer has misaligned during the wafer testing process.

[0056] In another embodiment, the wafer test information includes test results of wafer tests for chips at multiple second specified locations, wherein the chips at the second specified locations are chips at the sub-edge positions of the wafer; the target test result includes a second target test result, wherein the second target test result indicates that the chips at the second specified locations have no entire rows or columns of failures.

[0057] Specifically, because the edges of a wafer may contain incomplete or defective chips, these edge chips are typically considered faulty and therefore do not require testing. In other words, edge chips are not tested during wafer testing. However, chips located near the edges do require testing, and the likelihood of successful testing is generally higher, with a lower probability of entire rows or columns failing.

[0058] Based on this, by defining the secondary edge position as the second specified position, test results of wafer testing for chips at multiple second specified positions are obtained. These test results are compared with the second target test results to determine whether test misalignment occurred during wafer testing. The second target test result is that no entire row or column of chips at the second specified position fails. The specific failure type is not unique; it can be O / S failure or other failure types. Taking O / S failure as an example, if the test results indicate that an entire row or column of chips at the secondary edge position experiences O / S failure, then test misalignment is determined to have occurred; if no entire row or column of O / S failure occurs, then test misalignment is determined not to have occurred.

[0059] In this embodiment, by combining the test results of the wafer test of the chip at the next edge position of the wafer, it is possible to analyze whether there is a failure of an entire row or column of chips at the next edge position. No special design is required for the chips on the wafer, and it is possible to easily and accurately determine whether misalignment has occurred during the wafer test.

[0060] Furthermore, in one embodiment, the wafer testing information includes a wafer testing station diagram, and the test setting information includes a preset standard testing station diagram. For example... Figure 3 As shown, step S130 includes steps S136 and S138.

[0061] Step S136: If the comparison result shows that the test station information of the chip is inconsistent with the standard station information, then the wafer has been misaligned during the wafer testing process.

[0062] Step S136: If the comparison result shows that the test station information of all chips is consistent with the standard station information, then no test misalignment occurred during the wafer testing process.

[0063] Specifically, during wafer testing, the testing equipment moves according to a certain designed path. For example, if the wafer testing of chips on the wafer is performed according to an S-curve, that is, starting from the first row of chips to be tested, testing begins from left to right. After testing the first row, the second row is tested from right to left, and so on. Therefore, each chip has fixed test station information in each test. By combining the test station information of each chip, a wafer testing station diagram can be obtained.

[0064] Therefore, the wafer testing station diagram can be used to determine whether a wafer is misaligned during the wafer testing process. Specifically, the wafer testing station diagram is compared with the standard testing station diagram, and the comparison result is used to determine whether a wafer misalignment has occurred during the wafer testing process. If the testing station information of any chip is inconsistent with the standard station information, then a testing misalignment has occurred; if the testing station information of all tested chips is consistent with the standard station information, then no testing misalignment has occurred.

[0065] In this embodiment, by directly comparing the wafer test station diagram with the standard test station diagram, it is possible to quickly detect whether the wafer has experienced test misalignment.

[0066] It should be noted that the above provides three methods for determining whether misalignment has occurred during wafer testing in step S130 based on the comparison results: 1) Analyze the test results of the chip at the first specified position, specifically, obtain the first position information based on the golden map, and then check whether the test result of the chip at the first position is bin 6; 2) Analyze the test results of the chip at the second specified position, specifically checking whether the chip at the sub-edge position has an entire row or column of failure; 3) Analyze the wafer testing station diagram, specifically checking whether the testing station diagram is consistent with the preset standard testing station diagram. These three methods have different judgment objects and can be used as a reference for each other.

[0067] Specifically, considering that a single judgment method may err in some cases, for example, regarding judgment method 1), if there is an error in importing the golden map, the information obtained from the first specified position based on the golden map will also be incorrect. Another example is that, regarding judgment method 1), if the experimental design chip was removed during the golden map import and wafer testing was not performed on the experimental design chip, then bin 6 will be missing from the test results, making verification impossible. Yet another example is judgment method 2), where the wafer itself may indeed be of poor quality, resulting in entire rows or columns of chips failing at the sub-edge positions. Additionally, for example, the test station interface and the test probe card station interface may be misconnected, meaning there is a connection error in the test machine itself, causing errors in the obtained station information.

[0068] Given that a single judgment method may have a judgment error, in other embodiments, step S130 may also combine at least two of the above three judgment methods to perform misalignment analysis, and refer the judgment results of each judgment method to each other. When the judgment results are consistent, all of them are misaligned or none of them are misaligned, then the judgment result is valid.

[0069] In one implementation, taking misalignment analysis combining two judgment methods as an example, if both judgment methods result in no misalignment, the judgment result is valid, and a data validity prompt message is output to inform the operator that no misalignment occurred during wafer testing and the test data is valid; if both judgment methods result in misalignment, the judgment result is valid, and a data invalid prompt message is output to inform the operator that misalignment occurred during wafer testing and the test data is invalid; if one judgment method results in no misalignment and the other judgment method results in misalignment, corresponding prompt messages can be output, allowing the operator to further check whether misalignment has occurred and whether the two judgment methods have the aforementioned judgment errors.

[0070] In another implementation, taking misalignment analysis using a combination of three judgment methods as an example, if the judgment results of the three methods or two of them are all correct (no misalignment), the judgment result is valid, and a valid data message is output to inform the operator that no misalignment occurred during wafer testing and the test data is valid. If the judgment results of the three methods or two of them are both incorrect (misalignment), the judgment result is valid, and an invalid data message is output to inform the operator that a misalignment occurred during wafer testing and the test data is invalid. Furthermore, in cases where the judgment result of one method is inconsistent with the judgment results of the other two methods, the method with inconsistent output will display a judgment error message. The operator can then perform corresponding checks on the method with inconsistent output to obtain the specific reason for the judgment error.

[0071] It should be understood that although the steps in the flowcharts of the embodiments described above are shown sequentially according to the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowcharts of the embodiments described above may include multiple steps or multiple stages. These steps or stages are not necessarily completed at the same time, but can be executed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0072] Based on the same inventive concept, this application also provides a wafer testing validity control device for implementing the wafer testing validity control method described above. The solution provided by this device is similar to the implementation described in the above method; therefore, the specific limitations in one or more wafer testing validity control device embodiments provided below can be found in the limitations of the wafer testing validity control method described above, and will not be repeated here.

[0073] In one embodiment, such as Figure 4 As shown, a wafer testing validity control device is also provided, comprising: an information acquisition module 110, a data comparison module 120, and a data analysis module 130, wherein:

[0074] The information acquisition module 110 is used to acquire wafer test information obtained by performing wafer testing on the chips on the wafer.

[0075] The data comparison module 120 is used to compare the wafer test information with the corresponding set test information of the wafer to obtain the comparison result.

[0076] The data analysis module 130 is used to determine whether misalignment occurred during wafer testing based on the comparison results; if no misalignment occurred during wafer testing, the test data of wafer testing is determined to be valid.

[0077] In one embodiment, the data analysis module 130 is used to determine whether, if the comparison result is consistent with the target test result, the wafer has not experienced test misalignment during wafer testing; or if the comparison result is inconsistent with the target test result, the wafer has experienced test misalignment during wafer testing. The wafer test information includes test results for wafer testing of chips at multiple specified locations, and the test information includes the target test result.

[0078] In one embodiment, the wafer test information includes test results of wafer tests of chips at multiple first specified locations, wherein the chips at the first specified locations are chips determined based on the location information of the experimentally designed chips; the target test results include first target test results, which are test results of the experimentally designed chips determined through circuit design.

[0079] In one embodiment, the wafer test information includes test results of wafer tests for chips at multiple second specified locations, wherein the chips at the second specified locations are chips at the sub-edge positions of the wafer; the target test result includes a second target test result, wherein the second target test result indicates that the chips at the second specified locations have no failures in an entire row or column.

[0080] In one embodiment, the test result is information characterizing whether the chip is effective or not.

[0081] In one embodiment, when the test results indicate chip failure, the test results are also used to indicate the chip failure mode.

[0082] In one embodiment, the data analysis module 130 is used to determine whether a test misalignment has occurred during wafer testing if the comparison result shows that the test station information of a chip is inconsistent with the standard station information; and whether a test misalignment has occurred during wafer testing if the comparison result shows that the test station information of all chips is consistent with the standard station information. The wafer testing information includes a wafer testing station diagram, and the set test information includes a preset standard testing station diagram.

[0083] Each module in the aforementioned wafer testing validity control device can be implemented entirely or partially through software, hardware, or a combination thereof. These modules can be embedded in the processor of a computer device in hardware form or independent of it, or stored in the memory of a computer device in software form, so that the processor can call and execute the corresponding operations of each module.

[0084] In one embodiment, a computer device is provided, which may be a server, and its internal structure diagram may be as follows: Figure 5 As shown, this computer device includes a processor, memory, input / output interfaces (I / O), and a communication interface. The processor, memory, and I / O interfaces are connected via a system bus, and the communication interface is also connected to the system bus via the I / O interfaces. The processor provides computational and control capabilities. The memory includes non-volatile storage media and internal memory. The non-volatile storage media stores the operating system, computer programs, and a database. The internal memory provides the environment for the operation of the operating system and computer programs stored in the non-volatile storage media. The database stores data. The I / O interfaces are used for exchanging information between the processor and external devices. The communication interface is used for communicating with external terminals via a network connection. When the computer program is executed by the processor, it implements a wafer testing validity control method.

[0085] In one embodiment, a computer device is provided, including a memory and a processor. The memory stores a computer program, and the processor executes the computer program to perform the following steps: acquiring wafer test information obtained by performing wafer testing on chips on a wafer; comparing the wafer test information with the set test information corresponding to the wafer to obtain a comparison result; determining whether the wafer has misaligned during the wafer testing process based on the comparison result; and determining that the wafer test data is valid if no test misalignment has occurred during the wafer testing process.

[0086] In one embodiment, when the processor executes the computer program, it further implements the following steps: if the comparison result shows that the test result is consistent with the target test result, then no test misalignment occurred during the wafer testing process; if the comparison result shows that the test result is inconsistent with the target test result, then a test misalignment occurred during the wafer testing process. The wafer test information includes the test results of wafer tests on chips at multiple specified locations, and the test information includes the target test result.

[0087] In one embodiment, when the processor executes the computer program, it further performs the following steps: if the comparison result shows that the test station information of a chip is inconsistent with the standard station information, then a test misalignment has occurred during the wafer testing process; if the comparison result shows that the test station information of all chips is consistent with the standard station information, then no test misalignment has occurred during the wafer testing process. The wafer test information includes a wafer test station diagram, and the set test information includes a preset standard test station diagram.

[0088] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, it performs the following steps: acquiring wafer test information obtained by performing wafer testing on chips on a wafer; comparing the wafer test information with the set test information corresponding to the wafer to obtain a comparison result; determining whether the wafer has misaligned during the wafer testing process based on the comparison result; and determining that the wafer test data is valid if no test misalignment has occurred during the wafer testing process.

[0089] In one embodiment, when the computer program is executed by the processor, it further implements the following steps: if the comparison result shows that the test result is consistent with the target test result, then no test misalignment occurred during the wafer testing process; if the comparison result shows that the test result is inconsistent with the target test result, then a test misalignment occurred during the wafer testing process. The wafer test information includes the test results of wafer tests on chips at multiple specified locations, and the test information includes the target test result.

[0090] In one embodiment, when the computer program is executed by the processor, it further performs the following steps: if the comparison result shows that the test station information of a chip is inconsistent with the standard station information, then a test misalignment has occurred during the wafer testing process; if the comparison result shows that the test station information of all chips is consistent with the standard station information, then no test misalignment has occurred during the wafer testing process. The wafer test information includes a wafer test station diagram, and the set test information includes a preset standard test station diagram.

[0091] In one embodiment, a computer program product is provided, including a computer program that, when executed by a processor, performs the following steps: acquiring wafer test information obtained by performing wafer testing on chips on a wafer; comparing the wafer test information with the set test information corresponding to the wafer to obtain a comparison result; determining whether misalignment occurred during the wafer testing process based on the comparison result; and determining that the wafer test data is valid if no test misalignment occurred during the wafer testing process.

[0092] In one embodiment, when the computer program is executed by the processor, it further implements the following steps: if the comparison result shows that the test result is consistent with the target test result, then no test misalignment occurred during the wafer testing process; if the comparison result shows that the test result is inconsistent with the target test result, then a test misalignment occurred during the wafer testing process. The wafer test information includes the test results of wafer tests on chips at multiple specified locations, and the test information includes the target test result.

[0093] In one embodiment, when the computer program is executed by the processor, it further performs the following steps: if the comparison result shows that the test station information of a chip is inconsistent with the standard station information, then a test misalignment has occurred during the wafer testing process; if the comparison result shows that the test station information of all chips is consistent with the standard station information, then no test misalignment has occurred during the wafer testing process. The wafer test information includes a wafer test station diagram, and the set test information includes a preset standard test station diagram.

[0094] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Any references to memory, databases, or other media used in the embodiments provided in this application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. By way of illustration and not limitation, RAM can take many forms, such as Static Random Access Memory (SRAM) or Dynamic Random Access Memory (DRAM). The databases involved in the embodiments provided in this application may include at least one type of relational database and non-relational database. Non-relational databases may include, but are not limited to, blockchain-based distributed databases. The processors involved in the embodiments provided in this application may be general-purpose processors, central processing units, graphics processing units, digital signal processors, programmable logic devices, quantum computing-based data processing logic devices, etc., and are not limited to these.

[0095] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0096] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for controlling the effectiveness of wafer testing, characterized in that, include: Obtain wafer test information obtained from wafer testing of chips on a wafer; The wafer test information is compared with the set test information corresponding to the wafer to obtain a comparison result; the wafer test information includes the test results of wafer tests of chips at multiple specified locations, and the set test information includes the target test result; Based on the comparison results, determine whether misalignment occurred during the wafer testing process; If no test misalignment occurs during the wafer testing process, the test data of the wafer test is determined to be valid. The wafer test information includes test results of wafer tests for multiple chips at second specified locations. The chips at the second specified locations are chips at the sub-edge positions of the wafer, that is, chips on the wafer that are adjacent to the edge position chips. The target test results include second target test results, which indicate that the chips at the second specified locations have no entire rows or columns of failures.

2. The method according to claim 1, characterized in that, The step of determining whether misalignment occurred during wafer testing based on the comparison result includes: If the comparison result shows that the test result is consistent with the target test result, then no test misalignment occurred during the wafer testing process. If the comparison result shows that the test result is inconsistent with the target test result, then the wafer has been misaligned during the wafer testing process.

3. The method according to claim 2, characterized in that, The wafer test information includes test results of wafer tests for multiple chips at first specified locations, wherein the chips at the first specified locations are determined based on the location information of the experimentally designed chips; the target test results include first target test results, which are test results determined by the experimentally designed chips through circuit design.

4. The method according to claim 2, characterized in that, The test results provide information indicating whether the chip is effective or not.

5. The method according to claim 4, characterized in that, When the test results indicate chip failure, the test results are also used to indicate the chip failure mode.

6. The method according to claim 1, characterized in that, The wafer testing information includes a wafer testing station diagram, and the set testing information includes a preset standard testing station diagram; determining whether misalignment occurred during wafer testing based on the comparison result includes: If the comparison result shows that the test station information of the chip is inconsistent with the standard station information, then the wafer has been misaligned during the wafer testing process. If the comparison result shows that the test station information of all chips is consistent with the standard station information, then no test misalignment occurred during the wafer testing process.

7. A wafer testing validity control device, characterized in that, include: The information acquisition module is used to acquire wafer test information obtained from wafer testing of chips on the wafer; The data comparison module is used to compare the wafer test information with the set test information corresponding to the wafer to obtain a comparison result; the wafer test information includes the test results of wafer tests of chips at multiple specified locations, and the set test information includes the target test result; The data analysis module is used to determine whether misalignment occurred during wafer testing based on the comparison results. If no test misalignment occurs during the wafer testing process, the test data of the wafer test is determined to be valid. The wafer test information includes test results of wafer tests for multiple chips at second specified locations. The chips at the second specified locations are chips at the sub-edge positions of the wafer, that is, chips on the wafer that are adjacent to the edge position chips. The target test results include second target test results, which indicate that the chips at the second specified locations have no entire rows or columns of failures.

8. A computer device comprising a memory and a processor, wherein the memory stores a computer program, characterized in that, When the processor executes the computer program, it implements the steps of the method according to any one of claims 1 to 6.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1 to 6.

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