A memory and an electronic device

Abstract

This application discloses a memory and an electronic device for improving the computational capacity of the memory. An embodiment of this application provides a memory comprising multiple memory cells, each memory cell including: a substrate, a memory circuit and a transmission circuit located on one side of the substrate; the transmission circuit is electrically connected to the memory circuit; the memory circuit is used to store data; the transmission circuit is used to write data to or read data from the memory circuit; the transmission circuit and the memory circuit are stacked; the orthographic projection of the transmission circuit on the substrate overlaps with the orthographic projection of the memory circuit on the substrate.

Description

Technical Field

[0001] This application relates to the field of memory technology, and more particularly to a memory and electronic device. Background Technology

[0002] Currently, the in-memory computing circuitry of in-memory computing chips typically consists of multiple transistors. Silicon-based transistors have high mobility and can achieve nanometer-level aspect ratios. Most in-memory computing chips use silicon as a substrate, thus achieving the goal of small area, large number of computing units, and high computational power. However, to expand the application scenarios of in-memory computing chips and reduce costs, flexible in-memory computing chips are the best choice.

[0003] To realize flexible products with in-memory computing chips, in-memory computing circuits can be fabricated on flexible substrates. However, due to the limitations of flexible substrates, compared to fabricating transistors on silicon substrates, transistors fabricated on flexible substrates have a larger aspect ratio, meaning the area of ​​the in-memory computing circuits increases. Without changing the chip size, this results in a reduction in the number of in-memory computing circuits included in the chip, leading to a reduction in the chip's computing power. Summary of the Invention

[0004] This application provides a memory and an electronic device to improve the computing power of the memory.

[0005] This application provides a memory that includes multiple memory cells. Each memory cell includes a substrate, a memory circuit, and a transmission circuit located on one side of the substrate. The transmission circuit is electrically connected to the memory circuit.

[0006] The storage circuit is used to store data; the transmission circuit is used to write data to the storage circuit or read data from the storage circuit.

[0007] The transmission circuit and storage circuit are stacked together;

[0008] The orthographic projection of the transmission circuit onto the substrate overlaps with the orthographic projection of the storage circuit onto the substrate.

[0009] In some embodiments, the storage circuit includes a first inverter and a second inverter, and the transmission circuit includes a first transistor and a second transistor;

[0010] The orthogonal projection of the first transistor onto the substrate lies within the orthogonal projection of the first inverter onto the substrate.

[0011] The orthogonal projection of the second transistor onto the substrate lies within the orthogonal projection of the second inverter onto the substrate.

[0012] In some embodiments, the first inverter includes a third transistor and a fourth transistor; the second inverter includes a fifth transistor and a sixth transistor.

[0013] The gate of the third transistor is electrically connected to the gate of the fourth transistor, and the drain of the third transistor is electrically connected to the source of the fourth transistor; the gate of the fifth transistor is electrically connected to the gate of the sixth transistor, and the drain of the fifth transistor is electrically connected to the source of the sixth transistor; the source of the third transistor is electrically connected to the source of the fifth transistor, and the drain of the fourth transistor is electrically connected to the drain of the sixth transistor.

[0014] The drain of the first transistor is electrically connected to the drain of the third transistor, the source of the fourth transistor, the gate of the fifth transistor, and the gate of the sixth transistor.

[0015] The drain of the second transistor is electrically connected to the drain of the fifth transistor, the source of the sixth transistor, the gate of the third transistor, and the gate of the fourth transistor.

[0016] The orthographic projection of the first transistor onto the substrate lies within the orthographic projection of the third transistor onto the substrate.

[0017] The orthographic projection of the second transistor onto the substrate lies within the orthographic projection of the fifth transistor onto the substrate.

[0018] In some embodiments, the first transistor is located on the side of the third transistor whose gate is away from the substrate; the orthographic projection of the first transistor onto the substrate is located in the region between the orthographic projections of the source and drain of the third transistor onto the substrate.

[0019] The second transistor is located on the side of the fifth transistor whose gate is away from the substrate; the orthographic projection of the second transistor onto the substrate is located in the region between the orthographic projections of the source and drain of the fifth transistor onto the substrate.

[0020] In some embodiments, the source and drain of the first transistor are disposed on the same layer as the source and drain of the third transistor.

[0021] The source and drain of the second transistor are arranged on the same layer as the source and drain of the fifth transistor.

[0022] In some embodiments, the source and drain of the first transistor are disposed on the same layer as the source and drain of the second transistor, the gate of the first transistor is disposed on the same layer as the gate of the second transistor, and the active layer of the first transistor is disposed on the same layer as the active layer of the second transistor.

[0023] The source and drain of the third transistor, the source and drain of the fourth transistor, the source and drain of the fifth transistor, and the source and drain of the sixth transistor are arranged in the same layer. The gates of the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor are arranged in the same layer. The active layers of the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor are arranged in the same layer.

[0024] In some embodiments, the material of the active layer of the first transistor and the material of the active layer of the second transistor include oxide semiconductors.

[0025] The active layer materials of the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor include low-temperature polycrystalline silicon.

[0026] In some embodiments, the memory unit further includes: a first light-shielding portion and a second light-shielding portion;

[0027] The first light-shielding part is located between the active layer of the first transistor and the gate of the third transistor, and the orthographic projection of the active layer of the first transistor onto the substrate falls into the orthographic projection of the first light-shielding part onto the substrate.

[0028] The second light-shielding part is located between the active layer of the second transistor and the gate of the fifth transistor, and the orthographic projection of the active layer of the second transistor onto the substrate falls within the orthographic projection of the second light-shielding part onto the substrate.

[0029] In some embodiments, the materials of the active layers of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor include low-temperature polycrystalline silicon.

[0030] In some embodiments, a buffer layer is further included between the active layer of the first transistor and the active layer of the third transistor, and the thickness of the buffer layer is greater than 1 micrometer.

[0031] In some embodiments, the transmission circuit further includes: a word line, a first bit line, and a second bit line;

[0032] The gates of the first transistor and the second transistor are electrically connected to the word line, the source of the first transistor is electrically connected to the first bit line, and the source of the second transistor is electrically connected to the second bit line.

[0033] The storage circuit also includes: a low-level signal line and a high-level signal line; the low-level signal line is electrically connected to the drain of the fourth transistor and the drain of the sixth transistor, and the high-level signal line is electrically connected to the source of the third transistor and the source of the fifth transistor.

[0034] In some embodiments, the word line is disposed on the same layer as the gate of the first transistor and the gate of the second transistor;

[0035] The first bit line is located on the side of the source and drain of the first transistor that is away from the substrate, and the second bit line is located on the side of the source and drain of the second transistor that is away from the substrate.

[0036] The low-level signal line is on the same layer as the drain of the fourth transistor and the drain of the sixth transistor, and the high-level signal line is on the same layer as the source of the third transistor and the source of the fifth transistor.

[0037] In some embodiments, the first transistor, the second transistor, the fourth transistor, and the sixth transistor are N-type transistors, and the third transistor and the fifth transistor are P-type transistors.

[0038] An electronic device provided in this application includes a memory provided in this application.

[0039] The memory and electronic device provided in this application embodiment, since the transmission circuit and storage circuit included in each memory unit are stacked, can reduce the overall area occupied by the memory unit compared to the case where the transmission circuit and storage circuit are arranged on the same layer. Without changing the size of the memory, the number of memory units can be increased, thereby improving the storage and computing power of the memory. Attached Figure Description

[0040] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 A schematic diagram of the structure of a memory provided in an embodiment of this application;

[0042] Figure 2 A timing diagram of a memory provided for an embodiment of this application;

[0043] Figure 3 This is a schematic diagram of another memory structure provided in an embodiment of this application;

[0044] Figure 4 This is a schematic diagram of another memory structure provided in an embodiment of this application. Detailed Implementation

[0045] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Furthermore, the embodiments and features in the embodiments of this application can be combined with each other without conflict. All other embodiments obtained by those skilled in the art based on the described embodiments of this application without creative effort are within the scope of protection of this application.

[0046] Unless otherwise defined, the technical or scientific terms used in this application shall have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms "first," "second," and similar terms used in this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect.

[0047] It should be noted that the dimensions and shapes of the figures in the accompanying drawings do not reflect actual proportions and are intended only to illustrate the content of this application. Furthermore, the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout.

[0048] This application provides a memory, such as Figure 1 As shown, the memory includes multiple memory cells 10. Each memory cell 10 includes: a substrate 1, a memory circuit 2 and a transmission circuit 3 located on one side of the substrate 1; the transmission circuit 3 is electrically connected to the memory circuit 2.

[0049] Storage circuit 2 is used to store data; transmission circuit 3 is used to write data to storage circuit 2 or read data from storage circuit 2.

[0050] The transmission circuit 3 and the storage circuit 2 are stacked together;

[0051] The orthographic projection of the transmission circuit 3 onto the substrate 1 overlaps with the orthographic projection of the storage circuit 2 onto the substrate 1.

[0052] The memory provided in this application embodiment, since the transmission circuit and storage circuit included in each storage unit are stacked, can reduce the overall area occupied by the storage unit compared to the case where the transmission circuit and storage circuit are arranged on the same layer. Without changing the size of the memory, the number of storage units can be increased, thereby improving the storage and computing capacity of the memory.

[0053] It should be noted that, Figure 1 Only one storage unit 10 is shown in the diagram. In actual implementation, the number of storage units included in the memory can be set according to actual needs.

[0054] In specific implementation, the memory provided in this application embodiment is static random-access memory (SRAM).

[0055] In some embodiments, such as Figure 1 As shown, the storage circuit 2 includes a first inverter 201 and a second inverter 202, and the transmission circuit 3 includes a first transistor T1 and a second transistor T2.

[0056] The orthogonal projection of the first transistor T1 onto the substrate 1 is located within the orthogonal projection of the first inverter 201 onto the substrate 1.

[0057] The orthogonal projection of the second transistor T2 onto the substrate 1 lies within the orthogonal projection of the second inverter 202 onto the substrate 1.

[0058] The first inverter 201 and the second inverter 202 together form a latch.

[0059] In some embodiments, such as Figure 1 As shown, the first inverter 201 includes a third transistor T3 and a fourth transistor T4; the second inverter 202 includes a fifth transistor T5 and a sixth transistor T6.

[0060] The gate of the third transistor T3 is electrically connected to the gate of the fourth transistor T4, and the drain of the third transistor T3 is electrically connected to the source of the fourth transistor T4; the gate of the fifth transistor T5 is electrically connected to the gate of the sixth transistor T6, and the drain of the fifth transistor T5 is electrically connected to the source of the sixth transistor T6; the source of the third transistor T3 is electrically connected to the source of the fifth transistor T5, and the drain of the fourth transistor T4 is electrically connected to the drain of the sixth transistor T6.

[0061] The drain of the first transistor T1 is electrically connected to the drain of the third transistor T3, the source of the fourth transistor T4, the gate of the fifth transistor T5, and the gate of the sixth transistor T6.

[0062] The drain of the second transistor T2 is electrically connected to the drain of the fifth transistor T5, the source of the sixth transistor T6, the gate of the third transistor T3, and the gate of the fourth transistor T4.

[0063] In some embodiments, such as Figure 1 As shown, the transmission circuit 3 also includes: word line WL, first bit line BL, and second bit line BLB;

[0064] The gate G of the first transistor T1 and the gate G of the second transistor T2 are electrically connected to the word line WL. The source S of the first transistor T1 is electrically connected to the first bit line BL, and the source S of the second transistor T2 is electrically connected to the second bit line BLB.

[0065] The storage circuit 2 also includes: a low-level signal line VSS and a high-level signal line VDD; the low-level signal line VSS is electrically connected to the drain D of the fourth transistor T4 and the drain D of the sixth transistor T6, and the high-level signal line VDD is electrically connected to the source S of the third transistor T3 and the source S of the fifth transistor.

[0066] In some embodiments, such as Figure 1 As shown, the first transistor T1, the second transistor T2, the fourth transistor T4 and the sixth transistor T6 are N-type transistors, and the third transistor T3 and the fifth transistor T5 are P-type transistors.

[0067] The working principle of the SRAM storage unit provided in the embodiments of this application will be illustrated by example below. Figure 1 For example, SRAM storage cells are latched by connecting the first inverter 201 and the second inverter 202 end to end. Figure 1 The Q node and QB node are storage nodes. Their high and low voltage levels are always opposite, and they are connected to two bit lines BL / BLB respectively through two N-type transistors, the first transistor T1 and the second transistor T2. The voltage levels of the first bit line BL and the second bit line BLB are always opposite. The conduction of the first transistor T1 and the second transistor T2 is controlled by the voltage on the word line WL. Figure 1 The timing diagram of the SRAM memory cell shown is as follows: Figure 2 As shown. When writing "1", the levels of the first bit line BL and the second bit line BLB are "1" and "0" respectively, and the level of the word line WL is 1. The first transistor T1 and the second transistor T2 are both turned on, sending the signals on the first bit line BL and the second bit line BLB to the Q node and QB node respectively, so that Q=1 and QB=0. In this way, the data "1" is latched in the latch composed of the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6. The process of writing data "0" is similar. Taking reading "1" as an example, the first bit line BL and the second bit line BLB are pre-charged. After the pre-charging is completed, since the storage cell stores "1", WL=1, Q=1, QB=0. The first transistor T1 and the second transistor T2 are turned on, causing the potential of the second bit line BLB to drop. A voltage difference is generated between the potential of the first bit line BL and the second bit line BLB. The second bit line BLB becomes low, while the first bit line BL remains high, and "1" is read.

[0068] In some embodiments, the substrate is, for example, a flexible substrate.

[0069] In a practical implementation, the flexible substrate material is, for example, polyimide. The first transistor, second transistor, third transistor, fourth transistor, fifth transistor, and sixth transistor are thin-film transistors.

[0070] The memory provided in this application uses a flexible substrate instead of the silicon-based substrate in related technologies, making it suitable for high-performance flexible product applications such as cloud computing and edge computing. Furthermore, the fabrication of thin-film transistors on the flexible substrate in this application reduces processing costs compared to the fabrication of metal-oxide-semiconductor field-effect transistors on silicon-based substrates in related technologies. The combination of a flexible substrate and thin-film transistors allows electronic products including the memory provided in this application to have novel forms (e.g., flexible and bendable) and low costs, which is unattainable with traditional silicon-based substrate memories. Therefore, it greatly expands the potential application range of the memory. For example, the memory provided in this application can be used in wearable product chips, intelligent chips for everyday consumer products, and other similar applications.

[0071] It should be noted that transistors fabricated on flexible substrates have a larger width and length, meaning that the transistors included in the storage circuit are larger in size.

[0072] In a specific implementation, the orthogonal projection of the first transistor onto the substrate is located within the orthogonal projection of the third or fourth transistor onto the substrate; the orthogonal projection of the second transistor onto the substrate is located within the orthogonal projection of the fifth or sixth transistor onto the substrate.

[0073] The memory provided in this application embodiment has a first transistor whose orthogonal projection on the substrate is located within the orthogonal projection of the third or fourth transistor on the substrate; and a second transistor whose orthogonal projection on the substrate is located within the orthogonal projection of the fifth or sixth transistor on the substrate. This avoids increasing the area occupied by the memory cells when the transistors included in the memory circuit are large, and is beneficial to increasing the number of memory cells in the memory.

[0074] In some embodiments, such as Figure 3 As shown, the orthographic projection of the first transistor T1 onto the substrate 1 is located within the orthographic projection of the third transistor T3 onto the substrate 1.

[0075] The orthographic projection of the second transistor onto the substrate lies within the orthographic projection of the fifth transistor onto the substrate.

[0076] It should be noted that, Figure 3 Only cross-sectional views of the first, third, and fourth transistors are shown; the second, fifth, and sixth transistors are not shown. However, in a specific implementation, the cross-sectional views of the second, fifth, and sixth transistors are similar to those of the first, third, and fourth transistors. Figure 3 The first transistor in the structure can be replaced by the second transistor, and the third and fourth transistors can be replaced by the fifth and sixth transistors, respectively.

[0077] In some embodiments, such as Figure 3 As shown, the first transistor T1 is located on the side of the third transistor T3 whose gate G3 is away from the substrate 1; the orthographic projection of the first transistor T1 onto the substrate 1 is located in the region between the orthographic projections of the source S3 and drain D3 of the third transistor T3 onto the substrate 1.

[0078] The second transistor is located on the side of the fifth transistor whose gate is away from the substrate; the orthographic projection of the second transistor onto the substrate is located in the region between the orthographic projections of the source and drain of the fifth transistor onto the substrate.

[0079] In some embodiments, the source and drain of the first transistor are disposed on the same layer as the source and drain of the third transistor.

[0080] The source and drain of the second transistor are arranged on the same layer as the source and drain of the fifth transistor.

[0081] The memory provided in this application embodiment has its source and drain of the first transistor and the third transistor on the same layer, and its source and drain of the second transistor and the fifth transistor on the same layer. With the transmission circuit and storage circuit stacked, the number of film layers in the memory can be minimized, thus avoiding excessive memory thickness. Furthermore, having the source and drain of the first transistor and the third transistor on the same layer, and the source and drain of the second transistor and the fifth transistor on the same layer, facilitates electrical connection between the transmission circuit and the storage circuit, and also saves on process steps and costs.

[0082] In some embodiments, the source and drain of the first transistor are disposed on the same layer as the source and drain of the second transistor, the gate of the first transistor is disposed on the same layer as the gate of the second transistor, and the active layer of the first transistor is disposed on the same layer as the active layer of the second transistor.

[0083] The source and drain of the third transistor, the source and drain of the fourth transistor, the source and drain of the fifth transistor, and the source and drain of the sixth transistor are arranged in the same layer. The gates of the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor are arranged in the same layer. The active layers of the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor are arranged in the same layer.

[0084] In specific implementation, the active layers of the first and second transistors are arranged on the same layer, the gates of the first and second transistors are arranged on the same layer, the active layers of the third, fourth, fifth, and sixth transistors are arranged on the same layer, the gates of the third, fourth, fifth, and sixth transistors are arranged on the same layer, and the source and drain of the first, second, third, fourth, fifth, and sixth transistors are arranged on the same layer. In specific implementation, such as... Figure 3 As shown, the drain D1 of the first transistor T1, the drain D3 of the third transistor T3, and the source S4 of the fourth transistor T4 are connected together. The drains of the second transistor, the fifth transistor, and the source of the sixth transistor are also connected together.

[0085] In some embodiments, such as Figure 3 As shown, the memory also includes: a first buffer layer 9 located between the substrate and the active layer 6 of the third transistor T3; a first gate insulating layer 11 located between the active layer 6 of the third transistor T3 and the gate G3 of the third transistor T3; a second gate insulating layer 12 located between the gate G3 of the third transistor T3 and the active layer 8 of the first transistor T1; a second buffer layer 13 located between the second gate insulating layer 12 and the active layer 8 of the first transistor T1; a third gate insulating layer 14 located between the active layer 8 of the first transistor T1 and the gate G1 of the first transistor T1; and an interlayer insulating layer 15 located between the source S1 and drain D1 of the first transistor T1 and the gate G1 of the first transistor T1. The source S1 and drain D1 of the first transistor T1 are electrically connected to the active layer 8 of the first transistor T1 through vias penetrating the interlayer insulating layer 15 and the third gate insulating layer 14, respectively. The source S3 and drain D3 of the third transistor T3 are electrically connected to the active layer 6 of the third transistor T3 through vias penetrating the interlayer insulating layer 15, the third gate insulating layer 14, the second buffer layer 13, the second gate insulating layer 12, and the first gate insulating layer 11, respectively. The source S4 and drain D4 of the fourth transistor T4 are electrically connected to the active layer 7 of the fourth transistor T4 through vias penetrating the interlayer insulating layer 15, the third gate insulating layer 14, the second buffer layer 13, the second gate insulating layer 12, and the first gate insulating layer 11, respectively. Furthermore, the source and drain of the second transistor are electrically connected to the active layer of the second transistor through vias penetrating the interlayer insulating layer and the third gate insulating layer, respectively. The source and drain of the fifth transistor are electrically connected to the active layer of the fifth transistor through vias penetrating the interlayer insulating layer, the third gate insulating layer, the second buffer layer, the second gate insulating layer, and the first gate insulating layer, respectively. The source and drain of the sixth transistor are electrically connected to the active layer of the sixth transistor through vias penetrating the interlayer insulating layer, the third gate insulating layer, the second buffer layer, the second gate insulating layer, and the first gate insulating layer, respectively.

[0086] In some embodiments, the material of the active layer of the first transistor and the material of the active layer of the second transistor include oxide semiconductors.

[0087] The active layer materials of the third transistor, the fourth transistor, the fifth transistor, and the sixth transistor include low-temperature polycrystalline silicon.

[0088] It should be noted that if the active layer materials of the first transistor and the second transistor are also low-temperature polycrystalline silicon (LTPS), the laser used in the excimer laser annealing (ELA) process during LTPS fabrication will affect the channels of the third, fourth, fifth, and sixth transistors. Therefore, in the memory provided in this application embodiment, the active layer materials of the first transistor and the second transistor include oxide semiconductors, thus eliminating the need for laser-based conductor formation and avoiding any impact on the channels of the third, fourth, fifth, and sixth transistors, thereby preventing any impact on their yield.

[0089] In practical implementation, the oxide semiconductor is, for example, IGZO.

[0090] When the active layer of the first transistor and the active layer of the second transistor are made of oxide semiconductor, and the active layer of the third transistor, the active layer of the fourth transistor, the active layer of the fifth transistor and the active layer of the sixth transistor are made of low-temperature polysilicon, in some embodiments, the memory cell further includes: a first light-shielding portion and a second light-shielding portion.

[0091] like Figure 3 As shown, the first light-shielding part 4 is located between the active layer of the first transistor T1 and the gate G of the third transistor T3, and the orthographic projection of the active layer of the first transistor T1 onto the substrate 1 falls within the orthographic projection of the first light-shielding part 4 onto the substrate 1.

[0092] The second light-shielding part is located between the active layer of the second transistor and the gate of the fifth transistor, and the orthographic projection of the active layer of the second transistor onto the substrate falls within the orthographic projection of the second light-shielding part onto the substrate.

[0093] It should be noted that when a light source is present on the side of the active layer of the first transistor and the active layer of the second transistor facing the substrate, the provision of the first light-shielding part and the second light-shielding part can prevent the light from affecting the active layer of the first transistor and the active layer of the second transistor.

[0094] In some embodiments, the first light-shielding part and the second light-shielding part are disposed in the same layer, such as Figure 3As shown, the first light-shielding part 4 is located between the second buffer layer 13 and the second gate insulating layer 12. Correspondingly, the second light-shielding part is also located between the second buffer layer and the second gate insulating layer.

[0095] Alternatively, in some embodiments, the materials of the active layer of the first transistor T1, the active layer of the second transistor T2, the active layer of the third transistor T3, the active layer of the fourth transistor T4, the active layer of the fifth transistor T5, and the active layer of the sixth transistor T6 include low-temperature polycrystalline silicon.

[0096] In practical implementation, the impact of the laser processing on the active layers of the first and second transistors on the active layers of the third, fourth, fifth, and sixth transistors can be avoided by increasing the thickness of the buffer layer (i.e., the second buffer layer) between the active layers of the first and second transistors. In practical implementation, the thickness of the second buffer layer is greater than 1 micrometer.

[0097] In some embodiments, the word line WL is disposed on the same layer as the gate of the first transistor and the gate of the second transistor. This facilitates the electrical connection between the word line WL and the gates of the first and second transistors, eliminating the need for vias between them and simplifying the memory fabrication process.

[0098] In some embodiments, such as Figure 3 , Figure 4 As shown, the first line BL is located on the side of the first transistor T1 away from the substrate 1, between the source S1 and the drain D1.

[0099] The second bit line is located on the side of the second transistor where the source and drain are away from the substrate. That is, the first bit line and the second bit line are located on different film layers from the first transistor and the second transistor, thus providing ample wiring space for the first bit line and the second bit line, which simplifies the memory wiring process.

[0100] In some embodiments, the first bit line and the second bit line are arranged on the same layer.

[0101] In specific implementation, such as Figure 3 , Figure 4 As shown, the memory also includes a first planarization layer 16 located between the first bit line BL and the source S1 and drain D1 of the first transistor T1. The first bit line BL is electrically connected to the source S1 of the first transistor T1 through a via penetrating the first planarization layer 16. Furthermore, the second bit line is electrically connected to the source of the second transistor through a via penetrating the first planarization layer.

[0102] In a specific implementation, the memory also includes a second planarization layer located on the side of the first bit line and the second bit line away from the substrate.

[0103] In some embodiments, such as Figure 3 , Figure 4 As shown, the low-level signal line VSS is on the same layer as the drain D4 of the fourth transistor T4 and the drain (not shown) of the sixth transistor, and the high-level signal line VDD is on the same layer as the source S3 of the third transistor T3 and the source (not shown) of the fifth transistor.

[0104] In specific implementation, such as Figure 3 , Figure 4 As shown, the low-level signal line VSS is connected to the drain D4 of the fourth transistor T4 and the drain of the sixth transistor (not shown), and the high-level signal line VDD is connected to the source S3 of the third transistor T3 and the source of the fifth transistor (not shown).

[0105] An electronic device provided in this application includes a memory provided in this application.

[0106] In some embodiments, the electronic device is a display device with display functionality.

[0107] In a specific implementation, the display device may include, for example, a display panel and a driving module electrically connected to the display panel. The driving module may include, for example, one or more memories as provided in the embodiments of this application. The display panel may be, for example, a liquid crystal display panel or an electroluminescent display panel. The electroluminescent display panel may be, for example, an organic light-emitting diode display panel, a quantum dot light-emitting diode display panel, a mini light-emitting diode display panel, etc.

[0108] Of course, if the display panel is a mini light-emitting diode or the like and requires a driver chip corresponding to each pixel, the driver chip may also include the memory provided in the embodiments of this application.

[0109] The display device provided in this application embodiment includes any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, and navigator. Other essential components of this display device are understood by those skilled in the art and will not be described in detail here, nor should they be construed as limiting this application.

[0110] In summary, the memory and display device provided in this application embodiment, since the transmission circuit and storage circuit included in each memory unit are stacked, can reduce the overall area occupied by the memory unit compared to the case where the transmission circuit and storage circuit are arranged on the same layer. Without changing the size of the memory, the number of memory units can be increased, thereby improving the storage and computing power of the memory.

[0111] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the invention.

[0112] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A memory, comprising: The memory comprises a plurality of memory cells, each of the memory cells comprising: a substrate, a memory circuit and a transfer circuit located on one side of the substrate; the transfer circuit is electrically connected with the memory circuit; The memory circuit comprises: a first inverter composed of a third transistor and a fourth transistor, and a second inverter composed of a fifth transistor and a sixth transistor, for storing data; the transfer circuit comprises: a first transistor and a second transistor, for writing data to the memory circuit or reading data from the memory circuit; The gate of the third transistor is electrically connected with the gate of the fourth transistor, and the drain of the third transistor is electrically connected with the source of the fourth transistor; the gate of the fifth transistor is electrically connected with the gate of the sixth transistor, and the drain of the fifth transistor is electrically connected with the source of the sixth transistor; the source of the third transistor is electrically connected with the source of the fifth transistor, and the drain of the fourth transistor is electrically connected with the drain of the sixth transistor; The drain of the first transistor is electrically connected with the drain of the third transistor, the source of the fourth transistor, the gate of the fifth transistor and the gate of the sixth transistor; The drain of the second transistor is electrically connected with the drain of the fifth transistor, the source of the sixth transistor, the gate of the third transistor and the gate of the fourth transistor; The source and drain of the first transistor, the source and drain of the second transistor, the source and drain of the third transistor, the source and drain of the fourth transistor, the source and drain of the fifth transistor and the source and drain of the sixth transistor are arranged in the same layer; The gate of the first transistor is arranged in the same layer with the gate of the second transistor, and the active layer of the first transistor is arranged in the same layer with the active layer of the second transistor; The gate of the third transistor, the gate of the fourth transistor, the gate of the fifth transistor and the gate of the sixth transistor are arranged in the same layer, and the active layer of the third transistor, the active layer of the fourth transistor, the active layer of the fifth transistor and the active layer of the sixth transistor are arranged in the same layer; The transfer circuit is arranged in a stack with the memory circuit; The transfer circuit has an overlap with the memory circuit in the orthographic projection of the substrate; wherein the orthographic projection of the first transistor on the substrate is located within the orthographic projection of the third transistor on the substrate; and the orthographic projection of the second transistor on the substrate is located within the orthographic projection of the fifth transistor on the substrate.

2. The memory of claim 1, wherein, The first transistor is located on the side of the gate of the third transistor away from the substrate; and the orthographic projection of the first transistor on the substrate is located in the region between the orthographic projection of the source and drain of the third transistor on the substrate; The second transistor is located on the side of the gate of the fifth transistor away from the substrate; and the orthographic projection of the second transistor on the substrate is located in the region between the orthographic projection of the source and drain of the fifth transistor on the substrate.

3. The memory of claim 1, wherein, The material of the active layer of the first transistor and the material of the active layer of the second transistor comprise an oxide semiconductor; The material of the active layer of the third transistor, the material of the active layer of the fourth transistor, the material of the active layer of the fifth transistor and the material of the active layer of the sixth transistor comprise low-temperature polysilicon.

4. The memory of claim 3, wherein, The memory unit further comprises a first light shielding portion and a second light shielding portion; The first light shielding portion is located between the active layer of the first transistor and the gate of the third transistor, and the active layer of the first transistor falls within the orthogonal projection of the first light shielding portion on the substrate. The second light shielding portion is located between the active layer of the second transistor and the gate of the fifth transistor, and the active layer of the second transistor falls within the orthogonal projection of the second light shielding portion on the substrate.

5. The memory of claim 1, wherein, The material of the active layer of the first transistor, the material of the active layer of the second transistor, the material of the active layer of the third transistor, the material of the active layer of the fourth transistor, the material of the active layer of the fifth transistor and the material of the active layer of the sixth transistor comprise low-temperature polysilicon.

6. The memory of claim 5, wherein, A buffer layer is further included between the active layer of the first transistor and the active layer of the third transistor, and the thickness of the buffer layer is greater than 1 micrometer.

7. The memory of any one of claims 1 to 6, wherein, The transmission circuit further comprises a word line, a first bit line and a second bit line; The gate of the first transistor and the gate of the second transistor are electrically connected to the word line, the source of the first transistor is electrically connected to the first bit line, and the source of the second transistor is electrically connected to the second bit line; The memory circuit further comprises a low-level signal line and a high-level signal line; the low-level signal line is electrically connected to the drain of the fourth transistor and the drain of the sixth transistor, and the high-level signal line is electrically connected to the source of the third transistor and the source of the fifth transistor.

8. The memory of claim 7, wherein, The word line is arranged in the same layer as the gate of the first transistor and the gate of the second transistor; The first bit line is located on the side of the source and the drain of the first transistor away from the substrate, and the second bit line is located on the side of the source and the drain of the second transistor away from the substrate; The low-level signal line is arranged in the same layer as the drain of the fourth transistor and the drain of the sixth transistor, and the high-level signal line is arranged in the same layer as the source of the third transistor and the source of the fifth transistor.

9. The memory of any of claims 1-6, 8, wherein, The first transistor, the second transistor, the fourth transistor and the sixth transistor are N-type transistors, and the third transistor and the fifth transistor are P-type transistors.

10. An electronic device, comprising: The memory comprises the memory according to any one of claims 1-9.

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