Start-up protection for standby amplifiers

Abstract

Embodiments herein relate to startup protection for a standby amplifier. Specifically, an input voltage of the standby amplifier may be reduced to reduce the occurrence of damage to the standby amplifier or its components. In some embodiments, the input voltage may be reduced using a voltage divider that provides a reduced input voltage to the standby amplifier during a power-up operation. After the power-up operation is completed, the input voltage of the standby amplifier may be restored to an operating voltage. The reduced input voltage may reduce the occurrence of damage to the standby amplifier by maintaining a gate-to-drain voltage of one or more transistors of the standby amplifier below a maximum value.

Description

Technical Field

[0001] The present disclosure relates generally to computing systems, and more particularly to reducing a startup voltage of a backup amplifier to reduce malfunction of an input device of the backup amplifier. Background Art

[0002] Typically, a computing system includes a host subsystem and a memory subsystem. The memory subsystem may store data accessible to the processing circuitry of the host subsystem. For example, to perform an operation, the processing circuitry may execute instructions retrieved from a memory device implemented in the memory subsystem. In some cases, input data for the operation may also be retrieved from the memory device. Additionally or alternatively, data output from (e.g., generated therefrom) the operation may be stored in the memory device to, for example, enable subsequent retrieval. However, in some cases, the operating efficiency of the computing system may be limited by the architecture of the memory subsystem, and more specifically, by the circuitry associated with column selection operations for retrieving data stored in the memory device. Summary of the invention

[0003] One aspect of the present disclosure provides a backup amplifier, comprising: an operational transconductance amplifier, comprising a first transistor input pair and a second transistor input pair; a protection circuit, comprising a first protection transistor coupled to the first transistor input pair and a second protection transistor coupled to the second transistor input pair, the first protection transistor being configured to selectively couple the first transistor input pair to a voltage level based on an enable voltage, the second protection transistor being configured to selectively couple the second transistor input pair to a voltage level based on a reduced enable voltage; and an enable circuit for generating the reduced enable voltage, the enable circuit comprising a voltage divider for reducing the enable voltage to be less than a maximum drain voltage of a first transistor in the first transistor input pair.

[0004] Another aspect of the present disclosure provides a memory device comprising: a memory array comprising a plurality of memory cells arranged in a plurality of memory cell rows and a plurality of memory cell columns, wherein each of the plurality of memory cells is configured to store a data bit; a backup amplifier coupled to the memory array, the backup amplifier comprising a first transistor input pair and a second transistor input pair; a protection circuit comprising a first protection transistor coupled to the first transistor input pair and a second protection transistor coupled to the second transistor input pair, the first protection transistor being configured to selectively couple the first transistor input pair to a voltage level based on an enable voltage, the second protection transistor being configured to selectively couple the second transistor input pair to a voltage level based on a reduced enable voltage; and an enable circuit for generating the reduced enable voltage, the enable circuit comprising a voltage divider for reducing the enable voltage to be less than a maximum drain voltage of a first transistor in the first transistor input pair.

[0005] Another aspect of the present disclosure provides a memory system comprising: a memory array comprising a plurality of memory cells arranged in a plurality of memory cell rows and a plurality of memory cell columns, wherein each of the plurality of memory cells is configured to store a data bit; a spare amplifier coupled to the memory array, the spare amplifier comprising a first transistor input pair and a second transistor input pair; an enable circuit for generating an enable voltage for the spare amplifier; a protection circuit comprising a first protection transistor coupled to the first transistor input pair and a second protection transistor coupled to the second transistor input pair, the first protection transistor being configured to selectively couple the first transistor input pair to a voltage level based on the enable voltage, the second protection transistor being configured to selectively couple the second transistor input pair to a voltage level based on the enable voltage; and a reduced enable circuit for generating a reduced enable voltage based on the enable voltage, wherein the reduced enable voltage is less than the enable voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Various aspects of the present disclosure may be better understood after reading the following detailed description and by referring to the accompanying drawings.

[0007] Figure 1 is a simplified block diagram of an example of a computing system including a processing (eg, host) subsystem and a memory subsystem according to an embodiment of the present disclosure.

[0008] Figure 2 According to the embodiment of the present disclosure, Figure 1 Schematic diagram of an example circuit of a backup amplifier of a memory device implemented in a memory subsystem of FIG.

[0009] Figure 3 For generating a Figure 2 Schematic diagram of an example circuit for the enable signal of the standby amplifier.

[0010] Figure 4 For generating a Figure 2 Schematic diagram of an example circuit for a reduced enable signal for a standby amplifier.

[0011] Figure 5 To illustrate the use of the embodiment according to the present disclosure Figure 3 Example circuit of Figure 2 Figure 2. The signal waveform of the standby amplifier.

[0012] Figure 6 To illustrate the use of the embodiment according to the present disclosure Figure 3 and 4 Example circuit of Figure 2 Figure 2. The signal waveform of the standby amplifier. DETAILED DESCRIPTION

[0013] The present disclosure provides devices and techniques that facilitate improving the operating efficiency and / or operating performance of a computing system, for example, by reducing the voltage of an enable signal that turns on an amplifier while minimizing an increase in the physical size of the computing system.

[0014] A computing system generally includes various computing subsystems, such as a host (e.g., processing) subsystem and a memory subsystem. The host subsystem may include, for example, processing circuitry implemented in one or more processors and / or one or more processor cores. The memory subsystem may include one or more memory devices (e.g., chips or integrated circuits), such as implemented on memory modules such as dual in-line memory modules (DIMMs), and / or organized to implement one or more memory arrays (e.g., groups of memory cells).

[0015] Typically, during operation of the computing system, processing circuitry implemented in the processing subsystem may perform various operations by executing instructions stored in the memory subsystem. For example, the processing subsystem may determine output data by performing data processing operations based on input data. Additionally, the processing subsystem may generally include one or more registers and / or one or more processor-side cache memories that provide storage locations that the processing subsystem can directly access. However, the storage capacity implemented in the processing subsystem is typically limited.

[0016] Thus, the processing subsystem is typically communicatively coupled to the memory subsystem via one or more memory buses (e.g., external communication, command, and / or data buses). In some cases, a computing system may include, for example, multiple memory buses, each dedicated to a different type of communication. For example, a computing system may include: a memory command (e.g., control and / or request) bus dedicated to communicating command (e.g., control) signals indicating memory access commands (e.g., memory read or write commands); and a memory data bus dedicated to communicating data signals indicating data blocks to be stored (e.g., written) in a memory device of the memory subsystem (e.g., in response to a memory write command and / or a memory read command).

[0017] Furthermore, in some cases, the memory in the memory subsystem may be implemented using multiple different memory types. For example, the memory subsystem may include: one or more volatile memory devices, such as dynamic random access memory (DRAM) devices and / or static random access memory (SRAM) devices; one or more non-volatile memory devices, such as flash (e.g., NAND) memory devices, phase change memory (e.g., 3D XPoint) devices; TM ) devices and / or ferroelectric random access memory (FeRAM) devices.

[0018] The memory devices in the memory subsystem generally include various amplifiers (e.g., regulators), including standby amplifiers and active amplifiers. The active amplifier may be the main amplifier of the memory device and may support a relatively large amount of current, for example, during a read or write operation. The standby amplifier may be operable when the memory device has no current demand or a minimal current demand. The standby amplifier may ensure that the voltage of the memory device is maintained at a specified level when there is no current demand or a minimal current demand. The maximum current provided by the standby amplifier may be about ten to twenty percent of the maximum current of the active amplifier. For example, if the maximum current of the active amplifier is about five milliamperes (mA), the standby amplifier may provide up to about 500 milliamperes (μA). The standby amplifier may be powered on at startup (e.g., power-up) and during operation of the corresponding memory device.

[0019] Protecting a memory device and associated amplifier during startup may be critical because the voltage of the memory device may be in a metastable state. To protect a startup amplifier of a memory device, an input voltage (e.g., an enable voltage) of the startup amplifier may be reduced. Embodiments presented herein provide apparatus and techniques for reducing a startup voltage of a standby amplifier to improve operating performance and extend the life of one or more components of the standby amplifier. Furthermore, the reduced startup voltage may be clamped to the standby amplifier only during startup operations, and thus may not affect the standby amplifier or the memory device during a normal operating mode (e.g., after startup).

[0020] Figure 1 1 is a simplified block diagram of an example of a computing system 10 (eg, a device) including a processing (eg, host) subsystem 12 and a memory subsystem 14 according to an embodiment of the present disclosure. It should be understood that the computing system 10 may include Figure 1 Computing subsystems not shown, such as a networking subsystem, a communication subsystem, a radio frequency subsystem, a user input subsystem, a display subsystem, or a combination thereof.

[0021] In some embodiments, computing system 10 may be implemented in a single electronic device, such as a desktop computer, a workstation computer, a notebook computer, a server, a mobile phone, a virtual reality head-mounted device, etc. In other embodiments, computing system 10 may be distributed among multiple electronic devices. For example, processing subsystem 12 and memory subsystem 14 may be implemented in a host device, while other computing subsystems such as a user input subsystem and / or a display subsystem may be implemented in a client (e.g., remote) device. In some embodiments, computing subsystems may be distributed among multiple electronic devices. For example, a first portion of processing subsystem 12 and / or a first portion of memory subsystem 14 may be implemented in a host device, while a second portion of processing subsystem 12 and / or a second portion of memory subsystem 14 may be implemented in a client device.

[0022] As shown, processing subsystem 12 may include processing circuitry 16. Processing circuitry 16 may include one or more central processing units (CPUs), one or more graphics processing units (GPUs), one or more processor cores, or any combination thereof. During operation, processing subsystem 12 may perform various operations, such as determining output data by executing instructions that perform data processing operations based on input data via processing circuitry 16. Processing subsystem 12 may also include one or more cache memories 22 that may be integrated with processing circuitry 16. One or more cache memories 22 may provide storage locations that processing circuitry 16 may directly access. Processing subsystem 12 may be coupled to one or more memory controllers 28 via one or more buses 27 to control storage of one or more cache memories 22.

[0023] The memory subsystem 14 typically stores data that can be accessed by the processing subsystem 12 via one or more memory devices 18. The memory device 18 may include an integrated circuit or chip having one or more memory cells (e.g., circuitry) organized into one or more memory arrays, and thus may include one or more tangible, non-transitory computer-readable media. For example, the memory subsystem 14 may include one or more dynamic random access memory (DRAM) devices, one or more static random access memory (SRAM) devices, one or more flash (e.g., NAND) memory devices, one or more phase change memories (e.g., 3D XPoint TM ) memory device, one or more ferroelectric random access memories (FeRAM), or any combination thereof.

[0024] In some embodiments, multiple memory devices 18 may be implemented on a memory module such as a dual in-line memory module (DIMM) or a single in-line memory module (SIMM). For example, the memory module may include a printed circuit board (PCB) and multiple memory devices 18 each disposed on a flat or planar (e.g., front or back) surface of the printed circuit board. Additionally, the memory devices 18 may be coupled to external pins formed along an edge (e.g., bottom) of the printed circuit board via conductive traces formed on the printed circuit board.

[0025] It should be appreciated that one or more of memory devices 18 may be implemented using other packaging technologies. For example, memory device 18 may be coupled to a (e.g., silicon) interposer to implement a 2.5D configuration. Additionally or alternatively, memory devices 18 may be stacked to implement a 3D configuration. Furthermore, in some embodiments, memory device 18 may be implemented using organic packaging technology. In other words, the techniques described in this disclosure may be implemented as an on-package solution.

[0026] The memory subsystem 14 also includes one or more memory caches 24. Although implemented in the memory subsystem 14, the memory caches 24 may provide faster data communication than memory arrays implemented in the memory devices 18. For example, the memory caches 24 may be implemented using static random access memory (SRAM), while the memory devices 18 may be implemented using dynamic random access memory (DRAM). Additionally or alternatively, the memory caches 24 and the memory arrays implemented in the one or more memory devices 18 may utilize the same memory type (e.g., DRAM). In fact, in some embodiments, one or more of the memory caches 24 may be implemented in the memory devices 18. To control storage of the one or more memory caches 24, the memory subsystem 14 may be coupled to one or more memory controllers 28 via one or more buses 27.

[0027] As shown, the processing subsystem 12 is communicatively coupled to the memory subsystem 14 via one or more memory buses 20. The data bus 20 may include one or more cables, one or more wires, one or more conductive traces, one or more communication networks, or any combination thereof. Each of the one or more memory buses 20 may be dedicated to a different type of communication between the memory subsystem 14 and the processing subsystem 12. For example, the memory bus 20 may include a memory command bus and a memory data bus.

[0028] Figure 2 According to the embodiment of the present disclosure, Figure 1 Schematic diagram of an example circuit 50 of a backup amplifier 52 of a memory device 18 implemented in a memory subsystem 14 of FIG. The example circuit 50 includes a protection circuit 54 coupled to the backup amplifier 52. In some cases, the backup amplifier 52 may be referred to as an operational transconductance amplifier (OTA). In some cases, the backup amplifier may include the OTA 52 and the protection circuit 54. The backup amplifier 52 includes transistors T1, T2, T3, and T4. Transistors T1 and T2 may form a first input pair of the backup amplifier 52, and transistors T3 and T4 may form a second input pair of the backup amplifier 52. The bandwidth of the backup amplifier 52 may be limited, and therefore, the gate voltages of transistors T1 and T3 may increase slowly.

[0029] The protection circuit 54 includes transistors T9 and T10. The transistors T9 and T10 may be enabled (e.g., closed) when an enable voltage En 58 is applied to their gates via a node 56. A larger enable voltage En 58 may more quickly close transistors T9 and T10, and thus more quickly increase the voltage across transistors T1 and T3 to a high voltage (e.g., VPP).

[0030] Example circuit 50 also includes transistors T5, T6, T7, and T8 coupled to amplifier 52. As shown, each of transistors T1-T10 may be an n-channel transistor. It should be understood that transistors T1-T10 may be of different types (n-channel or p-channel) and may be arranged in a configuration different from that shown. In some cases, spare amplifier 52 may provide up to about 500 microamperes (μA).

[0031] In some embodiments, the maximum voltage of transistor T1 from drain to source, gate to drain, or gate to source may be, for example, about 1.4 volts. If one of those voltage measurements exceeds about 1.4 volts, transistor T1 may be damaged beyond repair and backup amplifier 52 may no longer operate. To prevent damage to transistor T1 (and transistor T3) and / or backup amplifier 52, protection circuit 54 may ensure that the drain voltage of transistor T1 does not exceed the gate voltage of transistor T9 minus the threshold voltage V of transistor T9. T That is, the drain voltage of transistor T1 may be less than the enable voltage En 58 at the gate of transistor T9 minus the threshold voltage V of transistor T9. T The transistor T10 may have a threshold voltage similar to the threshold voltage of the transistor T9. The drain voltage of the transistor T3 may be the same as or substantially similar to the drain voltage of the transistor T9. In this way, the transistors T9 and T10 of the protection circuit 54 may limit the voltage of the transistors T1 and T3 of the backup amplifier 52.

[0032] When the standby amplifier 52 is activated, the gate voltage of transistors T1 and T2 may be about 1 volt, and the gate voltage of transistors T3 and T4 may be zero volts. However, the drains of transistors T1 and T3 may be at a high voltage (e.g., about 2.2 volts). In this case, the voltage across transistors T1 and T3 may be greater than the maximum voltage of about 1.4 volts. Therefore, transistors T1 and / or T3 may be damaged.

[0033] Embodiments disclosed herein present devices and techniques for reducing and / or limiting the enable voltage En 58 supplied to transistors T1 and T3 via the protection circuit 54 during the startup operation. Once the startup operation is completed, the enable voltage En 58 can be restored to the previous voltage level. Advantageously, the reduced enable voltage En 58 can reduce the occurrence of damage to components (e.g., transistors T1 to T4) of the standby amplifier 52 during the startup operation without affecting subsequent execution or operation.

[0034] Figure 3 For generating a Figure 2Schematic diagram of an example circuit 80 for enabling a signal for a standby amplifier 52 of FIG. 8A. As shown, the circuit 80 may receive various inputs 82 and 88 to 94. Specifically, the input of the circuit 80 may include a power-on signal 90. When the power-on signal 90 is high (e.g., between about 1 volt and about 1.5 volts, such as about 1.2 volts), the enable voltage En 58 may be high (e.g., about 2 volts). The circuit 80 includes several components, including several inverters 84, switches 96, logic NOR gates 100, and logic NAND gates 102.

[0035] The enable voltage En 58 is output from the example circuit 80 via the output node 120. The enable voltage En 58 may be output via the output node 120. Figure 2 The node 56 in question supplies to the protection circuit 54. That is, the node 56 of the backup amplifier 52 may be coupled to the output node 120 of the circuit 80.

[0036] Figure 4 For generating a Figure 2 Schematic diagram of an example circuit 150 for generating a reduced enable voltage EnDy 152 of a standby amplifier 52. The example circuit 150 is a voltage divider for generating a reduced enable voltage EnDy 152 from the enable voltage En 58. That is, the voltage divider 150 generates a reduced enable voltage EnDy 152 via Figure 3 Node output 120 of circuit 80 receives enable voltage En58.

[0037] In some embodiments, the voltage divider 150 may be a resistor divider. As shown, the voltage divider 150 includes a number of resistors R1 to R7. In some embodiments, the resistance of each of the resistors R1 to R7 may be the same. For example, the resistance of each of the resistors may be about 30 kilo-ohms (kΩ). In other embodiments, the resistance of each resistor R1 to R7 may be different. In some cases, the area of ​​each resistor R1 to R7 may be about 1 micron.

[0038] The reduced enable voltage EnDy 152 may be generated by tapping the voltage divider 150 between resistors R2 and R3 via a switch 156. Thus, the reduced enable voltage EnDy 152 may be approximately 30% less than the enable voltage En 58. In some embodiments, the reduced enable voltage EnDy 152 may be approximately 15% less than the enable voltage En 58 by closing (or opening) the switch 156 so that the switch 156 taps the voltage divider 150 between resistors R1 and R2.

[0039] The reduced enable voltage EnDy 152 may be provided to the standby amplifier 52 until the reverse power-on signal 154 transitions from a logic high voltage (e.g., 1) to a logic low voltage (e.g., 0). That is, before the power-on operation and until the power-on operation is completed, the reverse power-on signal 154 may be logic high. When the power-on operation is completed, the power-on signal 90 may transition from logic low to logic high. That is, the logic high of the reverse power-on signal 154 may close the transistor T12, so that current flows through the voltage divider 150, and the reduced enable voltage EnDy 152 is provided to the standby amplifier 52. Once the power-on operation is completed, the reverse power-on signal 154 may transition from logic high to logic low, thereby disconnecting the transistor T12 and stopping the current from flowing through the resistors R1 to R7. In this case, after the power-on operation is completed, the enable voltage En 58 may be coupled to the protection circuit 54. In this manner, transistor T12 may control the voltage level provided to the protection circuit 54 such that a reduced enable voltage (eg, EnDy 152 ) may be provided to the protection circuit during a power-up operation.

[0040] In this way, the voltage divider 150 can provide a reduced enable voltage EnDy 152 to the standby amplifier 52 to reduce the occurrence of damage to the standby amplifier 52 and / or its components during the startup operation. After the startup operation is completed, the voltage divider 150 can provide the (e.g., unreduced) enable voltage En 58 to the standby amplifier 52 to ensure normal operation. It should be understood that the voltage divider 150 is merely an example, and many other configurations including different layouts and / or more or fewer resistors are possible to obtain different values ​​of the reduced enable voltage EnDy 152. For example, the reduced enable voltage EnDy 152 can be generated by tapping the voltage divider 150 between resistors different from the resistors discussed above, such as between resistors R3 and R4. Advantageously, the reduced enable voltage EnDy 152 can reduce the occurrence of damage to one or more components of the standby amplifier 52, and thus can extend the useful life of the components and / or the standby amplifier.

[0041] Figure 5 To illustrate the use of the embodiment according to the present disclosure Figure 3 Example circuit 80 Figure 2 FIG180 is a diagram of a signal waveform of a standby amplifier 52. As shown, FIG180 includes a power-on signal 90, an enable voltage En 58, Figure 2 The gate voltage 184 of transistor T1 or transistor T3, the drain voltage 186 of transistor T1 or transistor T3, the gate-to-drain voltage (VGD) 188 across transistor T1 or transistor T3, and the output voltage 190 of the standby amplifier 52.

[0042] In operation, when the power-on signal 90 transitions from low to high (e.g., from about 0 volts to about 1 volt), the gate-to-drain voltage (VGD) 188 across transistor T1 or transistor T3 increases to exceed 1.4 volts. That is, the gate-to-drain voltage (VGD) 188 across transistor T1 or transistor T3 exceeds the maximum voltage of transistor T1 or transistor T3. Therefore, during the power-on operation, transistor T1 or transistor T3 may be damaged by the relatively high voltage. In some cases, a high voltage (e.g., greater than 1.4 volts) may be applied across transistor T1 or transistor T3 for a relatively long period of time (e.g., between about 1 microsecond (μs) and about 4 μs), causing increased damage to transistor T1 or transistor T3.

[0043] If transistor T1 or transistor T3 is not completely damaged during a particular power-up operation, the damage may be cumulative, and thus transistor T1 or transistor T3 may be completely damaged during a subsequent power-up operation. As discussed above, embodiments herein present techniques for reducing the voltage supplied to transistor T1 or transistor T3 (and thus across transistor T1 or transistor T3) to substantially reduce the occurrence of damage caused thereby.

[0044] Figure 6 To illustrate the use of the embodiment according to the present disclosure Figure 3 and 4 Example circuits of 80 and 150 Figure 2 FIG200 is a diagram of a signal waveform of the standby amplifier 52. That is, FIG200 illustrates the signal waveform of the standby amplifier 52 using the voltage divider 150 to provide the reduced enable voltage EnDy152. As shown, Figure 2 The enable voltage En of the standby amplifier 52 is clamped to the reduced enable voltage EnDy 152 during the time period 204 during the power-up operation of the standby amplifier 52. As the enable voltage EnDy 152 is reduced, the gate-to-drain voltage (VGD) 188 across the transistor T1 or the transistor T3 can be reduced to about 1 volt. Once the power-up operation is completed, the input voltage of the standby amplifier 52 can be restored to the enable voltage En 58 voltage level (e.g., when the power-up signal 90 transitions from low to high and the reverse power-up signal 154 transitions from high to low).

[0045] That is, the reduced enable voltage EnDy 152 maintains the gate-to-drain voltage (VGD) 188 below the maximum voltage of transistor T1 or transistor T3 (e.g., 1.4 volts). In this way, the reduced enable voltage EnDy 152 can reduce the occurrence of damage to one or more components of the standby amplifier 52, and thus can extend the service life of the components and / or the standby amplifier.

[0046] One or more specific embodiments of the present disclosure are described herein and in the corresponding figures. The described embodiments are merely examples of the currently disclosed technology. In addition, in order to provide a concise description of these embodiments, all features of the actual implementation scheme may not be described in the specification. It should be understood that in the development process of any such actual implementation scheme, as in any engineering or design project, numerous implementation scheme-specific decisions must be made to achieve the specific goals of the developer, such as complying with system-related and enterprise-related constraints that may vary between various implementation schemes. In addition, it should be understood that such development work may be complex and time-consuming, but for those skilled in the art who benefit from the present disclosure, these may all be routine tasks in design, production, and manufacturing.

[0047] When introducing elements of various embodiments of the present disclosure, the articles "a," "an," and "the" are intended to mean that there are one or more of the elements. The terms "comprising," "including," and "having" are intended to be inclusive and mean that there may be additional elements in addition to the listed elements. Additionally, it should be understood that reference to "one embodiment" or "an embodiment" of the present disclosure is not intended to be interpreted as excluding the existence of additional embodiments that also incorporate the recited features.

[0048] The specific embodiments described above have been shown by way of example, and it should be understood that these embodiments are susceptible to various modifications and alternative forms. It should be further understood that the claims are not intended to be limited to the specific forms disclosed, but to cover all modifications, equivalents and alternatives within the spirit and scope of the present disclosure.

Claims

1. A backup amplifier, comprising: an operational transconductance amplifier including a first transistor input pair and a second transistor input pair; a protection circuit comprising a first protection transistor coupled to the first transistor input pair and a second protection transistor coupled to the second transistor input pair, the first protection transistor configured to selectively couple the first transistor input pair to a voltage level based on an enable voltage, the second protection transistor configured to selectively couple the second transistor input pair to a voltage level based on a reduced enable voltage; as well as An enable circuit for generating the reduced enable voltage includes a voltage divider for reducing the enable voltage to be less than a maximum drain voltage of a first transistor in the first transistor input pair.

2. The backup amplifier of claim 1, wherein the voltage divider comprises a resistor divider for generating the reduced enable voltage, and wherein the reduced enable voltage is approximately thirty percent less than the enable voltage.

3. The backup amplifier of claim 2, wherein the enable circuit provides the reduced enable voltage to the protection circuit during a power-up operation of the backup amplifier.

4. The backup amplifier of claim 2, wherein the voltage divider comprises a transistor for selectively coupling the protection circuit to the reduced enable voltage.

5. The backup amplifier of claim 2, wherein the resistor divider comprises a plurality of resistors having a resistance of approximately 30 kilo-ohms.

6. The backup amplifier of claim 1, wherein a maximum drain to gate voltage of the first transistor in the first transistor input pair is approximately 1.4 volts.

7. The backup amplifier of claim 6, wherein the protection circuit maintains a drain voltage of the first transistor of the first transistor input pair below a gate voltage of the first protection transistor minus a threshold voltage of the first protection transistor.

8. The backup amplifier of claim 1, wherein a maximum voltage of a first transistor in the second transistor input pair is approximately 1.4 volts.

9. A memory device comprising: a memory array comprising a plurality of memory cells arranged in a plurality of memory cell rows and a plurality of memory cell columns, wherein each memory cell of the plurality of memory cells is configured to store a bit of data; a spare amplifier coupled to the memory array, the spare amplifier comprising a first transistor input pair and a second transistor input pair; a protection circuit comprising a first protection transistor coupled to the first transistor input pair and a second protection transistor coupled to the second transistor input pair, the first protection transistor configured to selectively couple the first transistor input pair to a voltage level based on an enable voltage, the second protection transistor configured to selectively couple the second transistor input pair to a voltage level based on a reduced enable voltage; as well as An enable circuit for generating the reduced enable voltage includes a voltage divider for reducing the enable voltage to be less than a maximum drain voltage of a first transistor in the first transistor input pair.

10. The memory device of claim 9, wherein a maximum drain to gate voltage of the first transistor in the first transistor input pair is approximately 1.4 volts, and wherein the reduced enable voltage is approximately thirty percent less than the enable voltage.

11. The memory device of claim 10, wherein the protection circuit maintains a drain voltage of the first transistor of the first transistor input pair below a gate voltage of the first protection transistor minus a threshold voltage of the first protection transistor.

12. The memory device of claim 9, wherein the voltage divider comprises a resistor divider for generating the reduced enable voltage.

13. The memory device of claim 12, wherein the enable circuit provides the reduced enable voltage to the protection circuit during a power-up operation of the backup amplifier.

14. The memory device of claim 12, wherein the voltage divider comprises a transistor for selectively coupling the protection circuit to the reduced enable voltage.

15. The memory device of claim 12, wherein the resistor divider comprises a plurality of resistors having a resistance of approximately 30 kilo-ohms.

16. A memory system comprising: a memory array comprising a plurality of memory cells arranged in a plurality of memory cell rows and a plurality of memory cell columns, wherein each memory cell of the plurality of memory cells is configured to store a bit of data; a spare amplifier coupled to the memory array, the spare amplifier comprising a first transistor input pair and a second transistor input pair; an enabling circuit for generating an enabling voltage for the standby amplifier; a protection circuit comprising a first protection transistor coupled to the first transistor input pair and a second protection transistor coupled to a second transistor input pair, the first protection transistor configured to selectively couple the first transistor input pair to a voltage level based on the enable voltage, the second protection transistor configured to selectively couple the second transistor input pair to a voltage level based on the enable voltage; as well as A reduction enable circuit is configured to generate a reduced enable voltage based on the enable voltage, wherein the reduced enable voltage is less than the enable voltage.

17. The memory system of claim 16, wherein the reduced enable circuit comprises a voltage divider, and wherein the reduced enable voltage is approximately thirty percent less than the enable voltage.

18. The memory system of claim 17, wherein the voltage divider comprises a resistor divider circuit.

19. The memory system of claim 18, wherein the reduced enable circuit provides the reduced enable voltage to the protection circuit during a power-up operation.

20. The memory system of claim 19, wherein the enable circuit provides the enable voltage to the protection circuit after the power-up operation.

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