Memory structure and memory

Abstract

The present disclosure provides a memory structure and a memory, relating to the field of integrated circuit manufacturing technology. The memory structure includes a plurality of memory arrays arranged in parallel along a first direction and extending along a second direction, a sense amplifier array extending along the second direction is arranged between every two memory arrays, the sense amplifier array including an odd-bit sense amplifier array and an even-bit sense amplifier array, the odd-bit sense amplifier array connected to an odd-bit global signal line, and the even-bit sense amplifier array connected to an even-bit global signal line; a spare memory array is arranged on one side of the memory array located at an edge in the first direction, a first sense amplifier array is arranged between the spare memory array and the edge memory array, the first sense amplifier array connected to both the odd-bit global signal line and the even-bit global signal line. The embodiments of the present disclosure can improve the reliability, yield rate, and test success rate of memory products.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuit manufacturing, and in particular to a memory structure and a memory with higher reliability. Background Art

[0002] As process geometries continue to shrink, or during the early stages of new process development, improving the yield of memory products presents significant challenges. Effectively improving the yield of memory products, the success rate of memory chip repairs, and the reliability of memory chips has become a critical issue in the memory manufacturing field.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field. Summary of the Invention

[0004] The purpose of the present disclosure is to provide a memory structure and a memory, which are used to at least to some extent overcome the problem that the memory yield, reliability and repair success rate need to be improved due to the limitations and defects of related technologies.

[0005] According to a first aspect of the present disclosure, a memory structure is provided, comprising a plurality of memory arrays arranged in parallel along a first direction and extending along a second direction, a sense amplifier array extending along the second direction being arranged between every two memory arrays, the sense amplifier array comprising an odd-bit sense amplifier array and an even-bit sense amplifier array, the odd-bit sense amplifier array and the even-bit sense amplifier array being arranged alternately along the first direction, the odd-bit sense amplifier array being connected to an odd-bit global signal line, and the even-bit sense amplifier array being connected to an even-bit global signal line; a spare memory array being arranged on a side of the memory array located at an edge in the first direction, a first sense amplifier array being arranged between the spare memory array and the edge memory array, the first sense amplifier array being connected to both the odd-bit global signal line and the even-bit global signal line.

[0006] In an exemplary embodiment of the present disclosure, each of the storage arrays includes a plurality of storage sub-arrays arranged along the second direction, each of the sense amplifier arrays includes a plurality of sense amplifier sub-arrays, each of the sense amplifier sub-arrays is connected to a read-write conversion circuit, the sense amplifier sub-arrays correspond one-to-one to the storage sub-arrays, each of the odd-bit sense amplifier arrays is electrically connected to a plurality of odd-bit global signal lines through a plurality of the read-write conversion circuits, and each of the even-bit sense amplifier arrays is electrically connected to a plurality of even-bit global signal lines through a plurality of the read-write conversion circuits; the spare storage array includes a plurality of first spare storage sub-arrays, the first sense amplifier array includes a plurality of first sense amplifier sub-arrays, each of the first spare storage sub-arrays corresponds to a first sense amplifier sub-array, and the first sense amplifier sub-arrays are electrically connected to both the odd-bit global signal lines and the even-bit global signal lines through the spare read-write conversion circuits.

[0007] In an exemplary embodiment of the present disclosure, there are two spare storage arrays, which are respectively arranged beside the two storage arrays located at the edge.

[0008] In an exemplary embodiment of the present disclosure, each of the storage array and the spare storage array includes a second spare storage sub-array, and the second spare storage sub-array is arranged along the first direction. The sense amplifier array also includes a spare sense amplifier sub-array, and the spare sense amplifier sub-array is located between two adjacent second spare storage sub-arrays.

[0009] In an exemplary embodiment of the present disclosure, the number of the second spare storage sub-array in each of the storage arrays or the spare storage array is one.

[0010] In an exemplary embodiment of the present disclosure, the spare sense amplifier sub-arrays located in the odd-bit sense amplifier array are all electrically connected to the same spare odd-bit global signal line; and the spare sense amplifier sub-arrays located in the even-bit sense amplifier array are electrically connected to the same spare even-bit global signal line.

[0011] In an exemplary embodiment of the present disclosure, the backup read-write conversion circuit includes: an even-bit read control circuit, connecting the even-bit global signal line, the even-bit read control signal line and the complementary local signal line; an even-bit write control circuit, connecting the even-bit global signal line, the even-bit write control signal line and the complementary local signal line, and the local signal line; an odd-bit read control circuit, connecting the odd-bit global signal line, the odd-bit read control signal line and the local signal line; and an odd-bit write control circuit, connecting the odd-bit global signal line, the odd-bit write control signal line and the complementary local signal line and the local signal line.

[0012] In an exemplary embodiment of the present disclosure, the backup read-write conversion circuit further includes: a pre-charging circuit, which connects the complementary local signal line, the local signal line, a power supply voltage and a pre-charging signal, and the pre-charging circuit is used to pull up the complementary local signal line and the local signal line.

[0013] In an exemplary embodiment of the present disclosure, the backup read-write conversion circuit also includes: a read-write assist circuit, which connects the complementary local signal line, the local signal line and the enable signal, and is used to amplify the complementary local signal line and the local signal line.

[0014] In an exemplary embodiment of the present disclosure, the even-bit read control circuit includes a first N-type transistor and a second N-type transistor, the drain of the first N-type transistor is connected to the odd-bit global signal line, the gate is connected to the complementary local signal line, the drain of the second N-type transistor is connected to the source of the first N-type transistor, the gate is connected to the even-bit read control signal line, and the source is grounded; the even-bit write control circuit includes a third N-type transistor, a fourth N-type transistor, and a fifth N-type transistor, the first end of the third N-type transistor is connected to the odd-bit global signal line, the second end is connected to the local signal line, the gate is connected to the even-bit write control signal line, the drain of the fourth N-type transistor is connected to the local signal line, the gate is connected to the odd-bit global signal line, the drain of the fifth N-type transistor is connected to the source of the fourth N-type transistor, the gate is connected to the even-bit write control signal line, and the source is grounded.

[0015] In an exemplary embodiment of the present disclosure, the odd-bit read control circuit includes: the odd-bit read control circuit includes a sixth N-type transistor and a seventh N-type transistor, the drain of the sixth N-type transistor is connected to the even-bit global signal line, the gate is connected to the local signal line, the drain of the seventh N-type transistor is connected to the source of the sixth N-type transistor, the gate is connected to the odd-bit read control signal line, and the source is grounded; the odd-bit write control circuit includes an eighth N-type transistor, a ninth N-type transistor, and a tenth N-type transistor, the first end of the eighth N-type transistor is connected to the even-bit global signal line, the second end is connected to the complementary local signal line, the gate is connected to the odd-bit write control signal line, the drain of the ninth N-type transistor is connected to the complementary local signal line, the gate is connected to the even-bit global signal line, the drain of the tenth N-type transistor is connected to the source of the ninth N-type transistor, the gate is connected to the odd-bit write control signal line, and the source is grounded.

[0016] In an exemplary embodiment of the present disclosure, the pre-charging circuit includes: a first P-type transistor, whose source is connected to the power supply voltage, whose gate is connected to the pre-charging control signal, and whose drain is connected to the local signal line; a second P-type transistor, whose source is connected to the power supply voltage, whose gate is connected to the pre-charging control signal, and whose drain is connected to the complementary local signal line; and a third P-type transistor, whose first end is connected to the complementary local signal line, whose second end is connected to the local signal line, and whose control end is connected to the pre-charging control signal.

[0017] In an exemplary embodiment of the present disclosure, the read-write assist circuit includes: a fourth P-type transistor, whose source is connected to a power supply voltage; a fifth P-type transistor, whose source is connected to the power supply voltage, whose gate is connected to the source of the fourth P-type transistor, and whose source is connected to the gate of the fourth P-type transistor; an eleventh N-type transistor, whose drain is connected to the source of the fourth P-type transistor, and whose gate is connected to the source of the fifth P-type transistor; a twelfth N-type transistor, whose drain is connected to the source of the fifth P-type transistor, whose gate is connected to the source of the fourth P-type transistor, and whose source is connected to the source of the eleventh N-type transistor; and a thirteenth N-type transistor, whose drain is connected to the source of the eleventh N-type transistor, whose gate is connected to the enable signal, and whose source is grounded.

[0018] According to a second aspect of the present disclosure, a memory is provided, comprising the memory structure described in any one of the above items.

[0019] In the disclosed embodiment, a spare memory array and a first sense amplifier array are provided next to the memory array, and the first sense amplifier array is simultaneously connected to both the odd-bit global signal line and the even-bit global signal line. When the memory array or the sense amplifier array is damaged, the first sense amplifier array and the spare memory array are automatically used to replace it. This improves the reliability and factory test success rate of the memory product, increases the product yield, and reduces the production and use costs of the memory product.

[0020] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0022] Figure 1 FIG. 1 is a schematic diagram of a memory structure in an exemplary embodiment of the present disclosure.

[0023] Figure 2 It is a structural diagram of a memory structure in one embodiment of the present disclosure.

[0024] Figure 3 It is a structural diagram of a memory structure in one embodiment of the present disclosure.

[0025] Figure 4 It is a schematic diagram of the storage array control circuit.

[0026] Figure 5 Schematic diagram of the working principle of the backup read-write conversion circuit in the embodiment of the present disclosure.

[0027] Figure 6 2 is a circuit diagram of the backup read-write conversion circuit 181 in the backup read-write conversion circuit in the embodiment of the present disclosure.

[0028] Figure 7 2 is a schematic diagram of a backup read-write conversion circuit 181 in another embodiment of the present disclosure.

[0029] Figure 8 2 is a schematic diagram of a backup read-write conversion circuit 181 in another embodiment of the present disclosure.

[0030] Figure 9 is a schematic diagram of a memory structure in another embodiment of the present disclosure.

[0031] Figure 10 Schematic diagram of a storage circuit with a redundant replacement function in one embodiment of the present disclosure. DETAILED DESCRIPTION

[0032] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that the present disclosure will be more comprehensive and complete and will fully convey the concepts of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced while omitting one or more of the specific details, or that other methods, components, devices, steps, etc. may be employed. In other cases, well-known technical solutions are not shown or described in detail to avoid obscuring various aspects of the present disclosure.

[0033] The accompanying drawings are merely schematic illustrations of the present disclosure. Identical reference numerals in the drawings denote identical or similar components, and thus their repeated descriptions will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities that do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software, in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0034] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0035] Figure 1 FIG. 1 is a schematic diagram of a memory structure in an exemplary embodiment of the present disclosure.

[0036] refer to Figure 1 , the memory structure 100 may include:

[0037] Multiple memory arrays 11 are arranged in parallel along a first direction and extend along a second direction. A sense amplifier array extending along the second direction is disposed between every two memory arrays 11. The sense amplifier arrays include odd-bit sense amplifier arrays 12 and even-bit sense amplifier arrays 13. The odd-bit sense amplifier arrays 12 and even-bit sense amplifier arrays 13 are arranged alternately along the first direction. The odd-bit sense amplifier arrays 12 are connected to odd-bit global signal lines, while the even-bit sense amplifier arrays 13 are connected to even-bit global signal lines. It should be noted that the first direction is the direction in which the bit lines extend, and the second direction is the direction in which the word lines extend. Figure 1 The storage array 11 shown may be, for example, a rank (row).

[0038] A spare memory array 14 is disposed on one side of the memory array 11 located at the edge in a first direction. A first sense amplifier array 15 is disposed between the spare memory array 14 and the memory array 11 located at the edge. The first sense amplifier array 15 is connected to both the odd-bit global signal lines and the even-bit global signal lines. Because it is connected to both the odd-bit global signal lines and the even-bit global signal lines, the first sense amplifier array 15 can simultaneously control the spare memory array 14 and the memory array 11 located at the edge. When a failure is detected in any memory array 11, the spare memory array 14 can be read and written by controlling the first sense amplifier array 15, thereby replacing the failed memory array. When a failure is detected in any odd-bit sense amplifier array 12 or even-bit sense amplifier array 13, the first sense amplifier array 15 can be used to replace the failed sense amplifier array.

[0039] Since the sense amplifier array reads and writes half of the memory array, in one embodiment, two spare memory arrays 14 and two first sense amplifier arrays 14 can be used to replace a faulty memory array or a faulty sense amplifier array.

[0040] Figure 2 It is a structural diagram of a memory structure in one embodiment of the present disclosure.

[0041] refer to Figure 2 In one embodiment, the number of the spare memory arrays 14 is two, and they are respectively arranged beside the two memory arrays 11 located at the edge. Correspondingly, the number of the first sense amplifier arrays 15 is also two. Figure 2 In the embodiment shown, the number of spare memory arrays 14 is the same as the number of first sense amplifier arrays 15. When more spare memory arrays 14 are provided, those skilled in the art can connect the first sense amplifier arrays 15 according to the above rule. It is understandable that when more than two spare memory arrays 14 are provided, Figure 2 Other spare memory arrays 14 are provided next to the spare memory array 14 shown. Figure 1 Similarly, the first sense amplifier array 15 can be set on the right side or the left side of the spare memory array 14, that is, the relative positions of the first sense amplifier array 15 and the spare memory array 14 can be interchanged, and the present disclosure does not impose any special restrictions on this.

[0042] In practical applications, Figure 1 or Figure 2 The structure shown can replace the failed storage array when a storage array fails.

[0043] A storage array failure can be determined based on the test results of the storage array detection circuit. For example, a faulty storage array can be determined based on a storage array failure message generated during the test of the storage product. Alternatively, a storage array failure can be determined by triggering a test of the storage array in various ways (e.g., periodically or at each power-on) during the use of the storage product.

[0044] Since a storage array typically has multiple storage sub-arrays (bolcks), and each storage sub-array typically has multiple storage cells (cells), it is possible to determine, based on general product settings, when a certain number of storage cells or storage sub-arrays are faulty (e.g., 30% are faulty) before the storage array is deemed faulty. The presently disclosed embodiments do not limit the specific triggering logic for determining a storage fault.

[0045] There may be one or more faulty storage arrays. When the number of faulty storage arrays is less than half the number of spare storage arrays, the spare storage arrays may be used to replace the faulty storage arrays. When the number of faulty storage arrays is greater than or equal to half the number of spare storage arrays, the faulty storage arrays to be replaced by spare storage arrays may be determined based on the importance of the faulty storage array's location (e.g., center or edge) or the degree of damage (e.g., the percentage of storage cells or storage sub-arrays that have failed).

[0046] To further illustrate the replacement function of the spare storage array 14 and the first sense amplifier array 15 in the present disclosure, the following is a Figure 3 and Figure 4 The data line connection relationship in the exemplary embodiment of the present disclosure is described.

[0047] Figure 3 It is a structural diagram of a memory structure in one embodiment of the present disclosure.

[0048] refer to Figure 3 In one embodiment, each memory array 11 includes a plurality of memory sub-arrays 111 arranged along the second direction, the odd-bit sense amplifier array 12 includes a plurality of odd-bit sense amplifier sub-arrays 121, and the even-bit sense amplifier array 13 includes a plurality of even-bit sense amplifier sub-arrays 131. The odd-bit sense amplifier sub-array 121 or the even-bit sense amplifier sub-array 131 corresponds to the memory sub-array 111.

[0049] Each odd-bit sensitive amplifier sub-array 121 is electrically connected to multiple odd-bit global signal lines through an odd-bit read-write conversion circuit, and all odd-bit read-write conversion circuits corresponding to an odd-bit sensitive amplifier array 12 constitute an odd-bit read-write conversion circuit array 16; each even-bit sensitive amplifier sub-array 131 is electrically connected to multiple even-bit global signal lines through an even-bit read-write conversion circuit, and all even-bit read-write conversion circuits corresponding to an even-bit sensitive amplifier array 13 constitute an even-bit read-write conversion circuit array 17.

[0050] Spare memory array 14 includes multiple first spare memory sub-arrays 141, and first sense amplifier array 15 includes multiple first sense amplifier sub-arrays 151. Each first spare memory sub-array 141 corresponds to a first sense amplifier sub-array 151. Each first sense amplifier sub-array 151 is electrically connected to both the odd-bit global signal line and the even-bit global signal line via a spare read-write conversion circuit. The spare read-write conversion circuits corresponding to one first sense amplifier array 15 form a spare read-write conversion circuit array 18. It will be understood that the odd-bit read-write conversion circuit array 16 is connected to the odd-bit read control signal line and the odd-bit write control signal line, the even-bit read-write conversion circuit array 17 is connected to the even-bit read control signal line and the even-bit write control signal line, and the spare read-write conversion circuit array 18 is connected to all three control signal lines. The control signal lines are not shown in the figure.

[0051] Figure 4 It is a schematic diagram of the storage array control circuit.

[0052] refer to Figure 4 The memory array control circuit mainly includes a row decoding and control circuit 41 (XDEC, X Decoder), a column decoding circuit 42 (YDEC, Y Decoder), and a read amplifier circuit and a write driver circuit 43. The column decoding circuit 42 is used to provide a column select signal (CSL, Column Select). The read amplifier circuit and the write driver circuit 43 include a read amplifier circuit (secondsense amplifier, SSA) and a write driver circuit (write driver). The read amplifier circuit and the write driver circuit are both connected to the global signal line YIO and the complementary global signal line YIO#. The global signal line YIO and the complementary global signal line YIO# appear in pairs, and a pair of global signal line YIO and complementary global signal line YIO# constitutes Figure 1 、 Figure 2 or Figure 3 The relationship between the global signal lines and the storage array 11 and the odd-bit sense amplifier array 12, the even-bit sense amplifier array 13, the odd-bit read-write conversion circuit array 16 and the even-bit read-write conversion circuit array 17 is shown in FIG. Figure 4 A magnified detail on the right.

[0053] When a word line (WL) is selected by the XDEC row decoding and control circuit 41, data from the corresponding memory array 11 is transmitted to the odd-bit sense amplifier array 12 and even-bit sense amplifier array 13 located on either side of the memory array. After amplification by the odd-bit sense amplifier array 12 and even-bit sense amplifier array 13, the data is written back to the memory cells connected to the selected WL. When data needs to be modified or rewritten, the column decoding circuit 42 selects the corresponding sense amplifier. The data is then transmitted from a set of YIO & YIO# global signal lines through a read-write conversion circuit (lrwap) to a set of Ldat & Ldat# local signal lines, where it is written to the corresponding sense amplifier and the connected memory cells. During data readout, the data transmission direction is reversed. The YDEC column decoder circuit 42 selects the corresponding sense amplifier and transmits the data to a set of local signal lines Ldat and Ldat#. The data is then transferred to a set of global signal lines YIO and YIO# by the read-write converter circuit (lrwap) connected to the sense amplifier. Finally, it is amplified and output by the read amplifier circuit and the SSA in the write driver circuit 43. During operation, YIO and YIO# are paired in a dual-phase manner, with opposite and complementary polarities in both read and write modes.

[0054] As you can see, Figure 4 Each odd-bit read-write conversion circuit 161 is connected to an odd-bit global signal line (e.g., YIOn+1, YIOn+3), a complementary odd-bit global signal line (YIOn+1#, YIOn+3#), and a set of Ldat & Ldat# signal lines. Multiple odd-bit read-write conversion circuits 161 constitute an odd-bit read-write conversion circuit array 16. Each even-bit read-write conversion circuit 171 is connected to an even-bit global signal line (YIOn, YIOn+2), a complementary even-bit global signal line (YIOn#, YIOn+2#), and a set of Ldat & Ldat# signal lines. Multiple even-bit read-write conversion circuits 171 constitute an even-bit read-write conversion circuit array 17. The aforementioned n is an even number greater than or equal to zero. In some embodiments, the odd-bit read-write conversion circuit 161 may not be connected to the complementary odd-bit global signal line, that is, the complementary odd-bit global signal line is not set. Similarly, the even-bit read-write conversion circuit 171 may not be connected to the complementary even-bit global signal line, that is, the complementary even-bit global signal line is not set. The present disclosure does not make any special limitations on this.

[0055] From the perspective of the storage unit, the odd-bit sense amplifier array 12 or the even-bit sense amplifier array 13 includes multiple sense amplifier sub-arrays, each of which controls half of the storage array 11 on the left and right sides. Figure 4 The line that runs through the memory array is the bit line (BL). Figure 4 Combine Figure 3It can be seen that half of the memory cells in the spare memory array 14 are controlled by the first sense amplifier array 15 connected to the spare memory array 14. Using two first sense amplifier arrays 15 to control two spare memory arrays 14 respectively can achieve replacement of a complete memory array 11.

[0056] Specifically, when a storage array 11 fails, a first sense amplifier array 15 is controlled to exchange data with the odd-bit global signal lines connected to the odd-bit sense amplifier array corresponding to the failed storage array, so that a spare storage array 14 is used to replace the storage cells of half of the failed storage array; and another first sense amplifier array 15 is controlled to exchange data with the even-bit global signal lines connected to the even-bit sense amplifier array corresponding to the failed storage array, so that another spare storage array 14 is used to replace the storage cells of the other half of the failed storage array.

[0057] In addition, when the sense amplifier array is damaged, the embodiment of the present disclosure can also use the first sense amplifier array 15 and the spare memory array 14 to replace the two memory arrays 11 affected by the faulty sense amplifier array.

[0058] When a sense amplifier array (either the odd-bit sense amplifier array 12 or the even-bit sense amplifier array 13) fails, half of the memory cells in each of the two memory arrays 11 controlled by it are affected. Therefore, when a sense amplifier array failure is determined, one spare memory array 14 can be used to replace the half of the memory cells in the memory array 11 that are unable to operate normally due to the faulty sense amplifier, and another spare memory array 14 can be used to replace the other half of the memory cells in the memory array 11 that are unable to operate normally due to the faulty sense amplifier.

[0059] In a specific implementation, if an error occurs in a whole block of sense amplifier arrays, such as an odd-bit sense amplifier array 12, the sense amplifiers in the array exchange data with the odd-bit global signal lines. Therefore, when replacing the sense amplifiers, the two first sense amplifier arrays 15 corresponding to the two spare memory arrays 14 and the half connected to the spare memory array 14 are used as odd-bit sense amplifier arrays and exchange data with the odd-bit global signal lines corresponding to the faulty odd-bit sense amplifier array 12. When it is determined that data needs to be exchanged with an affected memory array 11 via the faulty sense amplifier array, word lines WL are set to select the memory array 11 and its corresponding spare memory array 14, and the first sense amplifier array 15 connected to the spare memory array 14 is controlled to exchange data with the odd-numbered global signal lines connected to the faulty sense amplifier (the memory array 11 connected to the first sense amplifier 15 can be deselected in this case). When it is determined that data needs to be exchanged with another affected memory array 11 via the faulty sense amplifier array, word lines WL are set to select the memory array 11 and its corresponding spare memory array 14, and the first sense amplifier array 15 connected to the spare memory array 14 is controlled to exchange data with the odd-numbered global signal lines connected to the faulty sense amplifier. The connection between the spare memory array 14 and word lines WL is the same as the connection between the memory array 11 and word lines WL.

[0060] Similarly, if the even-bit sense amplifier array 13 fails and is replaced, the two first sense amplifier arrays 15 corresponding to the two spare storage arrays 14 and the half connected to the spare storage array 14 also need to be used as the even-bit sense amplifier array and exchange data with the even-bit global signal line corresponding to the failed even-bit sense amplifier array 13.

[0061] As can be seen from the above description, the first sense amplifier array 15 must function as both an odd-bit sense amplifier array and an even-bit sense amplifier array. Therefore, it is necessary to modify the control method of each sense amplifier in the first sense amplifier array 15, that is, to modify the backup read-write conversion circuit.

[0062] Figure 5 Schematic diagram of the working principle of the backup read-write conversion circuit in the embodiment of the present disclosure.

[0063] refer to Figure 5The odd-bit read / write conversion circuit 161 or the even-bit read / write conversion circuit 171 connects a pair of local signal lines Ldat and a complementary local signal line Ldat# to an odd-bit sense amplifier subarray 121 or an even-bit sense amplifier subarray 131. Each read / write conversion circuit connects a pair of local signal lines Ldat and a complementary local signal line Ldat#, as well as a pair of signal lines YIO and YIO#. The odd-bit read / write conversion circuit 161 connects an odd-bit global signal line YIOn+1 and a complementary odd-bit global signal line YIOn+1#, while the even-bit read / write conversion circuit 171 connects an even-bit global signal line YIOn and a complementary even-bit global signal line YIOn#. In some embodiments, each read-write conversion circuit may also be connected only to the YIO signal line, that is, in some embodiments, the odd-bit read-write conversion circuit 161 may not be connected to the complementary odd-bit global signal line YIOn+1#. Similarly, the even-bit read-write conversion circuit 171 may not be connected to the complementary even-bit global signal line YIOn#. The present disclosure does not make any special limitations on this.

[0064] A pair of signal lines of a spare read-write conversion circuit 181 is connected to a spare sense amplifier sub-array 151. Multiple spare read-write conversion circuits 181 corresponding to a first sense amplifier array 15 constitute a spare read-write conversion circuit array 18. The spare read-write conversion circuits 181 are connected to both odd-bit global signal lines and even-bit global signal lines, thereby enabling the spare memory array 14 to be controlled to flexibly replace a faulty memory array or a memory array affected by a faulty sense amplifier array.

[0065] Figure 6 2 is a circuit diagram of the backup read-write conversion circuit 181 in an embodiment of the present disclosure.

[0066] refer to Figure 6 , the standby read-write conversion circuit 181 may include:

[0067] Even-bit read control circuit 61, connected to even-bit global signal line YIOn, even-bit read control signal line Rdn and complementary local signal line Ldat#;

[0068] Even-bit write control circuit 62, connected to even-bit global signal line YIOn, even-bit write control signal line Wrn, and complementary local signal line Ldat# and local signal line Ldat;

[0069] The odd-bit read control circuit 63 is connected to the odd-bit global signal line YIOn+1, the odd-bit read control signal line Rdn+1 and the local signal line Ldat;

[0070] The odd-bit write control circuit 64 is connected to the odd-bit global signal line YIOn+1, the odd-bit write control signal line Wrn+1, and the complementary local signal line Ldat# and the local signal line Ldat.

[0071] exist Figure 6 In the illustrated embodiment, the even-bit read control circuit 61 includes a first N-type transistor M1 and a second N-type transistor M2, wherein the drain of the first N-type transistor M1 is connected to the odd-bit global signal line YIOn+1, and the gate is connected to the complementary local signal line Ldat#; the drain of the second N-type transistor M2 is connected to the source of the first N-type transistor M1, the gate is connected to the even-bit read control signal line Rdn, and the source is grounded.

[0072] The even-bit write control circuit 62 includes a third N-type transistor M3, a fourth N-type transistor M4, and a fifth N-type transistor M5. The first end of the third N-type transistor M3 is connected to the odd-bit global signal line YIOn+1, the second end is connected to the local signal line Ldat, and the gate is connected to the even-bit write control signal line Wrn. The drain of the fourth N-type transistor M4 is connected to the local signal line Ldat, and the gate is connected to the odd-bit global signal line YIOn+1. The drain of the fifth N-type transistor M5 is connected to the source of the fourth N-type transistor M4, the gate is connected to the even-bit write control signal line Wrn, and the source is grounded.

[0073] The odd-bit read control circuit 63 includes: a sixth N-type transistor M6 and a seventh N-type transistor M7, the drain of the sixth N-type transistor M6 is connected to the even-bit global signal line YIOn, and the gate is connected to the local signal line Ldat, the drain of the seventh N-type transistor M7 is connected to the source of the sixth N-type transistor M6, the gate is connected to the odd-bit read control signal line Rdn+1, and the source is grounded.

[0074] The odd-bit write control circuit 64 includes an eighth N-type transistor M8, a ninth N-type transistor M9, and a tenth N-type transistor M10. The first end of the eighth N-type transistor M8 is connected to the even-bit global signal line YIOn, the second end is connected to the complementary local signal line Ldat#, and the gate is connected to the odd-bit write control signal line Wrn+1. The drain of the ninth N-type transistor M9 is connected to the complementary local signal line Ldat#, and the gate is connected to the even-bit global signal line YIOn. The drain of the tenth N-type transistor M10 is connected to the source of the ninth N-type transistor M9, the gate is connected to the odd-bit write control signal line Wrn+1, and the source is grounded.

[0075] When the circuit is in the even-bit reading state, after pre-charging the even-bit global signal line YIOn (the pre-charging circuit of the signal line YIO is not shown), the even-bit read control signal line Rdn enables the second N-type transistor M2 to turn on. When the complementary local signal line Ldat# is at a high potential and the local signal line Ldat is at a low potential, the first N-type transistor M1 is turned on, and the local signal line Ldat is transmitted to the even-bit global signal line YIOn through the ground voltage connected to the second N-type transistor M2. The voltage of the even-bit global signal line YIOn becomes a low potential. At this time, the even-bit global signal line YIOn reads the data on the local signal line Ldat. When the complementary local signal line Ldat# is at a low potential and the local signal line Ldat is at a high potential, the first N-type transistor M1 is turned off. At this time, the ground voltage connected to the second N-type transistor M2 cannot be transmitted to the even-bit global signal line YIOn. The even-bit global signal line YIOn maintains a precharged high potential, and the even-bit global signal line YIOn reads the data on the local signal line Ldat. When the circuit is in the even-bit write state, the even-bit write control signal Wrn enables the third N-type transistor M3 and the fifth N-type transistor M5. At this time, if the even-bit global signal line YIOn is at a high potential, the fourth N-type transistor M4 turns on, the complementary local signal line Ldat# goes low, and the local signal line Ldat maintains a precharged high potential. If the even-bit global signal line YIOn is at a low potential, the fourth N-type transistor M4 turns off, the complementary local signal line Ldat# remains at a precharged high potential, and the local signal line Ldat goes low. The reading and writing principles for odd-bits are the same and will not be further described here. As can be seen from the above, after receiving different read-write control signals, the backup read-write conversion circuit can read and write even bits or odd bits, so that the odd-numbered or even-numbered bits can be written to or read from the backup storage array according to different read-write control signals.

[0076] Figure 7 2 is a schematic diagram of a backup read-write conversion circuit 181 in another embodiment of the present disclosure.

[0077] refer to Figure 7 In an exemplary embodiment of the present disclosure, the standby read / write conversion circuit 181 may further include a precharge circuit 71. The precharge circuit 71 is connected to the complementary local signal line Ldat#, the local signal line Ldat, the power supply voltage Vcc, and the precharge signal Pre. The precharge circuit 71 is used to pull up the complementary local signal line Ldat# and the local signal line Ldat, and precharge the complementary local signal line Ldat# and the local signal line Ldat.

[0078] exist Figure 7 In the illustrated embodiment, the pre-charging circuit 71 may include:

[0079] A first P-type transistor M11, having a source connected to the power supply voltage Vcc, a gate connected to the pre-charge control signal Pre, and a drain connected to the local signal line Ldat;

[0080] A second P-type transistor M12, having a source connected to the power supply voltage Vcc, a gate connected to the precharge control signal Pre, and a drain connected to the complementary local signal line Ldat#;

[0081] The third P-type transistor M13 has a first end connected to the complementary local signal line Ldat#, a second end connected to the local signal line Ldat, and a control end connected to the pre-charge control signal Pre.

[0082] In the embodiment of the present disclosure, a pre-charge circuit 71 is provided to enable the first P-type transistor M11 and the second P-type transistor M12 by outputting a pre-charge control signal Pre before writing, thereby pre-charging the complementary local signal line Ldat# and the local signal line Ldat

[0083] By pulling up the complementary local signal line Ldat# and the local signal line Ldat, the threshold loss of signal transmission can be avoided, thereby achieving a better signal transmission effect.

[0084] Figure 8 2 is a schematic diagram of a backup read-write conversion circuit 181 in another embodiment of the present disclosure.

[0085] refer to Figure 8 In an exemplary embodiment of the present disclosure, the backup read-write conversion circuit 181 also includes a read-write auxiliary circuit 81, which connects the complementary local signal line Ldat#, the local signal line Ldat and the enable signal. The read-write auxiliary circuit 81 is used to amplify the complementary local signal line Ldat# and the local signal line Ldat.

[0086] exist Figure 8 In the illustrated embodiment, the read / write assist circuit 81 includes:

[0087] a fourth P-type transistor M14, a source of which is connected to a power supply voltage;

[0088] a fifth P-type transistor M15, having a source connected to the power supply voltage, a gate connected to the source M14 of the fourth P-type transistor, and a source connected to the gate of the fourth P-type transistor M14;

[0089] an eleventh N-type transistor M16, having a drain connected to the source of the fourth P-type transistor M14 and a gate connected to the source of the fifth P-type transistor M15;

[0090] a twelfth N-type transistor M17, having a drain connected to the source of the fifth P-type transistor M15, a gate connected to the source of the fourth P-type transistor M14, and a source connected to the source of the eleventh N-type transistor M16;

[0091] The thirteenth N-type transistor M18 has a drain connected to the source of the eleventh N-type transistor M16 , a gate connected to the enable signal En, and a source grounded.

[0092] The read / write assist circuit 81 can amplify the complementary local signal line Ldat# and the local signal line Ldat when the enable signal En is in the enabled state, so as to achieve a better signal transmission effect.

[0093] When a storage array fails, the spare storage array 14 and the first sense amplifier array 15 are automatically used to replace the faulty storage array. When a sense amplifier array fails, the spare storage array 14 and the first sense amplifier array 15 are automatically used to replace the two storage arrays affected by the faulty sense amplifier. This not only effectively improves the reliability of the memory product, but also increases the test success rate and yield rate of the memory product, thereby reducing production costs.

[0094] Figure 9 is a schematic diagram of a memory structure in another embodiment of the present disclosure.

[0095] refer to Figure 9 In one embodiment of the present disclosure, a second spare memory sub-array 91 is further provided in the memory array 11, and a spare sense amplifier sub-array 92 is provided between the second spare memory sub-arrays 91 of adjacent memory arrays 11. The spare sense amplifier sub-arrays 92 located in different odd-bit sense amplifier arrays 12 are all electrically connected to the same spare odd-bit global signal line, and the spare sense amplifier sub-arrays 92 located in different even-bit sense amplifier arrays 13 are all electrically connected to the same spare even-bit global signal line.

[0096] At the same time, the spare memory array 14 also includes a second spare memory sub-array 91. The second spare memory sub-array 91 is provided with a corresponding spare first sense amplifier sub-array 93 located in the first sense amplifier array 15. The spare first sense amplifier sub-array 93 is connected to the spare odd-bit global signal line and the spare even-bit global signal line simultaneously through the spare read-write conversion circuit array 18.

[0097] exist Figure 9In the illustrated embodiment, the number of second spare storage sub-arrays 91 in both the storage array 11 and the spare storage array 14 is one. In other embodiments, more second spare storage sub-arrays 91 may be provided in each storage array. Furthermore, the second spare storage sub-arrays 91 may be located at various positions within the storage array, with each second spare storage sub-array 91 having the same position within each storage array. In one exemplary embodiment of the present disclosure, the second spare storage sub-array 91 is located in the middle of the storage array 11 or the spare storage array 14. Those skilled in the art may adjust the number and position of the second spare storage sub-arrays 91 based on practical circumstances, and this disclosure does not impose any particular limitations thereon.

[0098] refer to Figure 9 When a major failure occurs at a critical location related to a column, the column of storage subarrays B (also called a column block) where the faulty storage subarray resides can be disabled first, and then a column of second spare storage subarrays A from each storage array can be used for repair and replacement. At this time, if spare storage array 14 is enabled, the column of second spare storage subarrays A includes the second spare storage subarrays 91 from each storage array 11 and the second spare storage subarrays 91 from the spare storage arrays 14. If spare storage array 14 is not enabled, the column of second spare storage subarrays A includes only the second spare storage subarrays 91 from each storage array 11.

[0099] In the peripheral circuit, when data needs to be written to a column of memory sub-arrays B that includes a faulty memory sub-array, data can be read and written to a column of second spare memory sub-arrays A in the entire memory array 11 to replace the column of memory sub-arrays B containing the faulty memory sub-array. During reading, the YIO data read from the column of second spare memory sub-arrays A needs to be controlled and output to the corresponding position of the column of memory sub-arrays being replaced.

[0100] The replacement function of column A for column B can replace the entire column A with the partial column B. For example, when accessing one storage array, the second spare storage sub-array in column A can replace the faulty storage sub-array in column B; when accessing another storage array, the second spare storage sub-array in column A can replace the faulty storage sub-array in column C.

[0101] Figure 10 Schematic diagram of a storage circuit with a redundant replacement function in one embodiment of the present disclosure.

[0102] refer to Figure 10In memory circuit 1000, an odd-bit sense amplifier array 12 and an even-bit sense amplifier array 13 are disposed between memory arrays 11. A spare memory array 14 and a first sense amplifier array 15 are disposed adjacent to the memory arrays 11 at the edges. Furthermore, memory circuit 1000 includes a column decoding circuit (YDEC) 101, a sense amplifier data write driver circuit (YIO SA&write driver) 102, and multiple data selectors (MUX, multiplexers) 103. The sense amplifier data write driver circuit 102 includes multiple sense amplifier data write circuits 1021.

[0103] Each sense amplifier data write circuit 1021 is connected to an odd-bit global signal line 104 or an even-bit signal line 105, and is also connected to a data selector 103. The other end of the data selector 103 is connected to the data bus 110 and is controlled by control logic and column block repair logic. Data is written to the odd-bit global signal line 104 or the even-bit global signal line 105 via the sense amplifier data write circuit 1021.

[0104] The memory circuit 1000 is divided into a plurality of column blocks in the second direction. Each block includes a memory sub-array and a sense amplifier sub-array located in the same column, such as column blocks 10B, 10C, and 10D. Each column block is connected to four odd-bit global signal lines 104 and four even-bit global signal lines 105, which means that 8 bits of data can be transmitted. Specifically, an odd-bit sense amplifier sub-array is connected to four odd-bit global signal lines via four read-write conversion circuits, and an even-bit sense amplifier sub-array is connected to four even-bit global signal lines via four read-write conversion circuits. The number of odd-bit global signal lines 104 and even-bit global signal lines 105 connected in each column block can be changed according to the storage capacity or storage processing capability of the memory array, but the present disclosure is not limited thereto.

[0105] The odd bit global signal line 104 is electrically connected to the odd bit sense amplifier array 12 through the odd bit connection point 106 (specifically, the odd bit global signal line 104 is electrically connected to the odd bit sense amplifier array 12 through the odd bit read-write conversion circuit). Figure 3 The even bit global signal line 105 is electrically connected to the even bit sense amplifier array 13 through the even bit connection point 107 (specifically, the even bit global signal line 105 is electrically connected to the even bit sense amplifier array 13 through the even bit read-write conversion circuit). Figure 3In addition, the odd bit global signal line 104 and the even bit global signal line 105 are electrically connected to the first sense amplifier array 15 through the odd bit connection point 106 and the even bit connection point 107. Figures 6 to 8 The circuit shown in FIG. 1 is not described in detail in this disclosure.

[0106] Spare column block area A includes multiple second spare memory sub-arrays and spare sense amplifier sub-arrays located in the same column. In some embodiments, when the spare memory array and the first sense amplifier array are enabled, spare column block area 10A also includes a first spare memory sub-array in the spare memory array and a spare first sense amplifier sub-array in the first sense amplifier array. The spare sense amplifier sub-arrays in the odd-bit sense amplifier array 12 are all electrically connected to the same four spare odd-bit global signal lines 108, while the spare sense amplifier sub-arrays in the even-bit sense amplifier array 13 are electrically connected to the same four spare even-bit global signal lines 109. The spare first sense amplifier sub-array is also electrically connected to both the four spare odd-bit global signal lines 108 and the four spare even-bit global signal lines 109. Spare column block area 10A is connected to a total of four spare odd-bit global signal lines 108 and four even-bit global signal lines 109, meaning it can transmit eight bits of data. The number of odd-bit global signal lines 108 and even-bit global signal lines 109 connected to the spare column block area 10A can be changed according to the storage capacity or storage processing capability of the memory array, which is the same as the column block areas 10B, 10C, and 10D. It can be understood that in some embodiments, the number of column blocks can be 16 (excluding the spare column block A). The spare odd-bit global signal lines 108 or the spare even-bit global signal lines 109 are connected to the spare sense amplifier subarray ( Figure 10 The connection method of the position where the middle dashed box intersects with the odd-bit sense amplifier array 12 or the even-bit sense amplifier array 13 is the same as that of other odd-bit global signal lines or even-bit global signal lines corresponding to the sense amplifier array where the spare sense amplifier sub-array is located, and will not be repeated here.

[0107] The relative positions and number of the spare column block areas 10A are merely examples. In other embodiments of the present disclosure, the spare column block areas 10A may be located at other positions, and the number may be equal to or greater than two.

[0108] When any of the column blocks 10B, 10C, or 10D is damaged (for example, the number of inoperable memory subarrays and / or sense amplifier subarrays exceeds a preset threshold), the damaged column block 10B, 10C, or 10D can be replaced entirely with the spare column block 10A. Specifically, the column block replacement logic configures the data selector 103 so that the data originally corresponding to the damaged column block 10B, 10C, or 10D is transferred to the spare column block 10A. The control logic then controls the data output of the data selector 103. Enabling the column block or spare column block can be accomplished using the column select signal (CSL) corresponding to each column.

[0109] Similarly, when any of the memory array 11, odd-bit sense amplifiers 12, or even-bit sense amplifiers 13 is damaged, the spare memory array 14 or first sense amplifier array 15 can be used as a replacement, thereby achieving row-wise replacement. In one embodiment, row block repair logic can be used to control the enabling or disabling of the memory array 11, odd-bit sense amplifiers 12, even-bit sense amplifiers 13, spare memory array 14, and first sense amplifier array 15, thereby correctly transferring data to the memory array or spare memory array.

[0110] With the memory structure provided by the embodiments of the present disclosure, large-area manufacturing errors, whether column-related or row-related, can be repaired by replacing the entire block together, thereby improving the repair capability and the yield and success rate of the chip, which is especially effective for the early research and development of new processes.

[0111] According to a second aspect of the present disclosure, a memory is provided, comprising the memory structure of any one of the above items.

[0112] It should be noted that although several modules or units of the device for action execution are mentioned in the detailed description above, this division is not mandatory. In fact, according to the embodiments of the present disclosure, the features and functions of two or more modules or units described above can be concretized in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided into multiple modules or units to be concretized.

[0113] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the claims.

Claims

1. A memory structure, characterized in that: include: a plurality of memory arrays arranged in parallel along a first direction and extending along a second direction, a sense amplifier array extending along the second direction being arranged between every two memory arrays, the sense amplifier array comprising an odd-bit sense amplifier array and an even-bit sense amplifier array, the odd-bit sense amplifier array and the even-bit sense amplifier array being arranged alternately along the first direction, the odd-bit sense amplifier array being connected to an odd-bit global signal line, and the even-bit sense amplifier array being connected to an even-bit global signal line; a spare memory array, disposed on a side of the memory array located at an edge in the first direction, with a first sense amplifier array disposed between the spare memory array and the edge memory array, the first sense amplifier array being connected to both the odd-numbered global signal lines and the even-numbered global signal lines; Each of the memory arrays includes a plurality of memory sub-arrays arranged along the second direction, each of the sense amplifier arrays includes a plurality of sense amplifier sub-arrays, each of the sense amplifier sub-arrays is connected to a read-write conversion circuit, and the sense amplifier sub-arrays correspond one-to-one to the memory sub-arrays, each of the odd-bit sense amplifier arrays is electrically connected to a plurality of odd-bit global signal lines via a plurality of the read-write conversion circuits, and each of the even-bit sense amplifier arrays is electrically connected to a plurality of even-bit global signal lines via a plurality of the read-write conversion circuits; The spare memory array includes a plurality of first spare memory sub-arrays, the first sense amplifier array includes a plurality of first sense amplifier sub-arrays, each of the first spare memory sub-arrays corresponds to one first sense amplifier sub-array, and the first sense amplifier sub-arrays are electrically connected to the odd-bit global signal line and the even-bit global signal line via a spare read-write conversion circuit; The standby read-write conversion circuit includes: an even-bit read control circuit connected to the even-bit global signal line, the even-bit read control signal line, and the complementary local signal line; an even-bit write control circuit, connected to the even-bit global signal line, the even-bit write control signal line, the complementary local signal line, and the local signal line; an odd-bit read control circuit connected to the odd-bit global signal line, the odd-bit read control signal line, and the local signal line; The odd-bit write control circuit is connected to the odd-bit global signal line, the odd-bit write control signal line, the complementary local signal line, and the local signal line.

2. The memory structure according to claim 1, wherein: There are two spare storage arrays, which are respectively arranged beside the two storage arrays located at the edge.

3. The memory structure according to any one of claims 1 to 2, wherein: Each of the storage arrays and the spare storage array includes a second spare storage sub-array, which is arranged along the first direction. The sense amplifier array also includes a spare sense amplifier sub-array, which is located between two adjacent second spare storage sub-arrays.

4. The memory structure according to claim 3, wherein: The number of the second spare storage sub-array in each of the storage arrays or the spare storage array is one.

5. The memory structure according to claim 3, wherein: The spare sense amplifier sub-arrays in the odd-bit sense amplifier array are electrically connected to the same spare odd-bit global signal line; the spare sense amplifier sub-arrays in the even-bit sense amplifier array are electrically connected to the same spare even-bit global signal line.

6. The memory structure according to claim 1, wherein: The standby read-write conversion circuit also includes: A pre-charging circuit is connected to the complementary local signal line, the local signal line, a power supply voltage and a pre-charging signal, and the pre-charging circuit is used to pull up the complementary local signal line and the local signal line.

7. The memory structure according to claim 1, wherein: The standby read-write conversion circuit also includes: A read / write assist circuit is connected to the complementary local signal line, the local signal line, and an enable signal, and is used to amplify the complementary local signal line and the local signal line.

8. The memory structure according to claim 1, wherein: The even-bit read control circuit includes a first N-type transistor and a second N-type transistor, wherein the drain of the first N-type transistor is connected to the odd-bit global signal line, and the gate is connected to the complementary local signal line; the drain of the second N-type transistor is connected to the source of the first N-type transistor, the gate is connected to the even-bit read control signal line, and the source is grounded; the even-bit write control circuit includes a third N-type transistor, a fourth N-type transistor, and a fifth N-type transistor, wherein the first end of the third N-type transistor is connected to the odd-bit global signal line, the second end is connected to the local signal line, and the gate is connected to the even-bit write control signal line; the drain of the fourth N-type transistor is connected to the local signal line, and the gate is connected to the odd-bit global signal line; the drain of the fifth N-type transistor is connected to the source of the fourth N-type transistor, the gate is connected to the even-bit write control signal line, and the source is grounded.

9. The memory structure according to claim 1, wherein: The odd-bit read control circuit includes: The odd-bit read control circuit includes a sixth N-type transistor and a seventh N-type transistor, the drain of the sixth N-type transistor is connected to the even-bit global signal line, the gate is connected to the local signal line, the drain of the seventh N-type transistor is connected to the source of the sixth N-type transistor, the gate is connected to the odd-bit read control signal line, and the source is grounded; the odd-bit write control circuit includes an eighth N-type transistor, a ninth N-type transistor, and a tenth N-type transistor, the first end of the eighth N-type transistor is connected to the even-bit global signal line, the second end is connected to the complementary local signal line, and the gate is connected to the odd-bit write control signal line, the drain of the ninth N-type transistor is connected to the complementary local signal line, the gate is connected to the even-bit global signal line, the drain of the tenth N-type transistor is connected to the source of the ninth N-type transistor, the gate is connected to the odd-bit write control signal line, and the source is grounded.

10. The memory structure according to claim 6, wherein: The pre-charge circuit comprises: a first P-type transistor, having a source connected to a power supply voltage, a gate connected to a precharge control signal, and a drain connected to the local signal line; a second P-type transistor, having a source connected to the power supply voltage, a gate connected to the precharge control signal, and a drain connected to the complementary local signal line; A third P-type transistor has a first end connected to the complementary local signal line, a second end connected to the local signal line, and a control end connected to the pre-charge control signal.

11. The memory structure according to claim 7, wherein: The read-write assist circuit comprises: a fourth P-type transistor, having a source connected to the power supply voltage; a fifth P-type transistor, having a source connected to the power supply voltage, a gate connected to the source of the fourth P-type transistor, and a source connected to the gate of the fourth P-type transistor; an eleventh N-type transistor, having a drain connected to the source of the fourth P-type transistor and a gate connected to the source of the fifth P-type transistor; a twelfth N-type transistor, having a drain connected to the source of the fifth P-type transistor, a gate connected to the source of the fourth P-type transistor, and a source connected to the source of the eleventh N-type transistor; The thirteenth N-type transistor has a drain connected to the source of the eleventh N-type transistor, a gate connected to the enable signal, and a source grounded.

12. A memory, characterized in that: The invention comprises the memory structure according to any one of claims 1 to 11.

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