Memory Read / Write Circuit, Memory Control Method, and Electronic Device

Abstract

The present disclosure relates to a memory read / write circuit, a memory control method, and an electronic device, and relates to the field of integrated circuit technologies. The memory read / write circuit includes: a sense amplifier, the power supply voltage of the sense amplifier is controlled and supplied by a first control signal or a second control signal, and the first power supply voltage controlled and supplied by the first control signal is greater than the second power supply voltage controlled and supplied by the second control signal; a control signal generation module, configured to, in a normal read / write mode, control the pulse duration of the first control signal to be a first duration; in a refresh mode, control the pulse duration of the first control signal to be a second duration, and the second duration is less than the first duration; the control signal generation module is further configured to, in the refresh mode, control the first control signals of multiple memory blocks in the memory to be sequentially turned on. The present disclosure can reduce the instantaneous current in the refresh mode.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuit technologies, and more particularly, to a memory read / write circuit, a memory control method, and an electronic device. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor memory device in computers. Due to its advantages such as simple structure, high density, low power consumption, and low cost, it has been widely used in the computer field and the electronics industry.

[0003] For DRAM, relatively high performance requirements are often imposed during the read / write stage to ensure a good user experience.

[0004] However, during the refresh stage, DRAM does not require the same high performance. Therefore, adopting different control methods during the read / write stage and the refresh stage is of great significance for reducing the power consumption of DRAM.

[0005] It should be noted that the information disclosed in the above background art section is only used to enhance the understanding of the background of the present disclosure, and thus may include information that does not constitute the prior art known to those of ordinary skill in the art. Summary of the Invention

[0006] An object of the present disclosure is to provide a memory read / write circuit, a memory control method, and an electronic device to reduce the instantaneous current of DRAM in the refresh mode.

[0007] Other features and advantages of the present disclosure will become apparent through the following detailed description, or will be partially learned through the practice of the present invention.

[0008] According to a first aspect of the present disclosure, there is provided a memory read / write circuit, including: a sense amplifier, the power supply voltage of the sense amplifier being controlled and supplied by a first control signal or a second control signal, the first power supply voltage controlled and supplied by the first control signal being greater than the second power supply voltage controlled and supplied by the second control signal; a control signal generation module, configured to, in a normal read / write mode, control the pulse duration of the first control signal to be a first duration; in a refresh mode, control the pulse duration of the first control signal to be a second duration, the second duration being less than the first duration; the control signal generation module is further configured to, in the refresh mode, control the first control signals of multiple memory blocks in the memory to be sequentially turned on.

[0009] In an exemplary embodiment of the present disclosure, the control signal generation module is further configured to generate the second control signal when the first control signal terminates in the normal read / write mode or the refresh mode.

[0010] In an exemplary embodiment of the present disclosure, the control signal generation module is further configured to control the pulse duration of the second control signal to be greater than the pulse duration of the first control signal in the normal read / write mode or the refresh mode.

[0011] In an exemplary embodiment of the present disclosure, the second duration is 0.

[0012] In an exemplary embodiment of the present disclosure, the control signal generation module is further configured to directly generate the second control signal without generating the first control signal in the refresh mode, and control the second control signals of multiple storage blocks to be sequentially turned on.

[0013] In an exemplary embodiment of the present disclosure, the negative voltage of the sense amplifier is controlled and supplied by a negative control signal, and the control signal generation module is further configured to control the generation of the negative control signal after generating the first control signal or the second control signal.

[0014] In an exemplary embodiment of the present disclosure, it further includes: a word line, a bit line, and a complementary bit line, and the sense amplifier is disposed between the bit line and the complementary bit line; the control signal generation module is further configured to turn off the bit line balance control signal applied to the bit line and the complementary bit line before generating the first control signal and the second control signal; apply a word line turn-on voltage to the word line to turn on the transistor connected to the word line.

[0015] In an exemplary embodiment of the present disclosure, the control signal generation module is further configured to control the word line turn-on voltages of multiple storage blocks to be sequentially turned on in the refresh mode.

[0016] In an exemplary embodiment of the present disclosure, it further includes: an activation window signal generation module and a refresh window signal generation module, and the activation window signal generation module and the refresh window signal generation module are respectively connected to the control signal generation module; the activation window signal generation module is configured to generate a storage block activation window signal, and the refresh window signal generation module is configured to generate a refresh window signal; the control signal generation module is configured to control the memory to enter the refresh mode when both the storage block activation window signal and the refresh window signal are obtained; control the memory to enter the normal read / write mode when only the activation window signal is obtained.

[0017] In an exemplary embodiment of the present disclosure, the control signal generation module includes: a first delay sub-module, a second delay sub-module, and a first NAND gate; wherein, the input terminals of the first NAND gate are connected to the output terminal of the first delay sub-module and the output terminal of the second delay sub-module, and the output terminal of the first NAND gate outputs the first control signal; the input terminal of the second delay sub-module is connected to the output terminal of the first delay sub-module, the input terminal of the first delay sub-module is connected to the storage block activation window signal, and the output terminal of the second delay sub-module outputs the second control signal.

[0018] In an exemplary embodiment of the present disclosure, the first delay sub-module includes a first delay unit and a second NAND gate; wherein, the input terminals of the second NAND gate are connected to the output terminal of the first delay unit and the storage block activation window signal, and the input terminal of the first delay unit is connected to the storage block activation window signal.

[0019] In an exemplary embodiment of the present disclosure, the first delay unit includes: a first multiplexer, a first delay device, a second delay device, and a first delay selection unit; wherein, the first delay device and the second delay device are respectively used to delay the storage block activation window signal, the delay duration of the first delay device is greater than that of the second delay device, the output terminal of the second delay device is connected to the input terminal of the first delay selection unit, the output terminals of the first delay device and the first delay selection unit are respectively connected to the input terminals of the first multiplexer, the input terminal of the first delay selection unit is further connected to the storage block activation window signal, and the control terminal of the first delay selection unit is connected to a first test signal; the control terminal of the first multiplexer is connected to the refresh window signal, and is used to select and output the output signal of the first delay selection unit when the refresh window signal is generated, and select and output the delayed signal of the first delay device when the refresh window signal is not generated.

[0020] In an exemplary embodiment of the present disclosure, the second delay sub-module includes a second delay unit and a first AND gate; wherein, the input terminals of the first AND gate are respectively connected to the output terminal of the second delay unit and the output terminal of the first delay sub-module, and the input terminal of the second delay unit is connected to the output terminal of the first delay sub-module.

[0021] In an exemplary embodiment of the present disclosure, the second delay unit includes: a third delay device, a second delay selection unit, and a second multiplexer; wherein, the third delay device is configured to delay the output signal of the first delay sub-module, the input end of the second delay selection unit is connected to the output signal of the first delay sub-module, and the output end of the second delay selection unit is connected to the input end of the second multiplexer; the control end of the second multiplexer is connected to the refresh window signal, and the second multiplexer is configured to select and output the output signal of the second delay selection unit when the refresh window signal is generated, and select and output the output signal of the first delay unit delayed by the third delay device when the refresh window signal is not generated.

[0022] In an exemplary embodiment of the present disclosure, the second delay selection unit includes: a second sub-delay unit, a third sub-delay unit, and a second sub-multiplexer; wherein, the input end of the second sub-delay unit is connected to the output signal of the first delay sub-module, the input end of the third sub-delay unit is connected to the output signal of the second sub-delay unit, the input end of the second sub-multiplexer is connected to the output signals of the second sub-delay unit and the third sub-delay unit, and the control end of the second sub-multiplexer is connected to a second test signal, and under the action of the second test signal, it controls the first control signals of multiple memory blocks to be sequentially turned on, or controls the second control signals of multiple memory blocks to be sequentially turned on.

[0023] In an exemplary embodiment of the present disclosure, the control signal generation module further includes: a bit line balance control signal generation sub-module, a word line turn-on voltage generation sub-module, and a third delay sub-module; wherein, the input end of the bit line balance control signal generation sub-module is connected to the memory block activation window signal, and the output end of the bit line balance control signal generation sub-module outputs the bit line balance control signal; the input end of the word line turn-on voltage generation sub-module is connected to the output end of the third delay sub-module, the output end of the word line turn-on voltage generation sub-module outputs the word line turn-on voltage, and the input end of the third delay sub-module is connected to the memory block activation window signal.

[0024] In an exemplary embodiment of the present disclosure, the third delay sub-module includes a third delay unit and a second AND gate; wherein, the input ends of the second AND gate are connected to the output signal of the third delay unit and the memory block activation window signal, and the input end of the third delay unit is connected to the memory block activation window signal.

[0025] In an exemplary embodiment of the present disclosure, the third delay unit includes: a third multiplexer, a fourth delay device, a fifth delay device, and a third delay selection unit; wherein, the fourth delay device and the fifth delay device are respectively configured to delay the storage block activation window signal, the delay duration of the fourth delay device is greater than that of the fifth delay device, the output end of the fifth delay device is connected to the input end of the third delay selection unit, and the output ends of the fourth delay device and the third delay selection unit are respectively connected to the input ends of the third multiplexer; the control end of the third multiplexer is connected to the refresh window signal, and is configured to select and output the output signal of the third delay selection unit when the refresh window signal is generated, and select and output the delay signal of the fourth delay device when the refresh window signal is not generated.

[0026] In an exemplary embodiment of the present disclosure, the third delay selection unit includes: a fourth sub-delay unit and a third sub-multiplexer; wherein, the input end of the fourth sub-delay unit is connected to the output signal of the fifth delay device, the input ends of the third sub-multiplexer are connected to the output signal of the fifth delay device and the output signal of the fourth sub-delay unit, and the control end of the third sub-multiplexer is connected to a third test signal; for different storage arrays, the delay lengths of the corresponding fourth sub-delay units are different.

[0027] According to a second aspect of the present disclosure, there is provided a memory control method. The memory includes a sense amplifier, and the power supply voltage of the sense amplifier is controlled and supplied by a first control signal or a second control signal. The power supply voltage controlled and supplied by the first control signal is greater than the power supply voltage controlled and supplied by the second control signal. The method includes: in a normal read / write mode, controlling the pulse duration of the first control signal generated to be a first duration; in a refresh mode, controlling the pulse duration of the first control signal generated to be a second duration, and the second duration is less than the first duration; in the refresh mode, controlling the first control signals of multiple storage blocks in the memory to be sequentially turned on.

[0028] In an exemplary embodiment of the present disclosure, the method further includes: in the normal read / write mode or the refresh mode, when the first control signal terminates, generating the second control signal.

[0029] In an exemplary embodiment of the present disclosure, the method further includes: in the normal read / write mode or the refresh mode, controlling the pulse duration of the second control signal generated to be greater than the pulse duration of the first control signal generated.

[0030] In an exemplary embodiment of the present disclosure, the second duration is 0.

[0031] In an exemplary embodiment of the present disclosure, the method further includes: in the refresh mode, directly generating the second control signal without generating the first control signal; and sequentially turning on the second control signals of multiple storage blocks.

[0032] In an exemplary embodiment of the present disclosure, the negative voltage of the sense amplifier is controlled and supplied by a negative control signal, and the method further includes: after generating the first control signal or the second control signal, controlling the generation of the negative control signal.

[0033] In an exemplary embodiment of the present disclosure, the memory further includes: word lines, bit lines, and complementary bit lines, and the sense amplifier is disposed between the bit lines and the complementary bit lines; before generating the first control signal or the second control signal, the method further includes: turning off the bit line balance control signal applied to the bit lines and the complementary bit lines; and applying a word line turn-on voltage to the word lines to turn on the transistors connected to the word lines.

[0034] In an exemplary embodiment of the present disclosure, the method further includes: in the refresh mode, sequentially turning on the word line turn-on voltages of multiple storage arrays.

[0035] In an exemplary embodiment of the present disclosure, the method further includes: when both an activation window signal and a refresh window signal are acquired, controlling the memory to enter the refresh mode; when only the activation window signal is acquired, controlling the memory to enter the normal read / write mode.

[0036] According to a third aspect of the present disclosure, there is provided an electronic device, including: multiple storage blocks, multiple array controllers, and multiple memory read / write circuits as described above; wherein, the memory read / write circuits are disposed in the array controllers, and one memory read / write circuit correspondingly controls one array.

[0037] The technical solution provided by the present disclosure may include the following beneficial effects:

[0038] In an exemplary embodiment of the present disclosure, by setting the pulse duration of the first control signal generated in the refresh mode to be less than the pulse duration of the first control signal generated in the normal read / write mode, the supply duration of the higher first power voltage in the refresh mode is less than that in the normal read / write mode. In this way, it can not only meet the refresh requirements with no high demand for tRCD performance, but also reduce the current loss caused by the relatively long duration of the first power voltage during the refresh process, avoid generating excessive instantaneous current in the refresh mode, and also reduce the requirement for the design of the load capacity of the first power voltage. Additionally, by controlling the sequential activation of the first control signals of multiple memory blocks in the refresh mode, the instantaneous current in the refresh mode can be further reduced, and the VDD load capacity of the memory can be improved.

[0039] It should be understood that the above general description and the following detailed description are merely exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] The accompanying drawings are incorporated herein and constitute a part of this specification, showing embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and those of ordinary skill in the art can obtain other drawings based on these drawings without creative efforts. In the drawings:

[0041] Figure 1 Schematically shows a structural diagram of a memory cell according to an exemplary embodiment of the present disclosure;

[0042] Figure 2 Schematically shows a structural diagram of a peripheral circuit in a DRAM according to an exemplary embodiment of the present disclosure;

[0043] Figure 3 Schematically shows a structural diagram of a memory block in a DRAM according to an exemplary embodiment of the present disclosure;

[0044] Figure 4 Schematically shows a structural diagram of a sense amplifier in a DRAM according to an exemplary embodiment of the present disclosure;

[0045] Figure 5 Schematically shows a control signal waveform diagram of a memory in the normal read / write mode according to an exemplary embodiment of the present disclosure;

[0046] Figure 6 Schematically shows the control signal waveform of a memory in the refresh mode according to an exemplary embodiment of the present disclosure Figure 1 ;

[0047] Figure 7 Schematically shows the control signal waveforms of a memory in a refresh mode according to an exemplary embodiment of the present disclosure Figure 2 ;

[0048] Figure 8 Schematically shows the control signal waveforms of a memory in a refresh mode according to an exemplary embodiment of the present disclosure Figure 3 ;

[0049] Figure 9 Schematically shows the control signal waveforms of a memory in a refresh mode according to an exemplary embodiment of the present disclosure Figure 4 ;

[0050] Figure 10 Schematically shows a schematic circuit diagram of a control signal generation module in a memory read / write circuit according to an exemplary embodiment of the present disclosure;

[0051] Figure 11 Schematically shows a schematic circuit diagram of a first delay unit in a memory read / write circuit according to an exemplary embodiment of the present disclosure;

[0052] Figure 12 Schematically shows a schematic circuit diagram of a second delay unit in a memory read / write circuit according to an exemplary embodiment of the present disclosure;

[0053] Figure 13 Schematically shows a schematic circuit diagram of a third delay unit in a memory read / write circuit according to an exemplary embodiment of the present disclosure;

[0054] Figure 14 Schematically shows a flowchart of the steps of a memory control method according to an exemplary embodiment of the present disclosure. Detailed implementation manners

[0055] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. Like reference numerals in the figures denote like or similar parts, and thus their repetitive description will be omitted.

[0056] In addition, the described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of the embodiments of the present disclosure. However, those skilled in the art will realize that the technical solutions of the present disclosure may be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. may be employed. In other cases, well-known structures, methods, devices, implementations, materials, or operations are not shown or described in detail to avoid obscuring aspects of the present disclosure.

[0057] The block diagrams shown in the drawings are only functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities may be implemented in software form, or these functional entities or a part of the functional entities may be implemented in one or more software-hardened modules, or these functional entities may be implemented in different networks and / or processor devices and / or microcontroller devices.

[0058] Semiconductor memories are used in computers, servers, handheld devices such as mobile phones, printers, and many other electronic devices and applications. A memory array in a semiconductor memory includes a plurality of memory cells, and each memory cell stores at least one bit of information. DRAM is an example of such a semiconductor memory. This solution is preferably used in DRAM. Therefore, the following description of the embodiments is made with reference to DRAM as a non-limiting example.

[0059] In a DRAM integrated circuit device, the memory cell array is typically arranged in rows and columns such that a specific memory cell can be addressed by specifying the row and column of its array. Word lines connect the rows to bit line sense amplifiers that detect data in a group of sense cells. Then, in a read operation, a subset of the data in the sense amplifiers is selected or "column selected" for output.

[0060] Refer to Figure 1 , each memory cell 100 in DRAM generally includes a capacitor 110, a transistor 120, a word line (WL) 130, and a bit line (BL) 140. The gate of the transistor 120 is connected to the word line 130, the drain of the transistor 120 is connected to the bit line 140, and the source of the transistor 120 is connected to the capacitor 110. The voltage signal on the word line 130 can control the opening or closing of the transistor 120, and then the data information stored in the capacitor 110 can be read through the bit line 140, or the data information can be written into the capacitor 110 through the bit line 140 for storage.

[0061] A memory block is composed of the above-mentioned multiple memory cells. The memory block generally occupies 50 - 65% of the entire area of the DRAM device, and the remaining area of the DRAM device is mainly composed of peripheral circuits. Refer toFigure 2 , showing a schematic structural diagram of a peripheral circuit. As Figure 2 , the peripheral circuit of the DRAM device includes a Command Decoder 210, an Address Latch 220, a Refresh Address Counter (RAC) 230, an Address Mux (AM) 240, and a Pre-Decoder (Pre-D) 250. Among them, the Command Decoder 210 is used to decode commands CMD such as RESET_n, CKE, CK_t / CK_c, PAR, TEN, CS_n, ACT_n, etc. issued by the system, and the Address Latch 220 is used to temporarily store address codes A<16:0>, etc.

[0062] In addition, the peripheral circuit of the DRAM device further includes a memory read / write circuit provided by the embodiments of the present disclosure. Among them, the memory read / write circuit mainly includes: an activation window signal generation module 261, a refresh window signal generation module 262, and a control signal generation module 263; the activation window signal generation module 261 and the refresh window signal generation module 262 are respectively connected to the control signal generation module 263. The activation window signal generation module 261 is used to generate a memory bank activation window signal BANK ACT Window, and the refresh window signal generation module 262 is used to generate a refresh window signal Refresh Window.

[0063] For the peripheral circuit of the DRAM device, the command decoder 210 and the address latch 220 are respectively connected to the activation window signal generation module 261, and are used to provide input signals for the activation window signal generation module 261, so that the activation window signal generation module 261 can generate a memory bank activation window signal BANK ACT Window. The refresh window signal generation module 262 is connected to the command decoder 210, and generates a refresh window signal RefreshWindow when a refresh signal is decoded.

[0064] Before introducing the control signal generation module 263 in the embodiments of the present disclosure, it is necessary to briefly describe the internal structure of the memory bank BANK in the memory. See Figure 3, which shows a schematic structural diagram of a memory block. The memory block 300 includes: bit lines BL, complementary bit lines BL_B, a plurality of word lines WL, and a plurality of memory cells 310. The plurality of memory cells 310 share the above-mentioned bit line BL or complementary bit line BL_B. In addition, the bit lines BL and complementary bit lines BL_B are also used to connect to the write input drivers INPUTWrite Driver and INPUT_B Write Driver, and output the output signals OUTPUT and OUTPUT_B.

[0065] In an exemplary embodiment of the present disclosure, the memory block 300 further includes: a sense module 320 and a bit line equalization module 330. Among them, the bit line equalization module 330 is used to pinch the bit line BL and the complementary bit line BL_B under the action of the bit line equalization control signal BLEQ, so as to close the read and write operations of the memory cell 310.

[0066] Referring to Figure 3 , the sense module 320 mainly includes a sense amplifier. The sense amplifier (Sense Amplifier, SA) can address a plurality of memory cells 310 through the bit line BL or BL_B. A conventional sense amplifier is more specifically a differential amplifier. The differential amplifier uses the bit line BL and the complementary bit line BL_B (as a reference line) used as a reference line to work, so as to detect and amplify the voltage difference between a pair of bit lines BL and BL_B.

[0067] Referring to Figure 4 , the four transistors in the sense amplifier 400 are respectively a first transistor 410, a second transistor 420, a third transistor 430, and a fourth transistor 440. Among them, the first transistor 410 and the third transistor 430 are both PMOS (Positive channel Metal Oxide Semiconductor) transistors, and the second transistor 420 and the fourth transistor 440 are both NMOS (Negative channel Metal Oxide Semiconductor, N-type metal oxide semiconductor) transistors. If the data stored in the memory cell 310 is 1, during the read operation, the voltage of the word line WL is first pulled up to Vccp, and the transistor in the memory cell 310 is turned on. At this time, the memory cell 310 is in the read / write activation state. A pair of bit lines BL and BL_B are disconnected from the voltage. When reading 1, a positive voltage is generated on the bit line BL. This voltage causes the fourth transistor 440 to conduct, so that the negative voltage on the N node is applied to the BL_B line and the gate of the first transistor 410 and makes it conduct. Finally, the Vcc voltage on the P node is applied to the BL line, so that it can be easily and accurately determined whether the data stored in the memory cell is 1 or 0 according to whether the voltage difference between a pair of bit lines is +Vcc or -Vcc.

[0068] As Figure 1 shown, for capacitor 110, when writing a 1, a voltage Vcc is applied to bit line BL. This voltage Vcc is conducted from the drain to the source through the turned-on transistor 120 and finally loaded onto the other plate of capacitor 110. When writing a 0, a voltage 0V is applied to bit line BL, resulting in a voltage of 0V on the other plate of capacitor 110 as well. The process of writing a 1 or 0 to capacitor 110 is the same.

[0069] When writing a 1 or a 0 to capacitor 110, the voltage of the capacitor 110 plates is 1 or 0. After writing is completed, the BL voltage returns to V CC / 2. When reading data, after transistor 120 is turned on, capacitor 110 shares charge with BL, causing the BL voltage to change. It is possible to determine whether the data stored in the memory cell is 1 or 0 based on whether the BL voltage increases or decreases.

[0070] During the read operation of the DRAM memory cell, a voltage greater than the turn-on voltage of transistor 120 also needs to be applied to the word line WL of the memory cell to turn on transistor 120. At this time, the charge on capacitor 110 is released to bit lines BL and BL_B through transistor 120.

[0071] For the memory read / write circuit provided by the embodiments of the present disclosure, whether in the normal read / write mode or the refresh mode, signal amplification needs to be completed through the sense amplifier.

[0072] In the memory read / write circuit provided by the exemplary embodiments of the present disclosure, the control signal generation module 263 is used to control the memory to enter the refresh mode when both the memory block activation window signal BANK ACT Window and the refresh window signal Refresh Window are acquired simultaneously; and to control the memory to enter the normal read / write mode when only the activation window signal BANK ACT Window is acquired.

[0073] Referring to Figure 2 and Figure 4 , under the control of the control signal generation module 263 provided by the exemplary embodiments of the present disclosure, the power supply voltage of the sense amplifier 400 can be controlled and supplied by the first control signal SAP1 or by the second control signal SAP2. Moreover, the first power supply voltage VDD controlled and supplied by the first control signal SAP1 is greater than the second power supply voltage VARY controlled and supplied by the second control signal SAP2.

[0074] By setting different power supply voltages VDD and VARY for the sense amplifier 400, at the initial stage of the normal read / write mode, a larger first power supply voltage VDD can be used for power supply to reduce the time consumed in the sensing and cell storage processes, thereby achieving the effect of optimizing performance such as the row address to column address delay time tRCD and the shortest cycle tRAS from the memory row active to precharge.

[0075] In the refresh mode, a different power supply method from that in the normal read / write mode can be set. For example, in the normal read / write mode, if the pulse duration of the first control signal SAP1 is controlled to be the first duration, then in the normal read / write mode, the duration supplied by the first power supply voltage VDD is the first duration; in the refresh mode, if the pulse duration of the first control signal SAP1 is controlled to be the second duration, then in the refresh mode, the duration supplied by the first power supply voltage VDD is the second duration.

[0076] In the exemplary embodiment of the present disclosure, the second duration is less than the first duration. That is to say, the duration of supplying the first power supply voltage VDD in the refresh mode is less than the duration of supplying the first power supply voltage VDD in the normal read / write mode. In this way, in the refresh mode where there is no high requirement for the tRCD performance, by reducing the duration of supplying the first power supply voltage VDD, it can not only meet the refresh requirements, but also reduce the consumption of the VDD current during the refresh process, avoid generating an excessive instantaneous current in the refresh mode, and also reduce the requirement for the VDD load capacity design.

[0077] Refer to Figure 5 , which shows the control signal waveform diagram of the memory in the normal read / write mode; refer to Figure 6 , which shows the control signal waveform diagram of the memory in the refresh mode. Taking the clock signal CLK as a reference, comparing Figure 5 and Figure 6 , in the refresh mode, the pulse duration T2 of the first control signal SAP1 is significantly less than the pulse duration T1 of the first control signal SAP1 in the normal read / write mode, so that the duration of supplying the first power supply voltage VDD can be reduced in the refresh mode.

[0078] In the exemplary embodiment of the present disclosure, the control signal generation module 263 can also be used to sequentially turn on the first control signals of multiple memory blocks in the memory in the refresh mode. For example, as Figure 7As shown, among the 16 memory banks Bank0 - Bank15 in the memory, the first control signal SAP1 is sequentially enabled. That is, after the first control signal SAP1 of the first memory bank Bank0 is enabled for a preset time, the first control signal SAP1 of the second memory bank Bank1 is enabled; then, the first control signal SAP1 of the third memory bank Bank2 is enabled; until the first control signal SAP1 of the 16th memory bank Bank15 is enabled. Among them, the preset time interval for sequential enabling can be set according to the actual situation, and the exemplary embodiments of the present disclosure do not make special limitations on this.

[0079] By sequentially enabling the first control signal SAP1 of multiple memory banks, the instantaneous current in the refresh mode can be further reduced, and the VDD bearing capacity of the memory can be improved.

[0080] Even as Figure 8 shown, in the refresh mode, the control of the first control signal SAP1 is cancelled, and the pulse duration of the first control signal SAP1, that is, the second duration, is set to 0. In this case, in the refresh mode, the first control signal SAP1 is not generated, and the second control signal SAP2 is directly generated, that is, the sense amplifier 400 is not supplied with the first power supply voltage VDD, but directly supplied with the second power supply voltage VARY. Thus, the instantaneous current of the memory in the refresh mode can be further reduced, and the VDD bearing capacity of the memory can be further improved.

[0081] In addition, the control signal generation module 263 can also be used to control the sequential enabling of the second control signal SAP2 of multiple memory banks with only the second control signal. For example, referring to Figure 7 the method in, the second control signal SAP2 of the 16 memory banks Bank0 - Bank15 is enabled at intervals, so that on the basis of Figure 8 the instantaneous current in the refresh mode can be further reduced, and the VDD bearing capacity of the memory can be improved.

[0082] In practical applications, the first power supply voltage VDD can be 1.2 - 1.3V, such as 1.25V, and the second power supply voltage VARY can be 0.9 - 1.1V, such as 1V. The exemplary embodiments of the present disclosure do not make special limitations on the specific values of the first power supply voltage VDD and the second power supply voltage VARY.

[0083] It should be noted that Figures 5 - 8 the PRE in represents the precharge command. Under this precharge command, the read and write operations end, and the capacitor precharge process of the memory cell is entered.

[0084] In an exemplary embodiment of the present disclosure, the above control signal generation module 263 is further configured to generate a second control signal SAP2 when the first control signal SAP1 terminates in a normal read / write mode or a refresh mode, and the pulse duration of the second control signal SAP2 is greater than that of the first control signal SAP1. That is to say, whether in the normal read / write mode or the refresh mode, the first power supply voltage VDD is only used in the initial stage, and in most subsequent read / write or refresh processes, the power supply voltage of the memory is supplied by the second power supply voltage VARY. The main purpose of initially setting the first power supply voltage VDD is to reduce latency and improve the read / write performance of the memory.

[0085] In an exemplary embodiment of the present disclosure, as Figure 4 shown, the negative voltage of the sense amplifier 400 is controlled and supplied by the negative control signal SAN. Referring to Figure 5 and Figure 6 it can be seen that the control signal generation module 263 is further configured to control the generation of the negative control signal SAN after generating the first control signal SAP1; referring to Figure 8 it can be seen that the control signal generation module 263 is further configured to control the generation of the negative control signal SAN after generating the second control signal SAP2.

[0086] As Figure 2 shown, in addition to controlling the generation of the first control signal SAP1, the second control signal SAP2, and the negative control signal SAN, the control signal generation module 263 provided in the embodiment of the present disclosure also controls the generation of the bit line balance control signal BLEQB and the word line turn-on voltage SWL. The control signal generation module 263 is further configured to turn off the bit line balance control signal BLEQ applied to the bit line BL and the complementary bit line BL_B before generating the first control signal SAP1 and the second control signal SAP2, so as to separate the pinched bit line BL and the complementary bit line BL_B (i.e., BLT and BLB in the figure are opened), thereby entering the read / write operation of the memory cell 310; then, apply the word line turn-on voltage SWL to the word line to turn on the transistor connected to the word line, and the voltage on the capacitor connected to the transistor is released to the bit line BL through charge sharing, thereby generating a voltage difference. Next, the sense amplifier 400 amplifies the above voltage difference, that is, generates the first power supply voltage SAP1, the second power supply voltage SAP2, and the negative control signal SAN. When the read / write process is almost over, turn off the word line turn-on voltage SWL, and at the same time, generate the bit line balance control signal BLEQB to pinch the bit line BL and the complementary bit line BL_B (i.e., the voltages of BLT and BLB in the figure are equal) to turn off the read / write operation of the memory cell 310 and complete the normal read / write process or the refresh process.

[0087] In an exemplary embodiment of the present disclosure, during the process of reducing the instantaneous current of the memory in the refresh mode, in addition to the above various methods, the control signal generation module 263 can also control the word line turn-on voltages SWL of multiple memory blocks to be turned on sequentially in the refresh mode. As Figure 9 shown, among the 16 memory blocks Bank0 - Bank15 in the memory, the word line turn-on voltages SWL are turned on sequentially. That is, after the word line turn-on voltage SWL of the first memory block Bank0 is turned on for a preset time, the word line turn-on voltage SWL of the second memory block Bank1 is turned on; then, the word line turn-on voltage SWL of the third memory block Bank2 is turned on; until the word line turn-on voltage SWL of the 16th memory block Bank15 is turned on; wherein, the preset time interval for sequential turn-on can be set according to the actual situation, and the exemplary embodiment of the present disclosure does not make special limitations on this. By sequentially turning on the word line turn-on voltages SWL of multiple memory blocks, the instantaneous current in the refresh mode can be further reduced, and the VDD bearing capacity of the memory can be improved.

[0088] Referring to Figure 10 , the exemplary embodiment of the present disclosure provides a circuit structure of a control signal generation module in a memory read / write circuit. Figure 10 Among them, the control signal generation module includes: a first delay sub-module 1010, a second delay sub-module 1020, and a first NAND gate 1030; wherein, the input terminals of the first NAND gate 1030 are connected to the output terminal of the first delay sub-module 1010 and the output terminal of the second delay sub-module 1020, and the output terminal of the first NAND gate 1030 outputs a first control signal SAP1.

[0089] The input terminal of the second delay sub-module 1020 is connected to the output terminal of the first delay sub-module 1010. The input terminal of the first delay sub-module 1010 is connected to the memory block activation window signal BANK ACT Window or a delayed signal of the memory block activation window signal BANK ACT Window, and the output terminal of the second delay sub-module 1020 outputs a second control signal SAP2.

[0090] In the exemplary embodiment of the present disclosure, the first delay sub-module 1010 includes a first delay unit 1011 and a second NAND gate 1012; wherein, the input terminals of the second NAND gate 1012 are connected to the output terminal of the first delay unit 1011 and the memory block activation window signal BANK ACT Window, and the input terminal of the first delay unit 1011 is connected to the memory block activation window signal BANKACT Window.

[0091] Referring to Figure 11As shown in the figure, the first delay unit 1011 includes: a first multiplexer 1110, a first delay device 1120, a second delay device 1130, and a first delay selection unit 1140; wherein, the first delay device 1120 and the second delay device 1130 are respectively used to delay the storage block activation window signal BANK ACT Window, and the delay duration of the first delay device 1120 is greater than that of the second delay device 1130; the output end of the second delay device 1130 is connected to the input end of the first delay selection unit 1140, the output ends of the first delay device 1120 and the first delay selection unit 1140 are respectively connected to the input ends of the first multiplexer 1110, the input end of the first delay selection unit 1140 is also connected to the storage block activation window signal BANK ACT Window, and the control end of the first delay selection unit 1140 is connected to the first test signal TM1. When generating the first test signal TM1, the first delay selection unit 1140 directly outputs the storage block activation window signal BANK ACT Window.

[0092] And the control end of the first multiplexer 1110 is connected to the refresh window signal Refresh Window, which is used to select and output the output signal of the first delay selection unit 1140 when generating the refresh window signal Refresh Window, and to select and output the delay signal of the first delay device 1120 when the refresh window signal is not generated. Thus, when generating the refresh window signal Refresh Window, if the first test signal TM1 is not generated, the delay signal of the second delay device 1130 selected and output by the first delay selection unit 1140 has a shorter delay duration, and compared with the normal refresh mode, a first control signal SAP1 with a shorter pulse duration can be obtained; if the first test signal TM1 is generated, the first delay selection unit 1140 selects and outputs the storage block activation window signal BANK ACT Window, and the first multiplexer 1110 also outputs the storage block activation window signal BANK ACT Window under the control of the refresh window signal Refresh Window. After the two storage block activation window signals BANK ACT Window pass through the second NAND gate 1012, no pulse signal will be generated. Therefore, under the action of the first test signal TM1, it can play a role in closing the first control signal SAP1, that is, the first control signal SAP1 will not be generated, and only the second control signal SAP2 will be generated, so as to achieve the purpose of directly generating the second control signal SAP2. The first delay selection unit 114 here can be a multiplexer.

[0093] Refer to Figure 10As shown, the second delay sub-module 1020 includes a second delay unit 1021 and a first AND gate 1022. Among them, the input terminals of the first AND gate 1022 are respectively connected to the output terminal of the second delay unit 1021 and the output terminal of the first delay sub-module 1010, and the input terminal of the second delay unit 1021 is connected to the output terminal of the first delay sub-module 1010.

[0094] Referring to Figure 12 , in the exemplary embodiment of the present disclosure, the second delay unit 1021 includes: a third delay device 1210, a second delay selection unit 1245, and a second multiplexer 1220. Among them, the third delay device 1210 is used to delay the output signal of the first delay sub-module 1010. The input terminal of the second delay selection unit 1245 receives the output signal of the first delay sub-module 1010, and the output terminal of the second delay selection unit 1245 is connected to the input terminal of the second multiplexer 1220. The control terminal of the second multiplexer 1220 receives the refresh window signal Refresh Window. The second multiplexer 1220 is used to select and output the output signal of the second delay selection unit 1245 when the refresh window signal Refresh Window is generated, and to select and output the output signal of the third delay device 1210 when the refresh window signal is not generated.

[0095] Among them, the second delay selection unit 1245 includes: a second sub-delay unit 1230, a third sub-delay unit 1240, and a second sub-multiplexer 1250. Among them, the input terminal of the second sub-delay unit 1230 receives the output signal of the first delay sub-module 1010. The input terminal of the third sub-delay unit 1240 receives the output signal of the second sub-delay unit 1230. The input terminals of the second sub-multiplexer 1250 receive the output signal of the second sub-delay unit 1230 and the output signal of the third sub-delay unit 1240. The control terminal of the second sub-multiplexer 1250 receives the second test signal TM2. Under the action of the second test signal TM2, it controls the first control signal SAP1 of multiple memory blocks in the memory to be sequentially turned on, or controls the second control signal SAP2 of multiple memory blocks to be sequentially turned on.

[0096] Referring to Figure 10As shown in the figure, the control signal generation module further includes: a bit line balance control signal generation sub-module 1040, a word line turn-on voltage generation sub-module 1050, and a third delay sub-module 1060; among them, the input end of the bit line balance control signal generation sub-module 1040 is connected to the memory block activation window signal BANK ACT Window, and the output end of the bit line balance control signal generation sub-module 1040 outputs a bit line balance control signal BLEQ; the input end of the word line turn-on voltage generation sub-module 1050 is connected to the output end of the third delay sub-module 1060, and the output end of the word line turn-on voltage generation sub-module 1050 outputs a word line turn-on voltage SWL. The input end of the third delay sub-module is connected to the memory block activation window signal BANK ACT Window.

[0097] After generating the memory block activation window signal BANK ACT Window, whether in the normal read / write mode or the refresh mode, it is necessary to generate the word line turn-on voltage SWL. As an example, as Figure 10 shown, the word line turn-on voltage SWL includes a plurality of delay units, a plurality of NAND gates, and a plurality of inverters. The specific connection method is not described here in detail. Since it is necessary to turn off the bit line balance control signal BLEQ before generating the word line turn-on voltage SWL, therefore, compared with the bit line balance control signal generation sub-module 1040, the word line turn-on voltage generation sub-module 1050 has one more delay unit.

[0098] In addition, compared with the word line turn-on voltage generation sub-module 1050, the bit line balance control signal generation sub-module 1040 is provided with an inverter at the output end to achieve the purpose of turning off the generated bit line balance control signal BLEQ.

[0099] In practical applications, there can be various circuit connection methods for forming the bit line balance control signal generation sub-module 1040 and the word line turn-on voltage generation sub-module 1050. The exemplary embodiments of the present disclosure are not limited to Figure 10 this.

[0100] In the exemplary embodiments of the present disclosure, the third delay sub-module 1060 includes a third delay unit 1061 and a second AND gate 1062; among them, the input end of the second AND gate 1062 is connected to the output signal of the third delay unit 1061 and the memory block activation window signal BANK ACT Window, and the input end of the third delay unit 1061 is connected to the memory block activation window signal BANK ACT Window.

[0101] Refer to Figure 13, in an exemplary embodiment of the present disclosure, the third delay unit 1061 includes: a third multiplexer 1310, a fourth delay device 1320, a fifth delay device 1330, and a third delay selection unit 1345; wherein, the fourth delay device 1320 and the fifth delay device 1330 are respectively configured to delay the memory bank activation window signal BANK ACT Window, the delay duration of the fourth delay device 1320 is greater than that of the fifth delay device 1330, the output end of the fifth delay device 1330 is connected to the input end of the third delay selection unit 1345, and the output ends of the fourth delay device 1320 and the third delay selection unit 1345 are respectively connected to the input ends of the third multiplexer 1310; the control end of the third multiplexer 1310 is connected to the refresh window signal Refresh Window, and is configured to select and output the output signal of the third delay selection unit 1345 when the refresh window signal Refresh Window is generated, and select and output the delayed signal of the fourth delay device 1320 when the refresh window signal Refresh Window is not generated.

[0102] Referring to Figure 13 , the third delay selection unit 1345 includes: a fourth sub-delay unit 1340 and a third sub-multiplexer 1350; wherein, the input end of the fourth sub-delay unit 1340 is connected to the output signal of the fifth delay device 1330, the input ends of the third sub-multiplexer 1350 are connected to the output signal of the fifth delay device 1330 and the output signal of the fourth sub-delay unit 1340, and the control end of the third sub-multiplexer 1350 is connected to the third test signal TM3; for different memory arrays, the delay lengths of the fourth sub-delay unit 1340 are different, so that the word line turn-on voltages SWL of multiple memory banks can be sequentially turned on in the refresh mode.

[0103] In summary, in the exemplary embodiment of the present disclosure, by setting the pulse duration of the first control signal generated in the refresh mode to be less than that of the first control signal generated in the normal read / write mode, the duration of supplying the larger first power supply voltage VDD in the refresh mode will be less than that in the normal read / write mode. By reducing the duration of supplying the first power supply voltage VDD in the refresh mode, it can not only meet the refresh requirements with relatively low requirements for tRCD performance, but also reduce the power consumption of the current of the first power supply voltage VDD during the refresh process, thereby reducing the probability of generating an excessive instantaneous current in the refresh mode, and also reducing the design requirements for the load capacity of the first power supply voltage VDD. In addition, by controlling the sequential turn-on of the first control signals of multiple memory banks in the refresh mode, the instantaneous current in the refresh mode can be further reduced, and the load capacity of VDD of the memory can be improved.

[0104] It should be noted that although the steps of the method in the present invention are described in a specific order in the accompanying drawings, this does not require or imply that these steps must be executed in that specific order, or that all the steps shown must be executed to achieve the desired result. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step for execution, and / or one step may be decomposed into multiple steps for execution, etc.

[0105] In addition, in the present exemplary embodiment, a memory control method is further provided. The memory control method is used to control a memory, including the aforementioned sense amplifier. Among them, the power supply voltage of the sense amplifier is controlled and supplied by a first control signal SAP1 or a second control signal SAP2, and the power supply voltage VDD controlled and supplied by the first control signal SAP1 is greater than the power supply voltage VARY controlled and supplied by the second control signal SAP2.

[0106] Referring to Figure 14 , the memory control method includes the following steps:

[0107] Step S1410, in the normal read / write mode, control the pulse duration of the first control signal generated to be a first duration;

[0108] Step S1420, in the refresh mode, control the pulse duration of the first control signal generated to be a second duration, and the second duration is less than the first duration;

[0109] Step S1430, in the refresh mode, control the first control signals of multiple memory blocks in the memory to be sequentially turned on.

[0110] In an exemplary embodiment of the present disclosure, in the normal read / write mode or the refresh mode, when controlling the termination of the first control signal, a second control signal is generated.

[0111] In an exemplary embodiment of the present disclosure, the memory control method further includes: in the normal read / write mode or the refresh mode, control the pulse duration of the second control signal generated to be greater than the pulse duration of the first control signal generated.

[0112] In an exemplary embodiment of the present disclosure, the second duration is 0.

[0113] In an exemplary embodiment of the present disclosure, the memory control method further includes: in the refresh mode, directly generate the second control signal without generating the first control signal; and control the second control signals of multiple memory blocks to be sequentially turned on.

[0114] In an exemplary embodiment of the present disclosure, the negative voltage of the sense amplifier is controlled and supplied by a negative control signal SAN, and the memory control method further includes: after generating the first control signal or the second control signal, control the generation of the negative control signal.

[0115] In an exemplary embodiment of the present disclosure, the method further includes: in a refresh mode, sequentially turning on the word line turn-on voltages of a plurality of memory arrays.

[0116] In an exemplary embodiment of the present disclosure, the memory further includes: word lines, bit lines, and complementary bit lines, and a sense amplifier is disposed between the bit lines and the complementary bit lines; before generating the first control signal or the second control signal, the memory control method further includes: turning off the bit line equalization control signal BLEQ applied to the bit lines and the complementary bit lines; applying a word line turn-on voltage SWL to the word lines to turn on the transistors connected to the word lines.

[0117] In an exemplary embodiment of the present disclosure, the memory control method further includes: when both the activation window signal BANK ACT Window and the refresh window signal Refresh Window are acquired, controlling the memory to enter a refresh mode; when only the activation window signal BANK ACT Window is acquired, controlling the memory to enter a normal read / write mode.

[0118] The specific details of the above memory control method have been described in detail in the corresponding memory read / write circuit, and thus will not be elaborated herein.

[0119] In an exemplary embodiment of the present disclosure, there is also provided an electronic device, which may include: a plurality of arrays, a plurality of array controllers, and a plurality of the above-mentioned memory read / write circuits; wherein, the above-mentioned memory read / write circuits are disposed in the array controllers, and one memory read / write circuit correspondingly controls one array. Among them, the specific structural details of the memory read / write circuits have been described in detail in the above embodiments, and will not be elaborated herein.

[0120] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using a software program, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions described in the embodiments of the present disclosure are generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. The computer-readable storage medium can be any available medium that the computer can access or a data storage device such as a server or a data center that contains one or more media integrated therein. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid state disk (SSD)), etc. In the embodiments of the present disclosure, the computer can include the devices described above.

[0121] Although the present disclosure has been described in connection with various embodiments, however, in the process of implementing the claimed present disclosure, those skilled in the art can understand and implement other variations of the disclosed embodiments by viewing the accompanying drawings, the disclosure content, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "one" does not exclude a plurality. A single processor or other unit can implement several functions recited in the claims. Certain measures are recited in mutually different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0122] Although the present disclosure has been described in connection with specific features and their embodiments, it is obvious that various modifications and combinations can be made without departing from the spirit and scope of the present disclosure. Accordingly, the present specification and the drawings are only exemplary illustrations of the present disclosure defined by the appended claims, and are considered to have covered any and all modifications, variations, combinations, or equivalents within the scope of the present disclosure. Obviously, those skilled in the art can make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalent technologies, the present disclosure also intends to include these changes and modifications.

Claims

1. A memory read / write circuit, characterized in that, Comprising: A sense amplifier, the power supply voltage of the sense amplifier being controlled and supplied by a first control signal or a second control signal, the first power supply voltage controlled and supplied by the first control signal being greater than the second power supply voltage controlled and supplied by the second control signal; A control signal generation module, configured to, in a normal read / write mode, control the pulse duration of the first control signal to be a first duration; In a refresh mode, control the pulse duration of the first control signal to be a second duration, the second duration being less than the first duration; The control signal generation module is further configured to, in the refresh mode, control the first control signals of multiple memory blocks in the memory to be sequentially enabled; Further comprising: a word line, a bit line, and a complementary bit line, the sense amplifier being disposed between the bit line and the complementary bit line; The control signal generation module is further configured to, before generating the first control signal and the second control signal, turn off the bit line balance control signal applied to the bit line and the complementary bit line; apply a word line activation voltage to the word line to turn on the transistor connected to the word line; Further comprising: an activation window signal generation module and a refresh window signal generation module, the activation window signal generation module and the refresh window signal generation module being respectively connected to the control signal generation module; The activation window signal generation module is configured to generate a memory block activation window signal, and the refresh window signal generation module is configured to generate a refresh window signal; The control signal generation module is configured to, when simultaneously obtaining the memory block activation window signal and the refresh window signal, control the memory to enter the refresh mode; when only obtaining the activation window signal, control the memory to enter the normal read / write mode.

2. The memory read / write circuit according to claim 1, wherein The control signal generation module is further configured to, in the normal read / write mode or the refresh mode, when the first control signal terminates, generate the second control signal.

3. The memory read / write circuit according to claim 2, wherein The control signal generation module is further configured to, in the normal read / write mode or the refresh mode, control the pulse duration of the second control signal to be greater than the pulse duration of the first control signal.

4. The memory read / write circuit according to claim 1, wherein The second duration is 0.

5. The memory read / write circuit according to claim 4, characterized in that The control signal generation module is further configured to, in the refresh mode, not generate the first control signal, directly generate the second control signal, and control the second control signals of multiple memory blocks to be sequentially enabled.

6. The memory read / write circuit according to any one of claims 1-5, characterized in that, The negative voltage of the sense amplifier is controlled and supplied by a negative control signal, and the control signal generation module is further configured to, after generating the first control signal or the second control signal, control the generation of the negative control signal.

7. The memory read / write circuit according to claim 1, wherein The control signal generation module is further configured to, in the refresh mode, control the word line activation voltages of multiple memory blocks to be sequentially enabled.

8. The memory read / write circuit according to claim 1, wherein The control signal generation module includes: a first delay sub-module, a second delay sub-module, and a first NAND gate; wherein, The input terminals of the first NAND gate are connected to the output terminal of the first delay sub-module and the output terminal of the second delay sub-module, and the output terminal of the first NAND gate outputs the first control signal; The input end of the second delay sub-module is connected to the output end of the first delay sub-module. The input end of the first delay sub-module receives the storage block activation window signal, and the output end of the second delay sub-module outputs the second control signal.

9. The memory read / write circuit according to claim 8, wherein The first delay sub-module includes a first delay unit and a second NAND gate; wherein, The input ends of the second NAND gate receive the output end of the first delay unit and the storage block activation window signal, and the input end of the first delay unit receives the storage block activation window signal.

10. The memory read / write circuit according to claim 9, wherein The first delay unit includes: a first multiplexer, a first delay device, a second delay device, and a first delay selection unit; wherein, The first delay device and the second delay device are respectively used to delay the storage block activation window signal. The delay duration of the first delay device is greater than that of the second delay device. The output end of the second delay device is connected to the input end of the first delay selection unit. The output ends of the first delay device and the first delay selection unit are respectively connected to the input ends of the first multiplexer. The input end of the first delay selection unit also receives the storage block activation window signal, and the control end of the first delay selection unit receives a first test signal; The control end of the first multiplexer receives the refresh window signal, and is used to select and output the output signal of the first delay selection unit when the refresh window signal is generated, and select and output the delayed signal of the first delay device when the refresh window signal is not generated.

11. The memory read / write circuit according to any one of claims 8-10, characterized in that, The second delay sub-module includes a second delay unit and a first AND gate; wherein, The input ends of the first AND gate are respectively connected to the output end of the second delay unit and the output end of the first delay sub-module, and the input end of the second delay unit is connected to the output end of the first delay sub-module.

12. The memory read / write circuit according to claim 11, wherein The second delay unit includes: a third delay device, a second delay selection unit, and a second multiplexer; wherein, The third delay device is used to delay the output signal of the first delay sub-module. The input end of the second delay selection unit receives the output signal of the first delay sub-module, and the output end of the second delay selection unit is connected to the input end of the second multiplexer; The control end of the second multiplexer receives the refresh window signal, and the second multiplexer is used to select and output the output signal of the second delay selection unit when the refresh window signal is generated, and select and output the output signal of the first delay unit delayed by the third delay device when the refresh window signal is not generated.

13. The memory read / write circuit according to claim 12, wherein The second delay selection unit includes: a second sub-delay unit, a third sub-delay unit, and a second sub-multiplexer; wherein, The input end of the second sub-delay unit is connected to the output signal of the first delay sub-module. The input end of the third sub-delay unit is connected to the output signal of the second sub-delay unit. The input ends of the second sub-multiplexer are connected to the output signal of the second sub-delay unit and the output signal of the third sub-delay unit. The control end of the second sub-multiplexer is connected to a second test signal. Under the action of the second test signal, it controls the sequential activation of the first control signals of multiple memory blocks in the memory, or controls the sequential activation of the second control signals of multiple memory blocks.

14. The memory read / write circuit according to claim 1 or 8, characterized in that, The control signal generation module further includes: a bit line balance control signal generation sub-module, a word line turn-on voltage generation sub-module, and a third delay sub-module; wherein, The input end of the bit line balance control signal generation sub-module is connected to the memory block activation window signal, and the output end of the bit line balance control signal generation sub-module outputs the bit line balance control signal; The input end of the word line turn-on voltage generation sub-module is connected to the output end of the third delay sub-module, and the output end of the word line turn-on voltage generation sub-module outputs the word line turn-on voltage. The input end of the third delay sub-module is connected to the memory block activation window signal.

15. The memory read / write circuit according to claim 14, wherein The third delay sub-module includes a third delay unit and a second AND gate; wherein, The input ends of the second AND gate are connected to the output signal of the third delay unit and the memory block activation window signal, and the input end of the third delay unit is connected to the memory block activation window signal.

16. The memory read / write circuit according to claim 15, characterized in that, The third delay unit includes: a third multiplexer, a fourth delay device, a fifth delay device, and a third delay selection unit; wherein, The fourth delay device and the fifth delay device are respectively used to delay the memory block activation window signal. The delay duration of the fourth delay device is greater than that of the fifth delay device. The output end of the fifth delay device is connected to the input end of the third delay selection unit. The output end of the fourth delay device and the output end of the third delay selection unit are respectively connected to the input ends of the third multiplexer; The control end of the third multiplexer is connected to the refresh window signal, and is used to select and output the output signal of the third delay selection unit when the refresh window signal is generated, and select and output the delay signal of the fourth delay device when the refresh window signal is not generated.

17. The memory read / write circuit according to claim 16, wherein The third delay selection unit includes: a fourth sub-delay unit and a third sub-multiplexer; wherein, The input end of the fourth sub-delay unit is connected to the output signal of the fifth delay device. The input ends of the third sub-multiplexer are connected to the output signal of the fifth delay device and the output signal of the fourth sub-delay unit. The control end of the third sub-multiplexer is connected to a third test signal; For different memory blocks, the delay lengths of the corresponding fourth sub-delay units are different.

18. A memory control method, characterized in that, The memory includes a sense amplifier, and a power supply voltage of the sense amplifier is controlled and supplied by a first control signal or a second control signal. The power supply voltage controlled and supplied by the first control signal is greater than the power supply voltage controlled and supplied by the second control signal. The method includes: In a normal read / write mode, controlling a pulse duration of the first control signal generated to be a first duration; In a refresh mode, controlling a pulse duration of the first control signal generated to be a second duration, where the second duration is less than the first duration; In the refresh mode, controlling the first control signals of multiple memory blocks in the memory to be sequentially turned on; The memory further includes: a word line, a bit line, and a complementary bit line. The sense amplifier is disposed between the bit line and the complementary bit line. Before generating the first control signal or the second control signal, the method further includes: Turning off a bit line balance control signal applied to the bit line and the complementary bit line; Applying a word line turn-on voltage to the word line to turn on a transistor connected to the word line; The method further includes: When an activation window signal and a refresh window signal are acquired simultaneously, controlling the memory to enter the refresh mode; When only the activation window signal is acquired, controlling the memory to enter the normal read / write mode.

19. The memory control method according to claim 18, wherein, The method further includes: In the normal read / write mode or the refresh mode, when controlling the termination of the first control signal, generating the second control signal.

20. The memory control method according to claim 19, wherein The method further includes: In the normal read / write mode or the refresh mode, controlling a pulse duration of the second control signal generated to be greater than a pulse duration of the first control signal generated.

21. The memory control method according to claim 18, wherein The second duration is 0.

22. The memory control method according to claim 21, wherein, The method further includes: In the refresh mode, not generating the first control signal and directly generating the second control signal; and controlling the second control signals of multiple memory blocks to be sequentially turned on.

23. The memory control method according to any one of claims 18-22, characterized in that, A negative voltage of the sense amplifier is controlled and supplied by a negative control signal. The method further includes: After generating the first control signal or the second control signal, controlling the generation of the negative control signal.

24. The memory control method according to claim 18, wherein The method further includes: In the refresh mode, controlling the word line turn-on voltages of multiple memory blocks to be sequentially turned on.

25. An electronic device, characterized in that, Including: Multiple memory blocks, multiple array controllers, and multiple memory read / write circuits as described in any one of claims 1-17; where The memory read / write circuits are disposed in the array controllers, and one memory read / write circuit correspondingly controls one array.

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