Memory read / write circuit, memory control method, and electronic device

Abstract

The present disclosure relates to a memory read / write circuit, a memory control method, and an electronic device, and relates to the field of integrated circuit technologies. The memory read / write circuit includes: a sense amplifier, the power supply voltage of the sense amplifier is controlled and supplied by a first control signal or a second control signal, and the first power supply voltage controlled and supplied by the first control signal is greater than the second power supply voltage controlled and supplied by the second control signal; a control signal generation module, configured to, in a normal read / write mode, control the pulse duration of the first control signal to be a first duration; and in a refresh mode, control the pulse duration of the first control signal to be a second duration, where the second duration is less than the first duration. The present disclosure can reduce the instantaneous current in the refresh mode.

Description

Technical Field

[0001] The present disclosure relates to the field of integrated circuit technologies, and in particular, to a memory read / write circuit, a memory control method, and an electronic device. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor memory device in computers. Due to its advantages such as simple structure, high density, low power consumption, and low cost, it has been widely used in the computer field and the electronics industry.

[0003] For DRAM, high performance is often required during the read / write stage to ensure a good user experience.

[0004] However, during the refresh stage, the same high performance is not required for DRAM. Therefore, adopting different control methods during the read / write stage and the refresh stage is of great significance for reducing the power consumption of DRAM.

[0005] It should be noted that the information disclosed in the above background art section is only used to enhance the understanding of the background of the present disclosure, and thus may include information that does not constitute the prior art known to those of ordinary skill in the art. Summary of the Invention

[0006] The purpose of the present disclosure is to provide a memory read / write circuit, a memory control method, and an electronic device to reduce the instantaneous current of DRAM in the refresh mode.

[0007] Other features and advantages of the present disclosure will become apparent through the following detailed description, or will be partially learned through the practice of the present invention.

[0008] According to a first aspect of the present disclosure, there is provided a memory read / write circuit, including: a sense amplifier, the power supply voltage of the sense amplifier being controlled and supplied by a first control signal or a second control signal, the first power supply voltage controlled and supplied by the first control signal being greater than the second power supply voltage controlled and supplied by the second control signal; a control signal generation module, configured to, in the normal read / write mode, control the pulse duration of the first control signal to be a first duration; in the refresh mode, control the pulse duration of the first control signal to be a second duration, the second duration being less than the first duration.

[0009] In an exemplary embodiment of the present disclosure, the control signal generation module is further configured to, in the normal read / write mode or the refresh mode, when the first control signal terminates, generate the second control signal.

[0010] In an exemplary embodiment of the present disclosure, the control signal generation module is further configured to, in the normal read / write mode or the refresh mode, control to generate a pulse duration of the second control signal that is greater than a pulse duration of the first control signal.

[0011] In an exemplary embodiment of the present disclosure, the second duration is 0.

[0012] In an exemplary embodiment of the present disclosure, the control signal generation module is further configured to, in the refresh mode, not generate the first control signal and directly generate the second control signal.

[0013] In an exemplary embodiment of the present disclosure, a negative voltage of the sense amplifier is controlled and supplied by a negative control signal, and the control signal generation module is further configured to, after generating the first control signal or the second control signal, control to generate the negative control signal.

[0014] In an exemplary embodiment of the present disclosure, it further includes: a word line, a bit line, and a complementary bit line, and the sense amplifier is disposed between the bit line and the complementary bit line; the control signal generation module is further configured to, before generating the first control signal and the second control signal, turn off a bit line balance control signal applied to the bit line and the complementary bit line; and apply a word line turn-on voltage to the word line to turn on a transistor connected to the word line.

[0015] In an exemplary embodiment of the present disclosure, it further includes: an activation window signal generation module and a refresh window signal generation module, and the activation window signal generation module and the refresh window signal generation module are respectively connected to the control signal generation module; the activation window signal generation module is configured to generate a memory block activation window signal, and the refresh window signal generation module is configured to generate a refresh window signal; the control signal generation module is configured to control the memory to enter the refresh mode when both the memory block activation window signal and the refresh window signal are obtained; and control the memory to enter the normal read / write mode when only the activation window signal is obtained.

[0016] In an exemplary embodiment of the present disclosure, the control signal generation module includes: a first delay sub-module, a second delay sub-module, and a first NAND gate; wherein, an input end of the first NAND gate is connected to an output end of the first delay sub-module and an output end of the second delay sub-module, and an output end of the first NAND gate outputs the first control signal; an input end of the second delay sub-module is connected to the output end of the first delay sub-module, an input end of the first delay sub-module is connected to the memory block activation window signal, and an output end of the second delay sub-module outputs the second control signal.

[0017] In an exemplary embodiment of the present disclosure, the first delay sub-module includes a first delay unit and a second NAND gate; wherein, the input end of the second NAND gate is connected to the output end of the first delay unit and the storage block activation window signal, and the input end of the first delay unit is connected to the storage block activation window signal.

[0018] In an exemplary embodiment of the present disclosure, the first delay unit includes: a first multiplexer and a first delay device and a second delay device connected to the first multiplexer; wherein, the first delay device and the second delay device are respectively used to delay the storage block activation window signal, and the delay duration of the first delay device is greater than that of the second delay device; the control end of the first multiplexer is connected to the refresh window signal, and is used to select and output the delay signal of the second delay device when the refresh window signal is generated, and select and output the delay signal of the first delay device when the refresh window signal is not generated.

[0019] In an exemplary embodiment of the present disclosure, the second delay sub-module includes a second delay unit and a first AND gate; wherein, the input ends of the first AND gate are respectively connected to the output end of the second delay unit and the output end of the first delay sub-module, and the input end of the second delay unit is connected to the output end of the first delay sub-module.

[0020] In an exemplary embodiment of the present disclosure, the second delay unit includes: a third delay device, a delay selection unit and a second multiplexer; wherein, the third delay device is used to delay the output signal of the first delay sub-module, the input end of the delay selection unit is connected to the output signal of the first delay sub-module, and the output end of the delay selection unit is connected to the input end of the second multiplexer; the control end of the second multiplexer is connected to the refresh window signal, and the second multiplexer is used to select and output the output signal of the delay selection unit when the refresh window signal is generated, and select and output the output signal of the first delay unit delayed by the third delay device when the refresh window signal is not generated.

[0021] In an exemplary embodiment of the present disclosure, the delay selection unit includes: a sub-delay unit and a sub-multiplexer; wherein, the input end of the sub-delay unit is connected to the output signal of the first delay sub-module, and the input end of the sub-multiplexer is connected to the output signal of the first delay sub-module and the output signal of the sub-delay unit; the control end of the sub-multiplexer is connected to a test signal, and under the action of the test signal, the pulse length of the first control signal is controlled to be 0.

[0022] In an exemplary embodiment of the present disclosure, the control signal generation module further includes: a bit line balance control signal generation sub-module, a word line turn-on voltage generation sub-module, and a third delay sub-module; wherein, an input end of the bit line balance control signal generation sub-module is connected to the storage block activation window signal, and an output end of the bit line balance control signal generation sub-module outputs the bit line balance control signal; an input end of the word line turn-on voltage generation sub-module is connected to an output end of the third delay sub-module, an output end of the word line turn-on voltage generation sub-module outputs the word line turn-on voltage, and an input end of the third delay sub-module is connected to the storage block activation window signal.

[0023] In an exemplary embodiment of the present disclosure, the third delay sub-module includes a third delay unit and a second AND gate; wherein, input ends of the second AND gate are connected to an output signal of the third delay unit and the storage block activation window signal, and an input end of the third delay unit is connected to the storage block activation window signal.

[0024] In an exemplary embodiment of the present disclosure, the third delay unit includes: a third multiplexer and a fourth delay device and a fifth delay device connected to the third multiplexer; wherein, the fourth delay device and the fifth delay device are respectively used for delaying the storage block activation window signal, and a delay duration of the fourth delay device is greater than a delay duration of the fifth delay device; a control end of the third multiplexer is connected to the refresh window signal, and is used for selecting and outputting a delay signal of the fifth delay device when the refresh window signal is generated, and selecting and outputting a delay signal of the fourth delay device when the refresh window signal is not generated.

[0025] According to a second aspect of the present disclosure, a memory control method is provided. The memory includes a sense amplifier, and a power supply voltage of the sense amplifier is controlled and supplied by a first control signal or a second control signal. The power supply voltage controlled and supplied by the first control signal is greater than the power supply voltage controlled and supplied by the second control signal. The method includes: in a normal read / write mode, controlling a pulse duration of the first control signal to be a first duration; in a refresh mode, controlling a pulse duration of the first control signal to be a second duration, and the second duration is less than the first duration.

[0026] In an exemplary embodiment of the present disclosure, the method further includes: in the normal read / write mode or the refresh mode, when the first control signal terminates, generating the second control signal.

[0027] In an exemplary embodiment of the present disclosure, the method further includes: in the normal read / write mode or the refresh mode, controlling the pulse duration of the second control signal to be greater than the pulse duration of the first control signal.

[0028] In an exemplary embodiment of the present disclosure, the second duration is 0.

[0029] In an exemplary embodiment of the present disclosure, the method further includes: in the refresh mode, not generating the first control signal and directly generating the second control signal.

[0030] In an exemplary embodiment of the present disclosure, the negative voltage of the sense amplifier is controlled and supplied by a negative control signal, and the method further includes: after generating the first control signal or the second control signal, controlling the generation of the negative control signal.

[0031] In an exemplary embodiment of the present disclosure, the memory further includes: word lines, bit lines, and complementary bit lines, and the sense amplifier is disposed between the bit line and the complementary bit line; before generating the first control signal or the second control signal, the method further includes: turning off the bit line balance control signal applied to the bit line and the complementary bit line; applying a word line turn-on voltage to the word line to turn on the transistor connected to the word line.

[0032] In an exemplary embodiment of the present disclosure, the method further includes: when both the activation window signal and the refresh window signal are acquired, controlling the memory to enter the refresh mode; when only the activation window signal is acquired, controlling the memory to enter the normal read / write mode.

[0033] According to a third aspect of the present disclosure, there is provided an electronic device, including: a plurality of memory blocks, a plurality of array controllers, and a plurality of the above-mentioned memory read / write circuits; wherein, the memory read / write circuits are disposed in the array controllers, and one memory read / write circuit correspondingly controls one array.

[0034] The technical solution provided by the present disclosure may include the following beneficial effects:

[0035] In an exemplary embodiment of the present disclosure, by setting the pulse duration of the first control signal generated in the refresh mode to be less than the pulse duration of the first control signal generated in the normal read / write mode, the supply duration of the higher first power supply voltage in the refresh mode is less than that in the normal read / write mode. In this way, it can not only meet the refresh requirements with relatively low requirements for tRCD performance, but also reduce the current loss caused by the relatively long duration of the first power supply voltage during the refresh process, avoid generating excessive instantaneous current in the refresh mode, and also reduce the requirements for the design of the load capacity of the first power supply voltage.

[0036] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The accompanying drawings herein are incorporated into the specification and form a part of the specification, showing embodiments consistent with the present disclosure, and are used together with the specification to explain the principles of the present disclosure. Obviously, the accompanying drawings in the following description are only some embodiments of the present disclosure, and those of ordinary skill in the art can obtain other drawings based on these drawings without creative efforts. In the drawings:

[0038] Figure 1 Schematically shows a structural diagram of a storage unit according to an exemplary embodiment of the present disclosure;

[0039] Figure 2 Schematically shows a structural diagram of a peripheral circuit in a DRAM according to an exemplary embodiment of the present disclosure;

[0040] Figure 3 Schematically shows a structural diagram of a memory block in a DRAM according to an exemplary embodiment of the present disclosure;

[0041] Figure 4 Schematically shows a structural diagram of a sense amplifier in a DRAM according to an exemplary embodiment of the present disclosure;

[0042] Figure 5 Schematically shows a control signal waveform diagram of a memory in the normal read / write mode according to an exemplary embodiment of the present disclosure;

[0043] Figure 6 Schematically shows a control signal waveform of a memory in the refresh mode according to an exemplary embodiment of the present disclosure Figure 1 ;

[0044] Figure 7 Schematically shows a control signal waveform of a memory in the refresh mode according to an exemplary embodiment of the present disclosure Figure 2 ;

[0045] Figure 8 Schematically shows a schematic circuit diagram of a control signal generation module in a memory read / write circuit according to an exemplary embodiment of the present disclosure;

[0046] Figure 9 Schematically shows a schematic circuit diagram of a first delay unit in a memory read / write circuit according to an exemplary embodiment of the present disclosure;

[0047] Figure 10 Schematically shows a schematic circuit diagram of a second delay unit in a memory read / write circuit according to an exemplary embodiment of the present disclosure;

[0048] Figure 11 Schematically shows a schematic circuit diagram of a third delay unit in a memory read / write circuit according to an exemplary embodiment of the present disclosure;

[0049] Figure 12 Schematically shows a flowchart of steps of a memory control method according to an exemplary embodiment of the present disclosure. Detailed implementation manners

[0050] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. Identical reference numerals in the figures denote identical or similar parts, and thus their repetitive description will be omitted.

[0051] In addition, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of the embodiments of the present disclosure. However, those skilled in the art will realize that the technical solutions of the present disclosure can be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. can be adopted. In other cases, well-known structures, methods, devices, implementations, materials, or operations are not shown or described in detail to avoid obscuring aspects of the present disclosure.

[0052] The block diagrams shown in the drawings are only functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities can be implemented in software form, or these functional entities or a part of these functional entities can be implemented in one or more software-hardened modules, or these functional entities can be implemented in different networks and / or processor devices and / or microcontroller devices.

[0053] Semiconductor memories are used in computers, servers, handheld devices such as mobile phones, printers, and many other electronic devices and applications. A memory array in a semiconductor memory includes a plurality of memory cells, and each memory cell stores at least one bit of information. DRAM is an example of such a semiconductor memory. This solution is preferably used in DRAM. Therefore, the following embodiments are described with reference to DRAM as a non-limiting example.

[0054] In a DRAM integrated circuit device, a memory cell array is typically arranged in rows and columns such that a specific memory cell can be addressed by specifying its row and column in the array. Word lines connect the rows to bit line sense amplifiers that detect data in a set of sense cells. Then, in a read operation, a subset of the data in the sense amplifiers is selected or "column selected" for output.

[0055] Referring to Figure 1 , each memory cell 100 in DRAM generally includes a capacitor 110, a transistor 120, a word line (WL) 130, and a bit line (BL) 140. The gate of the transistor 120 is connected to the word line 130, the drain of the transistor 120 is connected to the bit line 140, and the source of the transistor 120 is connected to the capacitor 110. The voltage signal on the word line 130 can control the opening or closing of the transistor 120, and then read the data information stored in the capacitor 110 through the bit line 140, or write the data information into the capacitor 110 through the bit line 140 for storage.

[0056] A memory block is composed of the above-mentioned multiple memory cells. The memory block generally occupies 50 - 65% of the entire area of the DRAM device, and the remaining area of the DRAM device is mainly composed of peripheral circuits. Referring to Figure 2 , a schematic structural diagram of a peripheral circuit is shown. As Figure 2 , the peripheral circuit of the DRAM device includes a Command Decoder 210, an Address Latch 220, a Refresh Address Counter (RAC) 230, an Address Mux (AM) 240, and a Pre-Decoder (Pre-D) 250. Among them, the Command Decoder 210 is used to decode commands CMD such as RESET_n, CKE, CK_t / CK_c, PAR, TEN, CS_n, ACT_n issued by the system, and the Address Latch 220 is used to temporarily store address codes A<16:0>, etc.

[0057] In addition, the peripheral circuit of the DRAM device further includes a memory read / write circuit provided by the embodiments of the present disclosure. Among them, the memory read / write circuit mainly includes: an activation window signal generation module 261, a refresh window signal generation module 262, and a control signal generation module 263; the activation window signal generation module 261 and the refresh window signal generation module 262 are respectively connected to the control signal generation module 263. The activation window signal generation module 261 is used to generate a memory bank activation window signal BANK ACTWindow, and the refresh window signal generation module 262 is used to generate a refresh window signal Refresh Window.

[0058] For the peripheral circuit of the DRAM device, the command decoder 210 and the address latch 220 therein are respectively connected to the activation window signal generation module 261, and are used to provide input signals for the activation window signal generation module 261, so that the activation window signal generation module 261 can generate a memory bank activation window signal BANK ACT Window. The refresh window signal generation module 262 is connected to the command decoder 210, and generates a refresh window signal RefreshWindow when a refresh signal is decoded.

[0059] Before introducing the control signal generation module 263 in the embodiments of the present disclosure, it is necessary to briefly describe the internal structure of a memory bank BANK in the memory. Refer to Figure 3 , which shows a schematic structural diagram of a memory bank. The memory bank 300 includes: bit lines BL, complementary bit lines BL_B, a plurality of word lines WL, and a plurality of memory cells 310. The plurality of memory cells 310 share the above-mentioned bit lines BL or complementary bit lines BL_B. In addition, the bit lines BL and complementary bit lines BL_B are also used to access write input drivers INPUTWrite Driver and INPUT_B Write Driver, and output output signals OUTPUT and OUTPUT_B.

[0060] In the exemplary embodiment of the present disclosure, the memory bank 300 further includes: a sensing module 320 and a bit line equalization module 330. Among them, the bit line equalization module 330 is used to pinch the bit lines BL and complementary bit lines BL_B under the action of a bit line equalization control signal BLEQ, so as to close the read / write operations on the memory cells 310.

[0061] Refer to Figure 3, the sensing module 320 mainly includes a sense amplifier. The sense amplifier (SA) can address multiple memory cells 310 through lines called bit lines BL or BL_B. A conventional sense amplifier is more specifically a differential amplifier that uses the bit line BL and the complementary bit line BL_B (as a reference line) to operate, so as to detect and amplify the voltage difference between a pair of bit lines BL and BL_B.

[0062] Referring to Figure 4 , the four transistors in the sense amplifier 400 are respectively the first transistor 410, the second transistor 420, the third transistor 430, and the fourth transistor 440. Among them, the first transistor 410 and the third transistor 430 are both PMOS (Positive channel Metal Oxide Semiconductor) transistors, and the second transistor 420 and the fourth transistor 440 are both NMOS (Negative channel Metal Oxide Semiconductor) transistors. If the data stored in the memory cell 310 is 1, during a read operation, the voltage of the word line WL is first raised to Vccp, and the transistor in the memory cell 310 is turned on. At this time, the memory cell 310 is in a read / write active state. A pair of bit lines BL and BL_B are disconnected from the voltage. When reading 1, a positive voltage is generated on the bit line BL. This voltage causes the fourth transistor 440 to conduct, so that the negative voltage on the N node is applied to the BL_B line and the gate of the first transistor 410 and makes it conduct. Finally, the Vcc voltage on the P node is applied to the BL line, so that it can be easily and accurately determined whether the data stored in the memory cell is 1 or 0 according to whether the voltage difference between a pair of bit lines is +Vcc or -Vcc.

[0063] As Figure 1 shown, for the capacitor 110, when writing 1, a voltage Vcc is applied to the bit line BL. This voltage Vcc will be conducted from its drain to the source through the conducting transistor 120 and finally loaded onto the plate of the capacitor 110. When writing 0, a voltage 0V is applied to the bit line BL, resulting in the voltage on the plate of the capacitor 110 also being 0V. The process of writing 1 or 0 to the capacitor 110 is the same.

[0064] When writing 1 or 0 to the capacitor 110, the voltage of the capacitor 110 plate is 1 or 0. After writing is completed, the BL voltage returns to V CC / 2. When reading data, after the transistor 120 is turned on, the capacitor 110 shares charge with the BL, causing the BL voltage to change. It can be determined whether the data stored in the memory cell is 1 or 0 according to whether the BL voltage increases or decreases.

[0065] During the read operation of the DRAM memory cell, a voltage greater than the turn-on voltage of the transistor 120 also needs to be applied to the word line WL of the memory cell to turn on the transistor 120. At this time, the charge on the capacitor 110 will be released to the bit lines BL and BL_B through the transistor 120.

[0066] For the memory read / write circuit provided by the embodiments of the present disclosure, whether in the normal read / write mode or the refresh mode, signal amplification needs to be completed through the sense amplifier.

[0067] In the memory read / write circuit provided by the exemplary embodiments of the present disclosure, the control signal generation module 263 is used to control the memory to enter the refresh mode when both the memory block activation window signal BANK ACT Window and the refresh window signal Refresh Window are obtained simultaneously; when only the activation window signal BANK ACT Window is obtained, the control memory enters the normal read / write mode.

[0068] Reference Figure 2 and Figure 4 , under the control of the control signal generation module 263 provided by the exemplary embodiments of the present disclosure, the power supply voltage of the sense amplifier 400 can be controlled and supplied by the first control signal SAP1, or can be controlled and supplied by the second control signal SAP2. Moreover, the first power supply voltage VDD controlled and supplied by the first control signal SAP1 is greater than the second power supply voltage VARY controlled and supplied by the second control signal SAP2.

[0069] By setting different power supply voltages VDD and VARY for the sense amplifier 400, at the initial stage of the normal read / write mode, a larger first power supply voltage VDD can be used for power supply to reduce the time consumed in the sensing and cell storage processes, so as to achieve the effect of optimizing performance such as the row address to column address delay time tRCD and the shortest cycle tRAS from the memory row being valid to precharging.

[0070] In the refresh mode, a different power supply method from that in the normal read / write mode can be set. For example, in the normal read / write mode, the pulse duration of the first control signal SAP1 is controlled to be the first duration, then in the normal read / write mode, the duration supplied by the first power supply voltage VDD is the first duration; in the refresh mode, the pulse duration of the first control signal SAP1 is controlled to be the second duration, then in the refresh mode, the duration supplied by the first power supply voltage VDD is the second duration.

[0071] In the exemplary embodiments of the present disclosure, the second duration is less than the first duration. That is to say, the duration of supplying the first power supply voltage VDD in the refresh mode is less than the duration of supplying the first power supply voltage VDD in the normal read / write mode. In this way, in the refresh mode where there is no high requirement for tRCD performance, by reducing the duration of supplying the first power supply voltage VDD, not only can the requirements of refreshing be met, but also the consumption of the VDD current during the refresh process can be reduced, avoiding the generation of excessive instantaneous current in the refresh mode, and also reducing the requirements for the design of the VDD carrying capacity.

[0072] Referring to Figure 5 , a control signal waveform diagram of the memory in the normal read / write mode is shown; referring to Figure 6 , a control signal waveform diagram of the memory in the refresh mode is shown. Based on the clock signal CLK, comparing Figure 5 and Figure 6 , in the refresh mode, the pulse duration T2 of the first control signal SAP1 is significantly less than the pulse duration T1 of the first control signal SAP1 in the normal read / write mode. Thus, in the refresh mode, the duration of supplying the first power supply voltage VDD can be reduced.

[0073] Even as Figure 7 shows, in the refresh mode, the control of the first control signal SAP1 is cancelled, and the pulse duration of the first control signal SAP1, that is, the second duration, is set to 0. In this case, in the refresh mode, the first control signal SAP1 is not generated, and the second control signal SAP2 is directly generated, that is, the sense amplifier 400 is not supplied with the first power supply voltage VDD, but directly supplied with the second power supply voltage VARY. Thereby, the instantaneous current of the memory in the refresh mode can be further reduced, and the VDD carrying capacity of the memory can be further improved.

[0074] In practical applications, the first power supply voltage VDD can be 1.2 - 1.3V, such as 1.25V, and the second power supply voltage VARY can be 0.9 - 1.1V, such as 1V. The exemplary embodiments of the present disclosure do not make special limitations on the specific values of the first power supply voltage VDD and the second power supply voltage VARY.

[0075] It should be noted that Figures 5 - 7 the PRE in

[0076] In an exemplary embodiment of the present disclosure, the above control signal generation module 263 is further configured to generate a second control signal SAP2 when the first control signal SAP1 terminates in a normal read / write mode or a refresh mode, and the pulse duration of the second control signal SAP2 is greater than that of the first control signal SAP1. That is to say, whether in the normal read / write mode or the refresh mode, the first power supply voltage VDD is only used in the initial stage, and in most subsequent read / write or refresh processes, the power supply voltage of the memory is supplied by the second power supply voltage VARY. The first power supply voltage VDD is mainly set initially to reduce latency and improve the read / write performance of the memory.

[0077] In an exemplary embodiment of the present disclosure, as Figure 4 shown, the negative voltage of the sense amplifier 400 is controlled and supplied by the negative control signal SAN. Referring to Figure 5 and Figure 6 it can be seen that the control signal generation module 263 is further configured to control the generation of the negative control signal SAN after generating the first control signal SAP1; referring to Figure 7 it can be seen that the control signal generation module 263 is further configured to control the generation of the negative control signal SAN after generating the second control signal SAP2.

[0078] As Figure 2 shown, in addition to controlling the generation of the first control signal SAP1, the second control signal SAP2, and the negative control signal SAN, the control signal generation module 263 provided in the embodiment of the present disclosure also controls the generation of the bit line balance control signal BLEQB and the word line turn-on voltage SWL. The control signal generation module 263 is further configured to turn off the bit line balance control signal BLEQ applied to the bit line BL and the complementary bit line BL_B before generating the first control signal SAP1 and the second control signal SAP2, so as to separate the pinched bit line BL and the complementary bit line BL_B (i.e., BLT and BLB in the figure are opened), thereby entering the read / write operation of the memory cell 310; then, apply the word line turn-on voltage SWL to the word line to turn on the transistor connected to the word line, and the voltage on the capacitor connected to the transistor is released to the bit line BL through charge sharing, thereby generating a voltage difference. Next, the sense amplifier 400 amplifies the above voltage difference, that is, generates the first power supply voltage SAP1, the second power supply voltage SAP2, and the negative control signal SAN. When the read / write process is almost over, turn off the word line turn-on voltage SWL, and at the same time, generate the bit line balance control signal BLEQB to pinch the bit line BL and the complementary bit line BL_B (i.e., the voltages of BLT and BLB in the figure are equal) to turn off the read / write operation of the memory cell 310 and complete the normal read / write process or the refresh process.

[0079] Based on this, referring to Figure 8, an exemplary embodiment of the present disclosure provides a circuit structure of a control signal generation module in a memory read / write circuit. Figure 8 In it, the control signal generation module includes: a first delay sub-module 810, a second delay sub-module 820, and a first NAND gate 830; wherein, the input terminals of the first NAND gate 830 are connected to the output terminal of the first delay sub-module 810 and the output terminal of the second delay sub-module 820, and the output terminal of the first NAND gate 830 outputs a first control signal SAP1.

[0080] The input terminal of the second delay sub-module 820 is connected to the output terminal of the first delay sub-module 810. The input terminal of the first delay sub-module 810 is connected to a memory block activation window signal BANK ACT Window or a delayed signal of the memory block activation window signal BANK ACT Window, and the output terminal of the second delay sub-module 820 outputs a second control signal SAP2.

[0081] In an exemplary embodiment of the present disclosure, the first delay sub-module 810 includes a first delay unit 811 and a second NAND gate 812; wherein, the input terminals of the second NAND gate 812 are connected to the output terminal of the first delay unit 811 and the memory block activation window signal BANK ACT Window, and the input terminal of the first delay unit 811 is connected to the memory block activation window signal BANK ACT Window.

[0082] Referring to Figure 9 As shown, the first delay unit 811 includes: a first multiplexer 910 and a first delay device 920 and a second delay device 930 connected to the first multiplexer 910; wherein, both the first delay device 920 and the second delay device 930 are used to delay the memory block activation window signal BANK ACT Window, and the delay duration of the first delay device 920 is greater than the delay duration of the second delay device 930; and the control terminal of the first multiplexer 910 is connected to a refresh window signal Refresh Window, and is used to select and output the delayed signal of the second delay device 930 when the refresh window signal Refresh Window is generated, and select and output the delayed signal of the first delay device 920 when the refresh window signal is not generated. In this way, when the refresh window signal Refresh Window is generated, the selected output delayed signal of the second delay device 930 has a shorter delay duration, and compared with the normal refresh mode, the pulse duration of the finally obtained first control signal SAP1 is shorter.

[0083] Referring to Figure 8As shown, the second delay sub-module 820 includes a second delay unit 821 and a first AND gate 822. Among them, the input terminals of the first AND gate 822 are respectively connected to the output terminal of the second delay unit 821 and the output terminal of the first delay sub-module 810, and the input terminal of the second delay unit 821 is connected to the output terminal of the first delay sub-module 810.

[0084] Referring to Figure 10 , in the exemplary embodiment of the present disclosure, the second delay unit 821 includes: a third delay device 1010, a delay selection unit 1034, and a second multiplexer 1020. Among them, the third delay device 1010 is used to delay the output signal of the first delay sub-module 810. The input terminal of the delay selection unit 1034 receives the output signal of the first delay sub-module 810, and the output terminal of the delay selection unit 1034 is connected to the input terminal of the second multiplexer 1020. The control terminal of the second multiplexer 1020 receives the refresh window signal Refresh Window. The second multiplexer 1020 is used to select and output the output signal of the delay selection unit 1034 when the refresh window signal Refresh Window is generated, and select and output the output signal of the third delay device 1010 when the refresh window signal is not generated.

[0085] Among them, the delay selection unit 1034 includes: a sub-delay unit 1030 and a sub-multiplexer 1040. Among them, the input terminal of the sub-delay unit 1030 receives the output signal of the first delay sub-module 810. The input terminals of the sub-multiplexer 1040 receive the output signal of the first delay sub-module 810 and the output signal of the sub-delay unit 1030, and the control terminal of the sub-multiplexer 1040 receives the test signal TM. In the case of having the test signal TM, the sub-multiplexer 1040 will select and output the output signal of the first delay sub-module 810. When the refresh window signal Refresh Window is generated, the output of the second delay unit 821 is the output signal of the first delay sub-module 810. After passing through the first AND gate 822, SAP1 will be turned off at the output terminal of the first NAND gate 830, that is, the pulse duration of the first control signal SAP1 is 0.

[0086] Referring to Figure 8As shown, the control signal generation module further includes: a bit line balance control signal generation sub-module 840, a word line turn-on voltage generation sub-module 850, and a third delay sub-module 860; wherein, the input end of the bit line balance control signal generation sub-module 840 is connected to the memory block activation window signal BANK ACT Window, and the output end of the bit line balance control signal generation sub-module 840 outputs a bit line balance control signal BLEQ; the input end of the word line turn-on voltage generation sub-module 850 is connected to the output end of the third delay sub-module 860, and the output end of the word line turn-on voltage generation sub-module 850 outputs a word line turn-on voltage SWL, and the input end of the third delay sub-module is connected to the memory block activation window signal BANK ACT Window.

[0087] After generating the memory block activation window signal BANK ACT Window, whether in the normal read / write mode or the refresh mode, it is necessary to generate the word line turn-on voltage SWL. As an example, as Figure 8 shown, the word line turn-on voltage SWL includes a plurality of delay units, a plurality of NAND gates, and a plurality of inverters, and the specific connection manner is not described herein again. Since the bit line balance control signal BLEQ needs to be turned off before generating the word line turn-on voltage SWL, therefore, compared with the bit line balance control signal generation sub-module 840, the word line turn-on voltage generation sub-module 850 is provided with an additional delay unit.

[0088] In addition, compared with the word line turn-on voltage generation sub-module 850, the bit line balance control signal generation sub-module 840 is provided with an inverter at the output end to achieve the purpose of turning off the generated bit line balance control signal BLEQ.

[0089] In practical applications, there can be various circuit connection manners for constituting the bit line balance control signal generation sub-module 840 and the word line turn-on voltage generation sub-module 850, and the exemplary embodiments of the present disclosure are not limited to Figure 8 this.

[0090] In the exemplary embodiments of the present disclosure, the third delay sub-module 860 includes a third delay unit 861 and a second AND gate 862; wherein, the input ends of the second AND gate 862 are connected to the output signal of the third delay unit 861 and the memory block activation window signal BANK ACT Window, and the input end of the third delay unit 861 is connected to the memory block activation window signal BANK ACT Window.

[0091] Referring to Figure 11, in an exemplary embodiment of the present disclosure, the third delay unit 861 includes: a third multiplexer 1110 and a fourth delay device 1120 and a fifth delay device 1130 connected to the third multiplexer 1110; wherein, the fourth delay device 1120 and the fifth delay device 1130 are respectively configured to delay the storage block activation window signal BANK ACT Window, and the delay duration of the fourth delay device 1120 is greater than that of the fifth delay device 1130; and the control terminal of the third multiplexer 1110 is connected to the refresh window signal Refresh Window, and is configured to select and output the delay signal of the fifth delay device 1130 when the refresh window signal Refresh Window is generated, and select and output the delay signal of the fourth delay device 1120 when the refresh window signal Refresh Window is not generated. In this way, when the refresh window signal Refresh Window is generated, the selected delay signal of the fifth delay device 1130 has a shorter delay duration. Compared with the normal refresh mode, on the basis of the first delay sub-module 810, the third delay sub-module 860 will further shorten the pulse duration of the first control signal SAP1.

[0092] In summary, in the exemplary embodiment of the present disclosure, by setting the pulse duration of the first control signal generated in the refresh mode to be less than the pulse duration of the first control signal generated in the normal read / write mode, the duration of supplying the larger first power supply voltage VDD in the refresh mode will be less than the duration of supplying the larger first power supply voltage VDD in the normal read / write mode. By reducing the duration of supplying the first power supply voltage VDD in the refresh mode, it can not only meet the refresh requirements with no high requirements for tRCD performance, but also reduce the consumption of the current of the first power supply voltage VDD during the refresh process, thereby reducing the probability of generating an excessive instantaneous current in the refresh mode, and also reducing the design requirements for the load capacity of the first power supply voltage VDD.

[0093] It should be noted that although the steps of the method in the present invention are described in a specific order in the drawings, this does not require or imply that these steps must be executed in this specific order, or that all the steps shown must be executed to achieve the desired result. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step for execution, and / or one step may be decomposed into multiple steps for execution, etc.

[0094] In addition, in the exemplary embodiment of the present invention, a memory control method is further provided. The memory control method is used to control a memory, which includes the aforementioned sense amplifier. Wherein, the power supply voltage of the sense amplifier is controlled and supplied by a first control signal SAP1 or a second control signal SAP2, and the power supply voltage VDD controlled and supplied by the first control signal SAP1 is greater than the power supply voltage VARY controlled and supplied by the second control signal SAP2.

[0095] Referring to Figure 12 , the memory control method includes the following steps:

[0096] Step S1210, in the normal read / write mode, control the pulse duration of the first control signal generated to be a first duration;

[0097] Step S1220, in the refresh mode, control the pulse duration of the first control signal generated to be a second duration, and the second duration is less than the first duration.

[0098] In an exemplary embodiment of the present disclosure, in the normal read / write mode or the refresh mode, when controlling the termination of the first control signal, generate the second control signal.

[0099] In an exemplary embodiment of the present disclosure, the memory control method further includes: in the normal read / write mode or the refresh mode, control the pulse duration of the second control signal generated to be greater than the pulse duration of the first control signal generated.

[0100] In an exemplary embodiment of the present disclosure, the second duration is 0.

[0101] In an exemplary embodiment of the present disclosure, the memory control method further includes: in the refresh mode, do not generate the first control signal, and directly generate the second control signal.

[0102] In an exemplary embodiment of the present disclosure, the negative voltage of the sense amplifier is controlled and supplied by a negative control signal SAN, and the memory control method further includes: after generating the first control signal or the second control signal, control the generation of the negative control signal.

[0103] In an exemplary embodiment of the present disclosure, the memory further includes: word lines, bit lines, and complementary bit lines, and the sense amplifier is disposed between the bit lines and the complementary bit lines; before generating the first control signal or the second control signal, the memory control method further includes: turning off the bit line balance control signal BLEQ applied to the bit lines and the complementary bit lines; applying a word line turn-on voltage SWL to the word lines to turn on the transistors connected to the word lines.

[0104] In an exemplary embodiment of the present disclosure, the memory control method further includes: when both the activation window signal BANK ACT Window and the refresh window signal Refresh Window are acquired simultaneously, controlling the memory to enter the refresh mode; when only the activation window signal BANK ACT Window is acquired, controlling the memory to enter the normal read / write mode.

[0105] The specific details of the above memory control method have been described in detail in the corresponding memory read / write circuit, so they will not be elaborated here.

[0106] In an exemplary embodiment of the present disclosure, an electronic device is further provided. The electronic device may include: a plurality of arrays, a plurality of array controllers, and a plurality of the above memory read / write circuits; wherein, the above memory read / write circuits are disposed in the array controllers, and one memory read / write circuit corresponds to controlling one array. The specific structural details of the memory read / write circuit have been described in detail in the above embodiments, so they will not be elaborated here.

[0107] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using a software program, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions described in the embodiments of the present disclosure are generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. The computer-readable storage medium may be any available medium that can be accessed by a computer, or a data storage device such as a server or a data center that includes one or more integrated media. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a magnetic tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid state disk (SSD)), etc. In the embodiments of the present disclosure, the computer may include the devices described above.

[0108] Although the present disclosure has been described in connection with various embodiments, it will be understood by those skilled in the art that other variations of the disclosed embodiments can be understood and effected while practicing the claimed disclosure, by studying the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the indefinite article "a" or "an" does not exclude a plurality. A single processor or other unit may implement several functions recited in the claims. Certain measures are recited in mutually different dependent claims, but this does not indicate that these measures cannot be combined to advantage.

[0109] Although the present disclosure has been described in connection with specific features and their embodiments, it will be apparent that various modifications and combinations can be made without departing from the spirit and scope of the disclosure. Accordingly, the specification and drawings are merely exemplary illustrations of the disclosure defined by the appended claims, and are considered to cover any and all modifications, variations, combinations, or equivalents within the scope of the disclosure. It is obvious that those skilled in the art can make various changes and modifications to the present disclosure without departing from the spirit and scope of the present disclosure. Thus, if these modifications and variations of the present disclosure fall within the scope of the claims of the present disclosure and their equivalent technologies, the present disclosure is also intended to include these changes and modifications.

Claims

1. A memory read / write circuit, characterized in that, Comprising: A sense amplifier, the supply voltage of the sense amplifier being controlled and supplied by a first control signal or a second control signal, the first supply voltage controlled and supplied by the first control signal being greater than the second supply voltage controlled and supplied by the second control signal; A control signal generation module, configured to, in a normal read / write mode, control the pulse duration of the first control signal to be a first duration; In a refresh mode, control the pulse duration of the first control signal to be a second duration, the second duration being less than the first duration; Further comprising: a word line, a bit line, and a complementary bit line, the sense amplifier being disposed between the bit line and the complementary bit line; The control signal generation module is further configured to, before generating the first control signal and the second control signal, turn off the bit line balance control signal applied to the bit line and the complementary bit line; apply a word line turn-on voltage to the word line to turn on the transistor connected to the word line; Further comprising: an activation window signal generation module and a refresh window signal generation module, the activation window signal generation module and the refresh window signal generation module being respectively connected to the control signal generation module; The activation window signal generation module is configured to generate a memory block activation window signal, and the refresh window signal generation module is configured to generate a refresh window signal; The control signal generation module is configured to, when obtaining both the memory block activation window signal and the refresh window signal, control the memory to enter the refresh mode; when obtaining only the activation window signal, control the memory to enter the normal read / write mode.

2. The memory read / write circuit according to claim 1, wherein The control signal generation module is further configured to, in the normal read / write mode or the refresh mode, generate the second control signal when the first control signal terminates.

3. The memory read / write circuit according to claim 2, wherein The control signal generation module is further configured to, in the normal read / write mode or the refresh mode, control the pulse duration of the second control signal to be greater than the pulse duration of the first control signal.

4. The memory read / write circuit according to claim 1, wherein The second duration is 0.

5. The memory read / write circuit according to claim 4, wherein The control signal generation module is further configured to, in the refresh mode, directly generate the second control signal without generating the first control signal.

6. The memory read / write circuit according to any one of claims 1-5, characterized in that, The negative voltage of the sense amplifier is controlled and supplied by a negative control signal, and the control signal generation module is further configured to, after generating the first control signal or the second control signal, control the generation of the negative control signal.

7. The memory read / write circuit according to claim 1, characterized in that The control signal generation module includes: a first delay sub-module, a second delay sub-module, and a first NAND gate; wherein, The input terminals of the first NAND gate are connected to the output terminal of the first delay sub-module and the output terminal of the second delay sub-module, and the output terminal of the first NAND gate outputs the first control signal; The input terminal of the second delay sub-module is connected to the output terminal of the first delay sub-module, the input terminal of the first delay sub-module is connected to the memory block activation window signal, and the output terminal of the second delay sub-module outputs the second control signal.

8. The memory read / write circuit according to claim 7, wherein, The first delay sub-module includes a first delay unit and a second NAND gate; wherein, The input end of the second NAND gate is connected to the output end of the first delay unit and the storage block activation window signal, and the input end of the first delay unit is connected to the storage block activation window signal.

9. The memory read / write circuit according to claim 8, wherein The first delay unit includes: a first multiplexer, a first delay device, and a second delay device connected to the first multiplexer; wherein, The first delay device and the second delay device are respectively used to delay the storage block activation window signal, and the delay duration of the first delay device is greater than that of the second delay device; The control end of the first multiplexer is connected to the refresh window signal, and is used to select and output the delay signal of the second delay device when the refresh window signal is generated, and select and output the delay signal of the first delay device when the refresh window signal is not generated.

10. The memory read / write circuit according to any one of claims 7-9, characterized in that, The second delay sub-module includes a second delay unit and a first AND gate; wherein, The input ends of the first AND gate are respectively connected to the output end of the second delay unit and the output end of the first delay sub-module, and the input end of the second delay unit is connected to the output end of the first delay sub-module.

11. The memory read / write circuit according to claim 10, wherein The second delay unit includes: a third delay device, a delay selection unit, and a second multiplexer; wherein, The third delay device is used to delay the output signal of the first delay sub-module, the input end of the delay selection unit is connected to the output signal of the first delay sub-module, and the output end of the delay selection unit is connected to the input end of the second multiplexer; The control end of the second multiplexer is connected to the refresh window signal, and the second multiplexer is used to select and output the output signal of the delay selection unit when the refresh window signal is generated, and select and output the output signal of the first delay unit delayed by the third delay device when the refresh window signal is not generated.

12. The memory read / write circuit according to claim 11, wherein The delay selection unit includes: a sub-delay unit and a sub-multiplexer; wherein, The input end of the sub-delay unit is connected to the output signal of the first delay sub-module, and the input ends of the sub-multiplexer are connected to the output signal of the first delay sub-module and the output signal of the sub-delay unit; The control end of the sub-multiplexer is connected to the test signal, and under the action of the test signal, controls the pulse length of the first control signal to be 0.

13. The memory read / write circuit according to claim 8 or 9, characterized in that, The control signal generation module further includes: a bit line balance control signal generation sub-module, a word line turn-on voltage generation sub-module, and a third delay sub-module; wherein, The input end of the bit line balance control signal generation sub-module is connected to the storage block activation window signal, and the output end of the bit line balance control signal generation sub-module outputs the bit line balance control signal; The input end of the word line turn-on voltage generation sub-module is connected to the output end of the third delay sub-module, the output end of the word line turn-on voltage generation sub-module outputs the word line turn-on voltage, and the input end of the third delay sub-module is connected to the storage block activation window signal.

14. The memory read / write circuit according to claim 13, wherein The third delay sub-module includes a third delay unit and a second AND gate; wherein, The input terminals of the second AND gate are connected to the output signal of the third delay unit and the storage block activation window signal, and the input terminal of the third delay unit is connected to the storage block activation window signal.

15. The memory read / write circuit according to claim 14, wherein The third delay unit includes: a third multiplexer and a fourth delay device and a fifth delay device connected to the third multiplexer; wherein, The fourth delay device and the fifth delay device are respectively used for delaying the storage block activation window signal, and the delay duration of the fourth delay device is greater than that of the fifth delay device; The control terminal of the third multiplexer is connected to the refresh window signal, and is used for selecting and outputting the delay signal of the fifth delay device when the refresh window signal is generated, and selecting and outputting the delay signal of the fourth delay device when the refresh window signal is not generated.

16. A memory control method, characterized in that, The memory includes a sense amplifier, and the power supply voltage of the sense amplifier is controlled and supplied by a first control signal or a second control signal. The power supply voltage controlled and supplied by the first control signal is greater than the power supply voltage controlled and supplied by the second control signal. The method includes: In the normal read / write mode, controlling the pulse duration of the first control signal generated to be a first duration; In the refresh mode, controlling the pulse duration of the first control signal generated to be a second duration, and the second duration is less than the first duration; The memory further includes: word lines, bit lines, and complementary bit lines. The sense amplifier is arranged between the bit lines and the complementary bit lines; before the first control signal or the second control signal is generated, the method further includes: Turning off the bit line balance control signal applied to the bit lines and the complementary bit lines; Applying a word line turn-on voltage to the word lines to turn on the transistors connected to the word lines; The method further includes: When the activation window signal and the refresh window signal are acquired simultaneously, controlling the memory to enter the refresh mode; When only the activation window signal is acquired, controlling the memory to enter the normal read / write mode.

17. The memory control method according to claim 16, wherein, The method further includes: In the normal read / write mode or the refresh mode, when the first control signal terminates, generating the second control signal.

18. The memory control method according to claim 17, wherein The method further includes: In the normal read / write mode or the refresh mode, controlling the pulse duration of the second control signal generated to be greater than the pulse duration of the first control signal generated.

19. The memory control method according to claim 16, wherein The second duration is 0.

20. The memory control method according to claim 19, wherein The method further includes: In the refresh mode, not generating the first control signal and directly generating the second control signal.

21. The memory control method according to any one of claims 16-20, characterized in that, The negative voltage of the sense amplifier is controlled and supplied by a negative control signal, and the method further includes: After the first control signal or the second control signal is generated, controlling the generation of the negative control signal.

22. An electronic device, characterized in that, Including: A plurality of storage blocks, a plurality of array controllers, and a plurality of memory read / write circuits as described in any one of claims 1-15; wherein, The memory read / write circuits are arranged in the array controllers, and one memory read / write circuit correspondingly controls one array.

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