A method, apparatus, and storage medium for testing a storage array structure

Abstract

The present application provides a method, an apparatus, and a storage medium for testing a storage array structure. The method includes: writing storage data into the storage array to be tested corresponding to each preset test mode, where each preset test mode belongs to one of a preset test mode library; repeatedly performing a row attack test on the storage array to be tested, and stopping the row attack test if a bit flip error occurs in the storage data, so as to obtain the number of row attack tests corresponding to the storage array to be tested under each preset test mode. A bit flip error indicates that the storage data has changed; determining a target preset test mode corresponding to the storage array to be tested in the preset test mode library based on the number of row attack tests; and determining the array structure of the storage array to be tested based on the target preset test mode. The present application can reduce the cost of reverse design and simplify the reverse design process.

Description

Technical Field

[0001] This application relates to the field of integrated circuit design, and particularly to a method and apparatus for testing a memory array structure, and a storage medium. Background Art

[0002] In the process of integrated circuit design, reverse design is often required. Reverse design means analyzing and learning from the internal structure of an existing chip.

[0003] However, due to the micro-size and large-scale integration of chips, reverse design requires the use of special reverse testing equipment, which is costly and complex to operate. And as the critical dimension of chips continues to decrease, reverse testing equipment is increasingly difficult to meet the needs of reverse design. Summary of the Invention

[0004] Embodiments of this application are expected to propose a method and apparatus for testing a memory array structure, and a storage medium, which can determine the memory array structure without using traditional reverse testing equipment, thereby reducing the cost of reverse design and simplifying the reverse design process.

[0005] The technical solution of this application is implemented as follows:

[0006] Embodiments of this application provide a method for testing a memory array structure, the method including:

[0007] For each preset test mode, write storage data into the memory array to be tested; each preset test mode belongs to one of a preset test mode library;

[0008] Repeat row attack testing on the memory array to be tested, and if a bit flip error occurs in the storage data, stop the row attack testing to obtain the number of row attack tests corresponding to the memory array to be tested in each preset test mode; the bit flip error indicates that the storage data has changed;

[0009] Based on the number of row attack tests, determine the target preset test mode corresponding to the memory array to be tested in the preset test mode library;

[0010] Based on the target preset test mode, determine the array structure of the memory array to be tested.

[0011] Embodiments of this application also provide a device for testing a memory array structure, the device including:

[0012] A writing unit, configured to write storage data into the memory array to be tested for each preset test mode; each preset test mode belongs to one of a preset test mode library;

[0013] A row attack test unit is configured to repeatedly perform row attack tests on the storage array to be tested. If a bit flip error occurs in the stored data, the row attack test is stopped, and the number of row attack tests corresponding to the storage array to be tested in each preset test mode is obtained. The bit flip error indicates that the stored data has changed.

[0014] A determination unit is configured to determine, based on the number of row attack tests, the target preset test mode corresponding to the storage array to be tested in the preset test mode library; and to determine the array structure of the storage array to be tested based on the target preset test mode.

[0015] An embodiment of the present application further provides a storage array structure testing device, which includes:

[0016] A memory for storing executable instructions;

[0017] A processor, when executing the executable instructions stored in the memory, implements the storage array structure testing method in the above solution.

[0018] Thus, the embodiment of the present application provides a storage array structure testing method, device, and storage medium, which can write stored data into the storage array to be tested corresponding to each preset test mode; then, repeatedly perform row attack tests on the storage array to be tested. If a bit flip error occurs in the stored data, the row attack test is stopped, and the number of row attack tests corresponding to the storage array to be tested in each preset test mode is obtained, where the bit flip error indicates that the stored data has changed; then, based on the number of row attack tests, the target preset test mode corresponding to the storage array to be tested is determined in the preset test mode library; finally, the array structure of the storage array to be tested is determined based on the target preset test mode. In this way, the determination of the storage array structure is completed without relying on traditional reverse testing equipment, avoiding problems such as high cost and complex process brought by using traditional reverse design methods, thereby reducing the cost of reverse design and simplifying the reverse design process. Description of the Drawings

[0019] Figure 1 It is a schematic architecture diagram of the storage array structure testing method provided by the embodiment of the present application;

[0020] Figure 2 It is the flow of the storage array structure testing method provided by the embodiment of the present application Figure 1 ;

[0021] Figure 3 It is a schematic diagram of the effect of the storage array structure testing method provided by the embodiment of the present application Figure 1 ;

[0022] Figure 4Schematic diagram of the effect of the storage array structure testing method provided by the embodiments of the present application Figure 2 ;

[0023] Figure 5 Schematic diagram of the effect of the storage array structure testing method provided by the embodiments of the present application Figure 3 ;

[0024] Figure 6 Schematic diagram of the effect of the storage array structure testing method provided by the embodiments of the present application Figure 4 ;

[0025] Figure 7 Flow chart of the storage array structure testing method provided by the embodiments of the present application Figure 2 ;

[0026] Figure 8 Flow chart of the storage array structure testing method provided by the embodiments of the present application Figure 3 ;

[0027] Figure 9 Flow chart of the storage array structure testing method provided by the embodiments of the present application Figure 4 ;

[0028] Figure 10 Flow chart of the storage array structure testing method provided by the embodiments of the present application Figure 5 ;

[0029] Figure 11 Flow chart of the storage array structure testing method provided by the embodiments of the present application Figure 6 ;

[0030] Figure 12 Schematic diagram of the structure of the storage array structure testing device provided by the embodiments of the present application Figure 1 ;

[0031] Figure 13 Schematic diagram of the structure of the storage array structure testing device provided by the embodiments of the present application Figure 2 . Detailed implementation manners

[0032] In order to make the objectives, technical solutions and advantages of the present application clearer, the technical solutions of the present application will be further elaborated in detail below in conjunction with the accompanying drawings and embodiments. The described embodiments should not be regarded as limitations on the present application. All other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the scope of protection of the present application.

[0033] In the following description, reference is made to "some embodiments", which describe a subset of all possible embodiments. However, it is understood that "some embodiments" may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0034] If a similar description such as "first / second" appears in the application documents, the following explanation shall be added. In the following description, the terms "first / second / third" are only used to distinguish similar objects and do not represent a specific order for the objects. It is understood that "first / second / third" can be interchanged in a specific order or sequence when permitted, so that the embodiments of the present application described herein can be implemented in an order other than that illustrated or described herein.

[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0036] In the process of integrated circuit design, it is often necessary to analyze and draw on the internal structure of existing chips, that is, reverse design is required. Especially for manufacturers that started the design and production relatively late, there is a large gap from international advanced design and production manufacturers, and they need to learn from others' design methods and experiences.

[0037] However, the design methods of each manufacturer are generally not publicly available. If you want to understand the internal structure of its chips, generally a dedicated reverse test device needs to be used, which is costly and complex to operate. For example, ADVANT EST T5503HS is a conventional ATE (Automatic Test Equipment) test station, which can complete certain SDRAM (Synchronous Dynamic Random-Access Memory) Array test analysis work, but its price is expensive, and the price of each unit can be as high as $2 million. At the same time, the operation process of the ATE test station is complex, and its operation process includes: sample preparation (Depot); delayer (Delayering); imaging (Imagi ng); stitching (Stitching), alignment (Aligning); annotation (Annotation); extraction (Extracti on), analysis (Analysis); schematic capture (Schematic Capture); netlist generation (Netlist); simulation (Simulation); verification (Verification); reporting (Reports). Therefore, the ATE test station is not easy to popularize.

[0038] On the other hand, with the continuous development of integrated circuit process technology, the integration degree of chips is getting higher and higher, and the test and analysis work of the internal structure of chips is becoming more and more difficult. Existing test equipment is increasingly difficult to meet the needs of reverse design.

[0039] Based on the above problems, embodiments of the present application are expected to propose a method, device and storage medium for testing a storage array structure, which can determine the storage array structure without relying on traditional reverse test equipment, thereby reducing the cost of reverse design and simplifying the reverse design process.

[0040] Figure 1 is an optional schematic architecture diagram of the storage array structure testing method provided by the embodiments of the present application. As Figure 1 shown, embodiments of the present application can perform test and analysis on synchronous dynamic random access memory 02 (SDRAM) based on field programmable gate array 01 (Field Programmable Gate Array, FPGA). Embodiments of the present application can develop a custom memory control unit 03 (Memory Controller) and a DDR (Double Data Rate, double data rate synchronous dynamic random access memory) port physical layer 04 (PHY, Physical Layer) based on the platform of FPGA 01 to send any instruction that meets the requirements of JEDEC (Joint Electronic Device Engineering Council) to any specified address in SDRAM 02. Among them, the memory control unit 03 and the DDR port physical layer 04 are both located inside the CPU or SoC main control chip. The memory control unit 03 is connected to the DDR port physical layer 04, and the DDR port physical layer 04 is externally connected to SDRAM 02. The memory control unit 03 is responsible for sending instruction information such as read / write to the DDR port physical layer 04; the DDR port physical layer 04 translates these instruction information into control signals and transmits them to each pin on SDRAM 02.

[0041] Figure 2 is an optional flowchart of the storage array structure testing method provided by the embodiments of the present application, which will be described in combination with the Figure 2 steps shown.

[0042] S101. Write storage data into the storage array to be tested corresponding to each preset test mode; each preset test mode belongs to one of the preset test mode libraries.

[0043] In embodiments of the present application, the test device can write storage data into the storage array to be tested corresponding to each preset test mode.

[0044] It should be noted that a preset test mode library is pre-set in the test device, and different preset test modes correspond to different stored data; writing a certain stored data into the storage array makes the storage cells in the storage array have corresponding charge storage conditions. Technicians can prepare storage arrays to be tested belonging to the same batch for analysis and testing, and these storage arrays to be tested have the same array structure. Analyzing and testing all these storage arrays to be tested will result in more reliable analysis results compared to only analyzing and testing a single storage array to be tested.

[0045] In the embodiment of the present application, first, the test device can divide the storage cells in the storage array to be tested into an aggressor row and a victim row, and the aggressor row and the victim row are adjacent to each other in the array structure. As Figure 3 shown, A10, A11, A12, and A13 are divided into the aggressor row, and the word lines (WL) where they are located are the aggressor row word lines WL AGGR ; V00, V01, V02, and V03, as well as V20, V21, V22, and V23 are divided into the victim row, and the word lines where they are located are the victim row word lines WL VICT .

[0046] Then, the test device can write the aggressor row stored data into the aggressor row and the victim row stored data into the victim row. Among them, the aggressor row stored data is represented by alternating binary codes, and the victim row stored data is represented by consecutive identical binary codes. For example, the test device can, corresponding to the first preset test mode, alternately write 01010101 and 10101010 into the aggressor row in sequence, which is represented in hexadecimal as 0x55 and 0xAA, that is, write 0x55, AA, 55, AA... or 0xAA, 55, AA, 55... into the aggressor row in sequence; and continuously write 00000000 or 11111111 into the victim row, which is represented in hexadecimal as 0x00 or 0xFF, that is, write 0x00, 00, 00, 00... or 0xFF, FF, FF, FF... into the victim row in sequence. Another example is that the test device can, corresponding to the second preset test mode, continuously write 01010101 or 10101010 into the aggressor row, that is, continuously write 0x55, 55, 55, 55... or 0xAA, AA, AA, AA... into the aggressor row; and continuously write 00000000 or 11111111 into the victim row, that is, write 0x00, 00, 00, 00... or 0xFF, FF, FF, FF... into the victim row in sequence.

[0047] S102. Repeatedly perform row attack tests on the storage array to be tested. If a bit flip error occurs in the stored data, stop the row attack test and obtain the number of row attack tests corresponding to the storage array to be tested under each preset test mode; a bit flip error indicates that the stored data has changed.

[0048] In the embodiment of the present application, after writing the stored data, the test device can repeatedly perform row attack tests on the storage array to be tested; if a bit flip error is detected in the stored data, stop the row attack test and record the corresponding number of row attack tests.

[0049] In the embodiment of the application, the test device can perform row attack tests in the way of Row Hammer. Refer to Figure 3 , the test device can attack the storage unit row A 10 、A 11 、A 12 and A 13 Quickly repeat and alternately perform Activation (ACT) and Precharge (PRE). Each time activation and precharge are performed, it is equivalent to a quick access to the attacked storage unit row, which will interfere with the adjacent victim storage unit rows. The victim storage unit rows will discharge slowly under frequent interference. When the stored charge of the victim storage unit is lower than the critical value with the discharge, a bit flip error will occur, that is, the stored data has changed, for example, from 1 to 0.

[0050] At the same time, the test device can read the existing stored data in the storage array to be tested at any time and compare it with the written stored data; if the read stored data is inconsistent with the written stored data, that is, a bit flip error occurs, stop the row attack test and record the corresponding test times.

[0051] S103. Based on the number of row attack tests, determine the target preset test mode corresponding to the storage array to be tested in the preset test mode library.

[0052] In the embodiment of the present application, for the storage array to be tested, the test device can determine the target preset test mode corresponding to the storage array to be tested in the preset test mode library based on the number of row attack tests.

[0053] In the embodiment of the present application, the test device can determine the minimum number of times in the number of row attack tests as the target test times; then in the preset test mode library, determine the target preset test mode corresponding to the target test times. Among them, the target test times are the minimum number of times, and the corresponding target preset test mode is the test mode most likely to cause bit flip errors.

[0054] For example, for a certain preset test mode, 10,000 ACT-PRE operations are performed on a certain attacked memory cell row in the memory array under test, and then it is checked whether the data in the adjacent victim memory cell row has an error (i.e., a bit flip occurs). If there is no error, then 20,000 ACT-PRE operations are performed on the attacked memory cell row, and then it is checked again whether the data in the adjacent victim memory cell row has an error. This is repeated until a bit flip occurs in the adjacent victim memory cell row, and the row attack test times corresponding to the preset test mode are recorded. For example, after 100,000 ACT-PRE operations, a bit flip starts to occur in the adjacent victim memory cell row. Then, for another preset test mode, the above process is repeated for the same attacked row in the memory array under test until a bit flip occurs in the adjacent victim memory cell row. For example, after 200,000 ACT-PRE operations, a bit flip starts to occur in the adjacent victim memory cell row. Then, the preset test mode corresponding to 100,000 times can be determined as the target preset test mode.

[0055] S104. Based on the target preset test mode, determine the array structure of the memory array under test.

[0056] In the embodiments of the present application, the test device can obtain the target preset test mode of the memory array under test according to the above method. After obtaining all the target preset test modes corresponding to the memory array under test with the same array structure, the array structure of the memory array under test can be determined based on these target preset test modes.

[0057] It should be noted that the difficulty of the bit flip error occurring in the victim memory cell row is related to the storage charge status of the surrounding memory cells. As Figure 4 shown, when the victim memory cell row V 20 is in a fully charged state, and the surrounding memory cells are all in an uncharged state. At this time, the victim memory cell row V 20 is most vulnerable to Row Hammer and a bit flip error occurs, that is, a bit flip error can occur through the least number of row attack tests. Therefore, the number of row attack tests can reflect the charge status of the memory cells around the victim memory cell row; combined with the stored data content written, the array structure of the memory array under test can be deduced.

[0058] For example, if the target preset test mode of the memory array under test is the above first preset test mode, the test device can determine its array structure as the first array structure. The first array structure is characterized by concentrating N consecutive transmission bits of the m-th signal; where m is greater than or equal to 0 and less than or equal to M - 1; M and N are multiples of 8. Figure 5 Characterizes the characteristics of the first array structure, such as Figure 5As shown, eight consecutive transmission bits (burst length) Y = 0 to Y = 7 of the 0th signal DQ0 are centrally placed in a group, where the burst length represents the amount of data throughput by the memory array at one time.

[0059] For another example, if the target preset test mode of the memory array to be tested is the second preset test mode as described above, the test device can determine that its array structure is the second array structure. The second array structure is characterized by centrally placing the nth consecutive transmission bits of M signals; where n is greater than or equal to 0 and less than or equal to N - 1; M and N are multiples of 8. Figure 6 Characterizes the characteristics of the second array structure, such as Figure 6 As shown, the 0th consecutive transmission bit Y = 0 of the 8 signals DQ0 to DQ7 is centrally placed in a group.

[0060] It can be understood that according to the preset test mode, storage data is written into the memory array to be tested, and then the row attack test is repeatedly performed on the memory array to be tested, and the number of row attack tests when bit flips occur is recorded to determine the target preset test mode. Since the target preset test modes most prone to bit flips corresponding to different array structures are different, the array structure of the memory array to be tested can be deduced by determining the target preset test mode. In this way, without relying on expensive and complex test machines, the array structure of the memory array can be determined only based on the FPGA platform, reducing the cost of reverse design and simplifying the reverse design process.

[0061] In some embodiments of the present application, the memory array to be tested includes: an attacking memory cell row and a victim memory cell row; the attacking memory cell row and the victim memory cell row are adjacent to each other in the array structure of the memory array to be tested.

[0062] The storage data includes: attacking row storage data and victim row storage data. The attacking row storage data is characterized by alternating binary codes, such as 01010101 or 10101010, which is represented in hexadecimal as 0x55 or 0xAA. The victim row storage data is characterized by consecutive identical binary codes, such as 00000000 or 11111111, which is represented in hexadecimal as 0x00 or 0xFF.

[0063] The preset test mode library includes: a first preset test mode and a second preset test mode. The array structure includes: a first array structure and a second array structure.

[0064] In some embodiments of the present application, it can be achieved through Figure 7 S1011 shown in Figure 2 S101 shown in will be described in combination with each step.

[0065] S1011. For each preset test mode, write attack row storage data to the attacked storage cell row and write victim row storage data to the victim storage cell row.

[0066] In the embodiments of the present application, the test device can, for each preset test mode, write attack row storage data to the attacked storage cell row in the storage array to be tested and write victim row storage data to the victim storage cell row in the storage array to be tested.

[0067] It should be noted that when the victim storage cell row is in a fully charged state while the surrounding storage cells are in an uncharged state, at this time, the victim storage cell row is most vulnerable to bit flip errors caused by Row Hammer. Therefore, by writing alternating binary codes to the attacked storage cell row and writing consecutive identical binary codes to the victim storage cell row, the above situation can be generated in the storage cells. For example, Figure 5 C1, C2, and C3 in Figure 6 and C4, C5, and C6 in

[0068] are all in a fully charged state while the surrounding storage cells are in an uncharged state.

[0069] In some embodiments of the present application, S104 shown in Figure 2 can be implemented through S1041, and will be described in combination with each step.

[0070] S1041. If the target preset test mode is the first preset test mode, then based on the first preset test mode, determine the first array structure of the storage array to be tested.

[0071] In the embodiments of the present application, the test device can write storage data to the attacked storage cell row and the victim storage cell row respectively corresponding to the first preset test mode. And if the first preset test mode is finally confirmed as the target preset test mode, then the test device can, based on the first preset test mode, determine that the array structure of the storage array to be tested is the first array structure.

[0072] For example, the first preset test mode represents writing 0x55, AA, 55, AA... or 0xAA, 55, AA, 55... to the rows of the attacking memory cells in sequence; and writing 0x00, 00, 00, 00... or 0xFF, FF, FF, FF... to the rows of the victim memory cells in sequence. Then the first array structure represents concentrating N consecutive transmission bits of the m-th signal; where m is greater than or equal to 0 and less than or equal to M - 1; M and N are multiples of 8.

[0073] In some embodiments of the present application, it can be implemented through S1042 Figure 2 S104 shown will be described in combination with each step.

[0074] S1042: If the target preset test mode is the second preset test mode, then based on the second preset test mode, determine the second array structure of the storage array to be tested.

[0075] In the embodiments of the present application, the test device can write storage data to the rows of the attacking memory cells and the rows of the victim memory cells respectively corresponding to the second preset test mode. And if the second preset test mode is finally confirmed as the target preset test mode, the test device can determine that the array structures of at least two storage arrays to be tested are the second array structure based on the second preset test mode.

[0076] For example, the second preset test mode represents writing 0x55, 55, 55, 55... or 0xAA, AA, AA, AA... to the rows of the attacking memory cells continuously; and writing 0x00, 00, 00, 00... or 0xFF, FF, FF, FF... to the rows of the victim memory cells in sequence. Then the second array structure represents concentrating the n-th consecutive transmission bit of M signals; where n is greater than or equal to 0 and less than or equal to N - 1; M and N are multiples of 8.

[0077] In some embodiments of the present application, the storage data of the attacking row includes: the first sub-storage data of the attacking row and the second sub-storage data of the attacking row; the numerical values of the corresponding data bits of the first sub-storage data of the attacking row and the second sub-storage data of the attacking row are opposite, such as 0x55 and 0xAA. The storage data of the victim row includes: the first sub-storage data of the victim row and the second sub-storage data of the victim row; the numerical values of the corresponding data bits of the first sub-storage data of the victim row and the second sub-storage data of the victim row are opposite, such as 0x00 and 0xFF.

[0078] In some embodiments of the present application, it can be implemented through S201~S204 Figure 7 S1011 shown will be described in combination with each step.

[0079] S201. Corresponding to the first preset test mode, alternately write the first attack row sub-storage data and the second attack row sub-storage data to the attack storage unit rows in sequence; and continuously write the first victim row sub-storage data to the victim storage unit rows.

[0080] In the embodiments of the present application, the test device can, corresponding to the first preset test mode, alternately write the first attack row sub-storage data and the second attack row sub-storage data to the attack storage unit rows in sequence, and continuously write the first victim row sub-storage data to the victim storage unit rows. For example, the test device can alternately write 0x55, AA, 55, AA... to the attack storage unit rows, and continuously write 0x00, 00, 00, 00... to the victim storage unit rows.

[0081] S202. Corresponding to the first preset test mode, alternately write the first attack row sub-storage data and the second attack row sub-storage data to the attack storage unit rows in sequence; and continuously write the second victim row sub-storage data to the victim storage unit rows.

[0082] In the embodiments of the present application, the test device can also, corresponding to the first preset test mode, alternately write the first attack row sub-storage data and the second attack row sub-storage data to the attack storage unit rows in sequence, and continuously write the second victim row sub-storage data to the victim storage unit rows. For example, the test device can alternately write 0x55, AA, 55, AA... to the attack storage unit rows, and continuously write 0xFF, FF, FF, FF... to the victim storage unit rows.

[0083] S203. Corresponding to the first preset test mode, alternately write the second attack row sub-storage data and the first attack row sub-storage data to the attack storage unit rows in sequence; and continuously write the first victim row sub-storage data to the victim storage unit rows.

[0084] In the embodiments of the present application, the test device can also, corresponding to the first preset test mode, alternately write the second attack row sub-storage data and the first attack row sub-storage data to the attack storage unit rows in sequence, and continuously write the first victim row sub-storage data to the victim storage unit rows. For example, the test device can alternately write 0xAA, 55, AA, 55... to the attack storage unit rows, and continuously write 0x00, 00, 00, 00... to the victim storage unit rows.

[0085] S204. Corresponding to the first preset test mode, alternately write the second attack row sub-storage data and the first attack row sub-storage data to the attack storage unit rows in sequence; and continuously write the second victim row sub-storage data to the victim storage unit rows.

[0086] In the embodiments of the present application, the test device may also correspond to the first preset test mode, and alternately write the second attack row sub-storage data and the first attack row sub-storage data to the attack storage unit rows in sequence, and continuously write the second victim row sub-storage data to the victim storage unit rows. For example, the test device may alternately write 0xAA, 55, AA, 55... to the attack storage unit rows in sequence, and continuously write 0xFF, FF, FF, FF... to the victim storage unit rows.

[0087] In some embodiments of the present application, it can be implemented through S301 to S304 Figure 7 S1011 shown will be described in combination with each step.

[0088] S301: Corresponding to the second preset test mode, continuously write the first attack row sub-storage data to the attack storage unit rows; and continuously write the first victim row sub-storage data to the victim storage unit rows.

[0089] In the embodiments of the present application, the test device may correspond to the second preset test mode, continuously write the first attack row sub-storage data to the attack storage unit rows, and continuously write the first victim row sub-storage data to the victim storage unit rows. For example, the test device may continuously write 0x55, 55, 55, 55... to the attack storage unit rows, and continuously write 0x00, 00, 00, 00... to the victim storage unit rows.

[0090] S302: Corresponding to the second preset test mode, continuously write the first attack row sub-storage data to the attack storage unit rows; and continuously write the second victim row sub-storage data to the victim storage unit rows.

[0091] In the embodiments of the present application, the test device may also correspond to the second preset test mode, continuously write the first attack row sub-storage data to the attack storage unit rows, and continuously write the second victim row sub-storage data to the victim storage unit rows. For example, the test device may continuously write 0x55, 55, 55, 55... to the attack storage unit rows, and continuously write 0xFF, FF, FF, FF... to the victim storage unit rows.

[0092] S303: Corresponding to the second preset test mode, continuously write the second attack row sub-storage data to the attack storage unit rows; and continuously write the first victim row sub-storage data to the victim storage unit rows.

[0093] In the embodiments of the present application, the test device may also correspond to the second preset test mode, continuously write the second attack row sub-storage data to the attack storage unit row, and continuously write the first victim row sub-storage data to the victim storage unit row. For example, the test device may continuously write 0xAA, AA, AA, AA... to the attack storage unit row, and continuously write 0x00, 00, 00, 00... to the victim storage unit row.

[0094] S304. Corresponding to the second preset test mode, continuously write the second attack row sub-storage data to the attack storage unit row; and continuously write the second victim row sub-storage data to the victim storage unit row.

[0095] In the embodiments of the present application, the test device may also correspond to the second preset test mode, continuously write the second attack row sub-storage data to the attack storage unit row, and continuously write the second victim row sub-storage data to the victim storage unit row. For example, the test device may continuously write 0xAA, AA, AA, AA... to the attack storage unit row, and continuously write 0xFF, FF, FF, FF... to the victim storage unit row.

[0096] In some embodiments of the present application, the row attack test includes: fast access; which can be implemented through S1021 Figure 2 The S102 shown will be described in combination with each step.

[0097] S1021. Repeatedly perform fast access on the attack storage unit row.

[0098] In the embodiments of the present application, the test device may repeatedly perform fast access on the attack storage unit row, thereby interfering with the adjacent victim storage unit rows. The victim storage unit rows will discharge slowly under frequent interference. When the charge stored in the victim storage unit is lower than the critical value due to discharge, a bit flip error will occur, that is, the stored data will change, for example, from 1 to 0.

[0099] In some embodiments of the present application, it can be achieved through Figure 8 The above S1021 shown by S1022 - S1023 will be described in combination with each step.

[0100] S1022. Quickly activate and precharge the attack storage unit row, thereby completing one fast access to the attack storage unit row.

[0101] In the embodiments of the present application, the test device may quickly perform ACT and PRE on the attack storage unit row, thereby completing one fast access to the attack storage unit row.

[0102] S1023. Repeat this process to complete the fast access to the repeated attack on the storage unit rows.

[0103] In the embodiments of the present application, the test device can perform ACT-PRE-ACT-PRE... on the repeated attack on the storage unit rows to complete the repeated fast access.

[0104] In some embodiments of the present application, it can be achieved through Figure 9 S1031 to S1032 shown in Figure 2 S103 shown, and will be described in conjunction with each step.

[0105] S1031. Determine the minimum target test times among the row attack test times.

[0106] In the embodiments of the present application, the test device can determine the minimum target test times among the row attack test times for the storage array to be tested.

[0107] S1032. In the preset test mode library, determine the target preset test mode corresponding to the target test times.

[0108] In the embodiments of the present application, if the target test times are the minimum times, the corresponding target preset test mode is the test mode in which bit flip errors are most likely to occur. The test device can determine the test mode in which bit flip errors are most likely to occur in the preset test mode library as the target preset test mode.

[0109] It can be understood that by determining the test mode in which bit flip errors are most likely to occur as the target preset test mode, the array structure of the storage array to be tested can be deduced inversely. In this way, without relying on expensive and complex test machines, the array structure of the storage array can be determined only based on the FPGA platform, reducing the cost of reverse design and simplifying the reverse design process.

[0110] In some embodiments of the present application, the storage array to be tested is included in the SDRAM. The array structure of the SDRAM can be determined by the above method.

[0111] In some embodiments of the present application, before Figure 2 S101 shown, there is also included Figure 10 S105 shown, and will be described in conjunction with each step.

[0112] S105. Perform conventional read and write tests on the storage array to be tested to verify that the working state of the storage array to be tested is normal.

[0113] In the embodiments of the present application, before performing a structural test on the storage array to be tested, conventional read and write tests such as write, read back, and check can be performed on the storage array to be tested to verify that the working state of the storage array to be tested is normal.

[0114] It can be understood that before the test, conventional read and write tests are performed on the storage array to be tested to verify that the working state of the storage array to be tested is normal, thereby avoiding affecting the accuracy of the structural test results due to the abnormal state of the storage array to be tested.

[0115] Figure 11 is an optional process schematic diagram of the storage array structure test method provided by the embodiments of the present application, and will be described in conjunction with Figure 11 the steps shown.

[0116] S401. Confirm that the test platform is working properly.

[0117] In the embodiments of the present application, before performing a chip structure test, the designer can first confirm whether the FPGA test platform is working properly. For example, perform a Row Hammer test on an SDRAM with a known array structure to verify whether the test results are consistent with the known array structure.

[0118] S402. Install the SDRAM to be tested.

[0119] In the embodiments of the present application, after confirming that the test platform is working properly, the designer can install the SDRAM to be tested into the test device.

[0120] S403. Perform conventional operations on the SDRAM to be tested to verify that the working state of the SDRAM to be tested is normal.

[0121] In the embodiments of the present application, the designer can first perform conventional operations on the SDRAM to be tested, such as write, read back, and check, etc., to verify whether the working state of the SDRAM to be tested is normal.

[0122] S404. Based on a preset test mode, write storage data to the SDRAM to be tested and perform a Row Hammer test.

[0123] In the embodiments of the present application, after the designer verifies that the SDRAM under test is in a normal working state, the test device can be used to write stored data to the SDRAM under test and perform a Row Hammer test; that is, according to a preset test pattern (testpattern), attack row stored data and victim row stored data are respectively written to the attacked memory cell row and the victim memory cell row, and a Row Hammer test is performed, and the attacked memory cell row is rapidly and repeatedly alternately activated and precharged.

[0124] S405. Analyze the test results to determine the target preset test pattern.

[0125] In the embodiments of the present application, after the Row Hammer test is completed, the designer can analyze the Row Hammer test results through the test device, and according to the number of Row Hammer attacks that have been performed when the first bit error occurs, find the preset test pattern corresponding to the least number of times of the worst case; and determine this preset test pattern as the target preset test pattern.

[0126] S406. Perform the above tests on other SDRAMs under test of the same batch.

[0127] In the embodiments of the present application, after the designer completes the structural test of a certain SDRAM under test, the test device can be used to perform the above structural tests on other SDRAMs under test of the same batch, and these SDRAMs under test have the same array structure.

[0128] S407. Determine the array structure of these SDRAMs under test based on the target preset test patterns of all SDRAMs under test of the same batch.

[0129] In the embodiments of the present application, the designer can determine the target preset test patterns of all SDRAMs under test of the same batch through the test device, and determine the array structure of these SDRAMs under test. By performing analysis tests on the storage arrays under test of the same batch, the obtained analysis results are more reliable than only performing analysis tests on a single storage array under test.

[0130] It can be understood that the SDRAM test platform based on FPGA does not need to occupy the fixed space of the SDRAM under test and can test the entire internal space of the SDRAM. Compared with the ATE test machine, it has the advantages of low price and high popularity; compared with traditional reverse engineering, it has the advantages of fast operation and easy to master.

[0131] Figure 12 This is an optional structural schematic diagram of the storage array structure test device provided by the embodiments of the present application. As Figure 12As shown in the figure, the embodiment of the present application further provides a test device 800 for a storage array structure, including: a writing unit 804, a row attack test unit 805, and a determination unit 806, where:

[0132] The writing unit 804 is configured to write storage data into the storage array to be tested corresponding to each preset test mode; each preset test mode belongs to one of the preset test mode libraries;

[0133] The row attack test unit 805 is configured to repeatedly perform a row attack test on the storage array to be tested. If a bit flip error occurs in the storage data, the row attack test is stopped, and the number of row attack tests corresponding to each preset test mode of the storage array to be tested is obtained; the bit flip error indicates that the storage data has changed;

[0134] The determination unit 806 is configured to determine the target preset test mode corresponding to the storage array to be tested in the preset test mode library based on the number of row attack tests; and, determine the array structure of the storage array to be tested based on the target preset test mode.

[0135] In some embodiments of the present application, the storage array to be tested includes: an attack storage unit row and a victim storage unit row; the attack storage unit row and the victim storage unit row are adjacent in the array structure of the storage array to be tested; the storage data includes: attack row storage data and victim row storage data; the attack row storage data is represented as alternately changing binary codes; the victim row storage data is represented as continuously identical binary codes; the preset test mode library includes: a first preset test mode and a second preset test mode; the array structure includes: a first array structure and a second array structure.

[0136] In some embodiments of the present application, the writing unit 804 is further configured to write the attack row storage data into the attack storage unit row and write the victim row storage data into the victim storage unit row corresponding to each preset test mode.

[0137] In some embodiments of the present application, the determination unit 806 is further configured to, if the target preset test mode is the first preset test mode, determine the first array structure of the storage array to be tested based on the first preset test mode.

[0138] In some embodiments of the present application, the first array structure is characterized in that N consecutive transmission bits of the m-th signal are concentratedly placed; where m is greater than or equal to 0 and less than or equal to M - 1; M and N are multiples of 8.

[0139] In some embodiments of the present application, the determination unit 806 is further configured to, if the target preset test mode is the second preset test mode, determine the second array structure of the storage array to be tested based on the second preset test mode.

[0140] In some embodiments of the present application, the second array structure is characterized in that the n-th consecutive transmission bits of M signals are centrally placed; where n is greater than or equal to 0 and less than or equal to N - 1; M and N are multiples of 8.

[0141] In some embodiments of the present application, the data stored in the attacked row includes: first attacked row sub-stored data and second attacked row sub-stored data; the values of the corresponding data bits of the first attacked row sub-stored data and the second attacked row sub-stored data are opposite; the data stored in the victim row includes: first victim row sub-stored data and second victim row sub-stored data; the values of the corresponding data bits of the first victim row sub-stored data and the second victim row sub-stored data are opposite.

[0142] In some embodiments of the present application, the writing unit 804 is further configured to, corresponding to a first preset test mode, alternately write the first attacked row sub-stored data and the second attacked row sub-stored data to the attacked memory cell rows in sequence; and continuously write the first victim row sub-stored data to the victim memory cell rows; or, corresponding to the first preset test mode, alternately write the first attacked row sub-stored data and the second attacked row sub-stored data to the attacked memory cell rows in sequence; and continuously write the second victim row sub-stored data to the victim memory cell rows; or, corresponding to the first preset test mode, alternately write the second attacked row sub-stored data and the first attacked row sub-stored data to the attacked memory cell rows in sequence; and continuously write the first victim row sub-stored data to the victim memory cell rows; or, corresponding to the first preset test mode, alternately write the second attacked row sub-stored data and the first attacked row sub-stored data to the attacked memory cell rows in sequence; and continuously write the second victim row sub-stored data to the victim memory cell rows.

[0143] In some embodiments of the present application, the writing unit 804 is further configured to, corresponding to a second preset test mode, continuously write the first attacked row sub-stored data to the attacked memory cell rows; and continuously write the first victim row sub-stored data to the victim memory cell rows; or, corresponding to the second preset test mode, continuously write the first attacked row sub-stored data to the attacked memory cell rows; and continuously write the second victim row sub-stored data to the victim memory cell rows; or, corresponding to the second preset test mode, continuously write the second attacked row sub-stored data to the attacked memory cell rows; and continuously write the first victim row sub-stored data to the victim memory cell rows; or, corresponding to the second preset test mode, continuously write the second attacked row sub-stored data to the attacked memory cell rows; and continuously write the second victim row sub-stored data to the victim memory cell rows.

[0144] In some embodiments of the present application, the row attack test unit 805 is further configured to repeatedly perform fast access to the attacked memory cell rows.

[0145] In some embodiments of the present application, the row attack test unit 805 is further configured to quickly activate and precharge the attacked memory cell row, thereby completing a quick access to the attacked memory cell row; and repeat this process to complete repeated quick access to the attacked memory cell row.

[0146] In some embodiments of the present application, the determining unit 806 is further configured to determine the minimum target test times among the row attack test times; and determine the target preset test mode corresponding to the target test times in the preset test mode library.

[0147] In some embodiments of the present application, the storage array to be tested is included in the SDRAM.

[0148] In some embodiments of the present application, the storage array structure testing device 800 further includes: a conventional test unit 807, where:

[0149] The conventional test unit 807 is configured to perform conventional read and write tests on the storage array to be tested to verify that the working state of the storage array to be tested is normal.

[0150] It should be noted that Figure 13 is an optional structural schematic diagram of the storage array structure testing device provided by the embodiments of the present application. As Figure 13 shown, the hardware entities of the storage array structure testing device 800 include: a processor 801, a communication interface 802, and a memory 803, where:

[0151] The processor 801 generally controls the overall operation of the storage array structure testing device 800.

[0152] The communication interface 802 can enable the storage array structure testing device 800 to communicate with other devices or equipment through a network.

[0153] The memory 803 is configured to store instructions and applications executable by the processor 801, and can also cache data to be processed or already processed by the processor 801 and each module in the storage array structure testing device 800 (for example, image data, audio data, voice communication data, and video communication data), and can be implemented by flash memory (FLASH) or random access memory (Random Access Memory, RAM).

[0154] It should be noted that in the embodiments of the present application, if the method for executing the above-mentioned timing task is implemented in the form of a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium. Based on such an understanding, the technical solution of the embodiments of the present application, in essence or the part that contributes to the related technology, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to enable the storage array structure testing device 800 (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the methods described in the various embodiments of the present application. The aforementioned storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memory (ROM), magnetic disks, or optical discs that can store program codes. In this way, the embodiments of the present application are not limited to any specific combination of hardware and software.

[0155] Correspondingly, the embodiments of the present application provide a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, it implements the steps in the method corresponding to the above-mentioned storage array structure testing device.

[0156] It should be pointed out here that: the descriptions of the above storage medium and device embodiments are similar to the descriptions of the above method embodiments and have similar beneficial effects to the method embodiments. For the technical details not disclosed in the storage medium and device embodiments of the present application, please refer to the descriptions of the method embodiments of the present application for understanding.

[0157] It should be noted that in this article, the term "including", "comprising" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or further includes elements inherent to such a process, method, article or device. Without further limitations, an element defined by the statement "including a..." does not exclude the existence of additional identical elements in the process, method, article or device including that element.

[0158] In several embodiments provided by the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. The device embodiments described above are only illustrative. For example, the division of the units is only a logical function division, and there can be other division methods in actual implementation. For example, multiple units or components can be combined, or can be integrated into another system, or some features can be ignored, or not executed. In addition, the coupling, direct coupling, or communication connection between the components shown or discussed with each other can be through some interfaces. The indirect coupling or communication connection of devices or units can be electrical, mechanical, or other forms.

[0159] The units described above as separate components may or may not be physically separated, and the components shown as units may or may not be physical units; they may be located in one place or distributed over multiple network units; some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0160] In addition, each functional unit in the embodiments of the present application may be all integrated in one processing unit, or each unit may be separately regarded as one unit, or two or more units may be integrated in one unit; the above-mentioned integrated unit may be implemented in the form of hardware, or in the form of a combination of hardware and software functional units.

[0161] As mentioned above, the above are only the implementation manners of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or substitutions, which should all be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A method for testing a storage array structure, characterized in that Including: For each preset test mode, write storage data into the storage array to be tested; Each of the preset test modes belongs to one of a preset test mode library; Repeatedly perform a row attack test on the storage array to be tested. If a bit flip error occurs in the storage data, stop the row attack test and obtain the corresponding row attack test times of the storage array to be tested under each preset test mode; The bit flip error indicates that the storage data has changed; Based on the row attack test times, determine the target preset test mode corresponding to the storage array to be tested in the preset test mode library; Based on the target preset test mode, determine the array structure of the storage array to be tested.

2. The test method for the storage array structure according to claim 1, wherein The storage array to be tested includes: an attack storage unit row and a victim storage unit row; the attack storage unit row and the victim storage unit row are adjacent in the array structure of the storage array to be tested; The storage data includes: attack row storage data and victim row storage data; the attack row storage data is represented as alternating binary codes; the victim row storage data is represented as consecutive identical binary codes; The preset test mode library includes: a first preset test mode and a second preset test mode; the array structure includes: a first array structure and a second array structure.

3. The test method for the storage array structure according to claim 2, characterized in that The step of writing storage data into the storage array to be tested corresponding to each preset test mode includes: Corresponding to each of the preset test modes, write the attack row storage data into the attack storage unit row and write the victim row storage data into the victim storage unit row.

4. The test method for the storage array structure according to claim 3, wherein The step of determining the array structure of the storage array to be tested based on the target preset test mode includes: If the target preset test mode is the first preset test mode, determine the first array structure of the storage array to be tested based on the first preset test mode.

5. The test method for a storage array structure according to claim 4, wherein The first array structure is characterized by concentrating N consecutive transmission bits of the m-th signal; where m is greater than or equal to 0 and less than or equal to M - 1; M and N are multiples of 8.

6. The test method for a storage array structure according to claim 3, characterized in that, The step of determining the array structure of the storage array to be tested based on the target preset test mode includes: If the target preset test mode is the second preset test mode, determine the second array structure of the storage array to be tested based on the second preset test mode.

7. The test method for the storage array structure according to claim 6, wherein The second array structure is characterized by concentrating the n-th consecutive transmission bits of M signals; where n is greater than or equal to 0 and less than or equal to N - 1; M and N are multiples of 8.

8. The method for testing a storage array structure according to claim 4 or 6, wherein The attack row storage data includes: a first attack row sub-storage data and a second attack row sub-storage data; the values of the corresponding data bits of the first attack row sub-storage data and the second attack row sub-storage data are opposite; The victim row storage data includes: a first victim row sub-storage data and a second victim row sub-storage data; the values of the corresponding data bits of the first victim row sub-storage data and the second victim row sub-storage data are opposite.

9. The test method for a storage array structure according to claim 8, wherein For each of the preset test modes, writing attack row storage data to the attack storage unit rows and writing victim row storage data to the victim storage unit rows includes: Corresponding to the first preset test mode, alternately writing the first attack row sub-storage data and the second attack row sub-storage data to the attack storage unit rows in sequence; and continuously writing the first victim row sub-storage data to the victim storage unit rows; or, Corresponding to the first preset test mode, alternately writing the first attack row sub-storage data and the second attack row sub-storage data to the attack storage unit rows in sequence; and continuously writing the second victim row sub-storage data to the victim storage unit rows; or, Corresponding to the first preset test mode, alternately writing the second attack row sub-storage data and the first attack row sub-storage data to the attack storage unit rows in sequence; and continuously writing the first victim row sub-storage data to the victim storage unit rows; or, Corresponding to the first preset test mode, alternately writing the second attack row sub-storage data and the first attack row sub-storage data to the attack storage unit rows in sequence; and continuously writing the second victim row sub-storage data to the victim storage unit rows.

10. The test method for the storage array structure according to claim 8, wherein For each of the preset test modes, writing attack row storage data to the attack storage unit rows and writing victim row storage data to the victim storage unit rows further includes: Corresponding to the second preset test mode, continuously writing the first attack row sub-storage data to the attack storage unit rows; and continuously writing the first victim row sub-storage data to the victim storage unit rows; or, Corresponding to the second preset test mode, continuously writing the first attack row sub-storage data to the attack storage unit rows; and continuously writing the second victim row sub-storage data to the victim storage unit rows; or, Corresponding to the second preset test mode, continuously writing the second attack row sub-storage data to the attack storage unit rows; and continuously writing the first victim row sub-storage data to the victim storage unit rows; or, Corresponding to the second preset test mode, continuously writing the second attack row sub-storage data to the attack storage unit rows; and continuously writing the second victim row sub-storage data to the victim storage unit rows.

11. The test method for the storage array structure according to claim 2, characterized in that, The row attack test includes: fast access; repeating the row attack test on the storage array to be tested includes: Repeating fast access to the attack storage unit rows.

12. The method for testing a storage array structure according to claim 11, wherein Repeating fast access to the attack storage unit rows includes: Quickly activating and precharging the attack storage unit rows, thereby completing one fast access to the attack storage unit rows; Repeating this process, thereby completing repeating fast access to the attack storage unit rows.

13. The test method for a storage array structure according to claim 1, characterized in that Determining the target preset test mode of the storage array to be tested in the preset test mode library based on the number of row attack tests includes: Determining the minimum target test number among the number of row attack tests; In the preset test mode library, determine the target preset test mode corresponding to the target number of test times.

14. The test method for the storage array structure according to claim 1, wherein The storage array to be tested is included in the SDRAM.

15. The test method for the storage array structure according to claim 1, wherein For each corresponding preset test mode, before writing storage data into the storage array to be tested, the method further includes: Performing a conventional read / write test on the storage array to be tested to verify that the working state of the storage array to be tested is normal.

16. A test device for a storage array structure, characterized in that Including: A writing unit, configured to write storage data into the storage array to be tested for each preset test mode; Each of the preset test modes belongs to one of the preset test mode libraries; A row attack test unit, configured to repeatedly perform a row attack test on the storage array to be tested, and if a bit flip error occurs in the storage data, stop the row attack test to obtain the corresponding row attack test times of the storage array to be tested under each preset test mode; The bit flip error indicates that the storage data has changed; A determining unit, configured to determine the target preset test mode corresponding to the storage array to be tested in the preset test mode library based on the row attack test times; And based on the target preset test mode, determine the array structure of the storage array to be tested.

17. The test device for a storage array structure according to claim 16, wherein The device further includes: A conventional test unit, configured to perform a conventional read / write test on the storage array to be tested to verify that the working state of the storage array to be tested is normal.

18. A test device for a storage array structure, characterized in that, Including: A memory, configured to store executable instructions; A processor, configured to implement the method according to any one of claims 1 to 15 when executing the executable instructions stored in the memory.

19. A storage medium, characterized in that, Stored with executable instructions, configured to cause a processor to implement the method according to any one of claims 1 to 15 when executed.

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