Photolithography process method

Abstract

The application relates to a photoetching process method, which comprises the following steps: providing a semiconductor substrate; a first surface of the semiconductor substrate is provided with an alignment mark pattern located in an alignment mark area and an epitaxial layer located in a device area; covering a photoresist layer on the device area and exposing the alignment mark pattern located in the alignment mark area; and patterning the epitaxial layer based on the alignment mark pattern with the photoresist layer. The photoetching process method can expose the alignment mark pattern and use the alignment mark pattern for alignment by covering the photoresist layer on the device area and exposing the alignment mark pattern located in the alignment mark area, so as to improve the patterning precision of the epitaxial layer located in the device area, that is, to improve the overlay precision of a preset target pattern, and to ensure the good performance of the device. In this way, even if the thickness of the epitaxial layer exceeds 5 microns, the preset target pattern will not have overlay deviation because the alignment mark pattern has been exposed before the epitaxial layer is patterned.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuit processing and micro-electro-mechanical system (MEMS) manufacturing process, and particularly relates to a photolithography process method. BACKGROUND

[0002] In the process of integrated circuit processing and micro-electro-mechanical system (MEMS) manufacturing process, in order to make the device have good voltage resistance, isolation and other performances, it is usually necessary to introduce a silicon epitaxy process when processing the device, and the silicon epitaxy process can form multiple layers of single crystal with different thicknesses, doping types and concentrations according to different device requirements, so as to improve the flexibility of device design and the performance of the device.

[0003] In the photolithography process after the silicon epitaxy process, high alignment accuracy is required to align and monitor the overlay of the front layer pattern. However, when the thickness of the silicon epitaxy is more than 5um, the alignment mark pattern will have obvious problems such as pattern shift and pattern distortion, which will cause the preset target pattern to have overlay deviation and affect the performance of the device. SUMMARY

[0004] Therefore, it is necessary to provide a photolithography process method capable of protecting the alignment mark pattern, so that when the thickness of the silicon epitaxy layer is more than 5um, the alignment mark pattern will not have problems such as pattern shift and pattern distortion, so as to ensure that the preset target pattern does not have overlay deviation, and to ensure the good performance of the device.

[0005] According to one aspect of the present application, a photolithography process method is provided, comprising:

[0006] providing a semiconductor substrate; the first surface of the semiconductor substrate is provided with an alignment mark pattern located in an alignment mark area, and an epitaxial layer located in a device area;

[0007] covering a photoresist layer on the device area, and exposing the alignment mark pattern located in the alignment mark area;

[0008] based on the alignment mark pattern, patterning the epitaxial layer by means of the photoresist layer.

[0009] The above photolithography process method exposes the alignment mark pattern by covering a photoresist layer on the device area and exposing the alignment mark pattern located in the alignment mark area, so that the alignment mark pattern can be exposed and used for alignment, thereby improving the patterning accuracy of the epitaxial layer located in the device area, that is, improving the overlay accuracy of the preset target pattern, to ensure the good performance of the device. In this way, even if the thickness of the epitaxial layer is more than 5um, the preset target pattern will not have overlay deviation because the alignment mark pattern has been exposed before patterning the epitaxial layer.

[0010] In one of the embodiments, the covering the photoresist layer on the device region and exposing the alignment mark pattern on the alignment mark region comprises:

[0011] covering a photoresist layer on the first surface of the semiconductor substrate;

[0012] removing the photoresist layer on the alignment mark region by an exposure and development process to expose the alignment mark pattern.

[0013] In one of the embodiments, the providing a semiconductor substrate further comprises:

[0014] forming the alignment mark pattern on the first surface of the semiconductor substrate by an etching process; the alignment mark pattern is located on the alignment mark region.

[0015] In one of the embodiments, the forming the alignment mark pattern on the first surface of the semiconductor substrate by an etching process further comprises:

[0016] forming a silicon dioxide layer on the alignment mark pattern.

[0017] In one of the embodiments, the forming a silicon dioxide layer on the alignment mark pattern comprises:

[0018] forming a silicon dioxide layer on the first surface of the semiconductor substrate by a thermal growth process;

[0019] removing the silicon dioxide layer on the device region by an etching process.

[0020] In one of the embodiments, the providing a semiconductor substrate further comprises:

[0021] forming the epitaxial layer on the first surface of the semiconductor substrate by a thermal growth process; the epitaxial layer is located on the device region.

[0022] In one of the embodiments, the forming the epitaxial layer on the first surface of the semiconductor substrate by a thermal growth process further comprises:

[0023] forming a buried layer with a preset doping type on the first surface of the semiconductor substrate by a buried layer process; the buried layer is located on the device region.

[0024] In one of the embodiments, the preset doping type is N-type or P-type.

[0025] In one of the embodiments, the epitaxial layer is a silicon epitaxial layer.

[0026] In one of the embodiments, the alignment mark pattern is at least two, and at least two of the alignment mark patterns are arranged at intervals. BRIEF DESCRIPTION OF DRAWINGS

[0027] Figure 1 A cross section of a semiconductor substrate after removing a film layer on an alignment mark pattern in the related art;

[0028] Figure 2 A flow chart of a photolithography process in an embodiment of the present application.

[0029] DETAILED DESCRIPTION

[0030] 11, semiconductor substrate; 12, alignment mark pattern; 13, alignment mark area; 14, epitaxial layer. DETAILED DESCRIPTION

[0031] In order to make the above objectives, features and advantages of the present application more apparent, specific embodiments of the present application will be described in detail below with reference to the accompanying drawings. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. It will be apparent, however, to one skilled in the art, that the present application can be practiced without some or all of these details under other conditions and / or can include other structures, as not to limit the scope of the present application. In other instances, well known structures and functions are not described in detail in order to avoid obscuring the concept of the present application.

[0032] In the description of the present application, it is to be understood that the orientations or positional relationships indicated by the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise", "axial", "radial", "circumferential", and the like are based on the orientations or positional relationships shown in the drawings, and are merely intended to facilitate the description of the present application and simplify the description, and therefore cannot be understood as indicating or implying that the devices or elements indicated by the terms must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application.

[0033] In addition, the terms "first", "second", and the like are used only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated by the terms. Therefore, the features defined with "first", "second" can explicitly or implicitly include at least one of the features. In the description of the present application, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise specifically limited.

[0034] In the present application, unless specifically defined otherwise, the terms "mounting", "connected", "connecting", "fixed", and "fixing" should be construed as broad terms, for example, can be fixed connection, can also be detachable connection, or integral; can be mechanical connection, can also be electrical connection; can be direct connection, can also be indirect connection through an intermediate medium, can be internal communication of two elements or interaction relationship between two elements, unless specifically defined otherwise. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0035] In the present application, unless specifically defined otherwise, the first feature is "on" or "under" the second feature can be that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, the first feature "above", "over" and "on" the second feature can be that the first feature is directly above or obliquely above the second feature, or only indicates that the horizontal height of the first feature is higher than that of the second feature. The first feature "below", "under" and "under" the second feature can be that the first feature is directly below or obliquely below the second feature, or only indicates that the horizontal height of the first feature is less than that of the second feature.

[0036] It should be noted that when an element is referred to as "fixed to" or "disposed on" another element, it can be directly on the other element or there can be a mediating element. When an element is referred to as "connected to" another element, it can be directly connected to the other element or there can be a mediating element. The terms "vertical", "horizontal", "up", "down", "left", "right" and similar expressions used herein are for illustrative purposes only and are not the only implementation.

[0037] Figure 1 The cross section of the semiconductor substrate after removing the film layer on the alignment mark pattern in the related art is shown.

[0038] In the process of integrated circuit processing and micro-electro-mechanical system (MEMS) manufacturing, a silicon epitaxial process is usually introduced to provide device voltage resistance, isolation and other functions. The process can grow multiple single crystals with different thicknesses and doping types and concentrations according to different device requirements, thereby improving the flexibility of device design and the performance of the device. In the process of power device technology and MEMS product technology, the silicon epitaxial process is usually completed after the buried layer process. In the photolithography process after the silicon epitaxial process, high alignment accuracy is required to align and monitor the overlay of the front layer pattern. Since the thickness of the silicon epitaxial layer is designed according to the performance required by the device, when the thickness of the silicon epitaxial layer exceeds 5 microns, the alignment mark pattern 12 will have obvious problems such as pattern shift and pattern distortion. Therefore, the film layer on the alignment mark area 13 is usually removed to ensure that the alignment mark pattern is clear and available, but this will cause a large height difference between the silicon epitaxial layer and the alignment mark pattern 12 (see the height difference D indicated by the arrow in FIG. 1), which will cause the surface of the alignment mark pattern 12 to be unevenly coated with photoresist when coating photoresist in the subsequent step, and there will be errors in signal recognition in the photolithography process, thereby causing the target pattern on the silicon epitaxial layer to have overall overlay deviation. Figure 1

[0039] Therefore, in order to solve at least one of the above problems, the present application provides a photolithography process method. Since the height difference between the epitaxial layer 14 and the alignment mark pattern 12 is not more than 5 microns, the alignment mark pattern 12 basically does not have problems such as pattern shift and pattern distortion. Therefore, in the following embodiments of the present application, the height difference between the epitaxial layer 14 and the alignment mark pattern 12 is greater than 5 microns.

[0040] Figure 2 The flowchart of the photolithography process method in an embodiment of the present application is shown in FIG. 2.

[0041] Referring to FIG. 1, Figure 2 the present application provides a photolithography process method, which comprises the following steps:

[0042] S110: providing a semiconductor substrate 11; the first surface of the semiconductor substrate 11 is provided with an alignment mark pattern 12 located in an alignment mark area 13 and an epitaxial layer 14 located in a device area;

[0043] S120: covering a photoresist layer on the device area and exposing the alignment mark pattern 12 located in the alignment mark area 13;

[0044] S130: patterning the epitaxial layer 14 based on the alignment mark pattern 12 by means of the photoresist layer.

[0045] Optionally, the epitaxial layer 14 is a silicon epitaxial layer.

[0046] ​Since the technical problem solved by the photolithography process method of the present application is that the height difference between the epitaxial layer 14 and the alignment mark pattern 12 causes the preset target pattern to be out of overlay deviation, the photoresist layer in step S120 of the present application is also coated on the surface shown in the figure, that is, the photoresist layer on the alignment mark pattern 12 cannot be uniformly coated due to the height difference. Figure 1 The photoresist layer on the alignment mark pattern 12 cannot be uniformly coated due to the height difference.

[0047] The above-mentioned photolithography process method coats a photoresist layer on the device area and exposes the alignment mark pattern 12 in the alignment mark area 13, so that the alignment mark pattern 12 can be exposed and used for alignment, thereby improving the patterning accuracy of the epitaxial layer 14 in the device area, that is, improving the overlay accuracy of the preset target pattern to ensure good performance of the device. In this way, when the thickness of the epitaxial layer 14 exceeds 5 microns, since the alignment mark pattern 12 has been exposed before the epitaxial layer 14 is patterned, it can be clearly used for alignment, and the preset target pattern will not have overlay deviation.

[0048] Step S120 coats a photoresist layer on the device area and exposes the alignment mark pattern 12 in the alignment mark area 13, specifically comprising:

[0049] Coating a photoresist layer on the first surface of the semiconductor substrate 11;

[0050] Removing the photoresist layer on the alignment mark area 13 by exposure and development process to expose the alignment mark pattern 12.

[0051] Wherein, the semiconductor substrate 11 is a silicon substrate; the photoresist is a positive photoresist; the first surface is one side surface of the semiconductor substrate 11 along the thickness direction of itself, and the first surface is used as the surface for forming the preset target pattern, which refers to the specified pattern that is preset, that is, the pattern that the device finally needs to obtain. It can be understood that the semiconductor substrate 11 can also be of other types, and the photoresist can also be a negative photoresist, which can be selected according to actual needs.

[0052] It can be understood that a coating machine or the like can be selected to coat a photoresist layer on the first surface of the semiconductor substrate 11, and the photoresist layer will cover the entire first surface of the semiconductor substrate 11, but due to the height difference between the epitaxial layer 14 and the alignment mark pattern 12, the photoresist on the alignment mark pattern 12 is not uniform, which affects the subsequent alignment of the alignment mark pattern 12, which is one of the technical problems solved by the photolithography process method to be protected by the present application.

[0053] Therefore, by covering the first surface of the semiconductor substrate 11 with a photoresist layer and then removing the photoresist layer on the alignment mark area 13 by a linear exposure process to expose the alignment mark pattern 12, the alignment mark pattern 12 is clearly available, and the semiconductor substrate 11 can be aligned by the exposed alignment mark pattern 12, thereby improving the overlay accuracy of the preset target pattern.

[0054] Before the step S110 of providing the semiconductor substrate 11, the photolithography process further includes:

[0055] forming the alignment mark pattern 12 on the first surface of the semiconductor substrate 11 by an etching process; the alignment mark pattern 12 is located in the alignment mark area 13.

[0056] The specific shape of the alignment mark pattern 12 can be rectangular, square, triangular, pentagonal, etc., which can be selected as needed and is not limited herein. In addition, in order to facilitate the alignment of the alignment mark pattern 12, the alignment mark pattern 12 is generally recessed (i.e., grooved), and the groove depth of the alignment mark pattern 12 ranges from 500A to 2000A, and the width ranges from 1 micrometer to 8 micrometers. Since the groove depth of the alignment mark pattern 12 is very small, it will not cause uneven photoresist coating, and will not cause the alignment mark pattern 12 to have problems such as pattern shift and pattern distortion.

[0057] Optionally, the etching process for forming the alignment mark pattern 12 is dry etching or wet etching.

[0058] In some embodiments, the alignment mark pattern 12 is at least two, and the at least two alignment mark patterns 12 are arranged at intervals. Optionally, the at least two alignment mark patterns 12 are symmetrically and arranged at intervals, and are located in the alignment mark area 13.

[0059] It can be understood that the number of alignment mark patterns 12 can also be three, four, five, etc., and the plurality of alignment mark patterns 12 can be symmetrically and arranged at intervals on the first surface of the semiconductor substrate 11, or can be arranged at intervals on the corresponding semiconductor substrate 11 as needed. The number of alignment mark patterns 12 can be selected as needed.

[0060] Therefore, by forming at least two alignment mark patterns 12 on the first surface of the semiconductor substrate 11, the alignment mark patterns 12 are used for alignment to determine the position of the semiconductor substrate 11, thereby facilitating the improvement of the overlay accuracy of the preset target pattern, avoiding the occurrence of overlay deviation, and facilitating the improvement of the performance of the device.

[0061] In some embodiments, after the alignment mark pattern 12 is formed on the first surface of the semiconductor substrate 11 by the etching process, the photolithography process further includes:

[0062] A silicon dioxide layer is formed on the alignment mark pattern 12.

[0063] In this way, by forming the silicon dioxide layer on the alignment mark pattern 12, since the silicon dioxide layer can inhibit the formation of silicon, the formation of the silicon epitaxial layer on the alignment mark pattern 12 can be avoided.

[0064] In some embodiments, forming the silicon dioxide layer on the alignment mark pattern 12 comprises:

[0065] forming the silicon dioxide layer on the first surface of the semiconductor substrate 11 by a thermal growth process;

[0066] removing the silicon dioxide layer on the device region by an etching process.

[0067] In some embodiments, the thermal growth process is chemical vapor deposition (CVD), and the thickness of the silicon dioxide layer formed by the thermal growth process ranges from 100A to 2 microns.

[0068] It can be understood that the silicon dioxide layer can be formed by other processes besides the thermal growth process, as long as the use requirements can be met.

[0069] In this way, by forming the silicon dioxide layer on the first surface of the semiconductor substrate 11 by the thermal growth process, and then removing the silicon dioxide layer on the device region by the etching process, that is, the silicon dioxide layer on the alignment mark pattern 12 in the alignment mark region 13 is retained, the silicon dioxide layer can protect the alignment mark pattern 12, that is, when the epitaxial layer 14 is a silicon epitaxial layer, the silicon dioxide layer can inhibit the formation of the silicon epitaxial layer on the alignment mark pattern 12, and the thickness of the silicon dioxide layer on the alignment mark pattern 12 can be greatly reduced.

[0070] Before providing the semiconductor substrate 11, the photolithography process further comprises:

[0071] forming the epitaxial layer 14 on the first surface of the semiconductor substrate 11 by a thermal growth process; the epitaxial layer 14 is located in the device region.

[0072] In some embodiments, the thermal growth process is chemical vapor deposition (CVD), and the epitaxial layer 14 is a silicon epitaxial layer.

[0073] It can be understood that the epitaxial layer 14 can be formed by other processes besides the thermal growth process, as long as the use requirements can be met.

[0074] It should be noted that the temperature range for forming the silicon epitaxial layer by chemical vapor deposition is 600-1150°C, the thickness range of the silicon epitaxial layer is 5-30 microns, disilane (Si2H6) is the raw material for forming the silicon epitaxial layer, and according to the thickness of the grown silicon epitaxial layer, 0.25%-1.0% of chlorine gas (Cl2) relative to disilane (i.e., the flow rate of chlorine gas relative to disilane is 0.25%-1.0%) can be added to the reaction precursor, thereby inhibiting the growth of silicon crystal nuclei on the surface of the silicon dioxide layer. Among them, chlorine gas inhibits the growth of silicon on the surface of the silicon dioxide layer by inhibiting the nucleation rate of silicon, but chlorine gas does not inhibit the growth of silicon on the silicon substrate. When the process of growing the silicon epitaxial layer is completed, the desired thickness of the silicon epitaxial layer can be obtained on the surface of the silicon substrate, and only a very thin silicon epitaxial layer (thickness range of 200A-1000A) is formed on the silicon dioxide layer, which does not affect the pattern quality of the alignment mark pattern 12 protected by the silicon dioxide layer. The silicon epitaxial layer on the alignment mark pattern 12 can be removed.

[0075] It should be noted that after forming the alignment mark pattern 12 on the first surface of the semiconductor substrate 11 by the etching process, a silicon dioxide layer can also be formed on the alignment mark pattern 12. In this embodiment, after forming the alignment mark pattern 12 on the first surface of the semiconductor substrate 11 by the etching process, the photolithography process method further comprises:

[0076] forming an epitaxial layer 14 on the first surface of the semiconductor substrate 11 by a thermal growth process;

[0077] covering a photoresist layer on the first surface of the semiconductor substrate 11;

[0078] removing the photoresist layer on the alignment mark area 13 by an exposure and development process;

[0079] removing the epitaxial layer 14 on the alignment mark pattern 12 by an etching process;

[0080] removing the photoresist layer on the device area by exposure and development.

[0081] Therefore, the epitaxial layer 14 on the alignment mark pattern 12 is removed by the etching process to avoid the problems of pattern shift and pattern distortion of the alignment mark pattern 12, and ensure that the alignment mark pattern 12 is clear and available. However, after the epitaxial layer 14 on the alignment mark pattern 12 is removed, a height difference (i.e., thickness inconsistency) exists between the alignment mark pattern 12 in the alignment mark area 13 and the silicon epitaxial layer in the device area, which causes the photoresist on the alignment mark pattern 12 to be unevenly coated when the photoresist is coated on the first surface of the semiconductor substrate 11, and further causes the semiconductor substrate 11 to be unable to be aligned, and the preset target pattern to be misaligned. Therefore, after the epitaxial layer 14 in the device area is formed, a photoresist layer is coated on the first surface of the semiconductor substrate 11 in the present application; the photoresist layer on the alignment mark area 13 is removed by the exposure and development process to expose the alignment mark pattern 12.

[0082] In some embodiments, before the epitaxial layer 14 is formed on the first surface of the semiconductor substrate 11 by the thermal growth process, the photoetch process further includes:

[0083] forming a buried layer with a preset doping type on the first surface of the semiconductor substrate 11 by a buried layer process; the buried layer is located in the device area.

[0084] Optionally, the preset doping type is N-type or P-type; and the buried layer process is ion implantation.

[0085] It should be noted that the buried layer process is a process widely used in semiconductor processes such as bipolar semiconductor devices, image sensors, Bi-CMOS devices, etc. Taking a bipolar semiconductor device as an example, the collector of the transistor needs to be led out from the bottom layer of the device upwards, thereby increasing the series resistance of the collector, which is not conducive to the performance of the circuit. In order to provide a low-resistance current path for the collector and reduce the series resistance of the collector, a buried layer is usually formed in the substrate of the device, and then an epitaxial layer is formed, and a collector aligned with the buried layer is formed in the epitaxial layer. It can be seen that in such devices, the buried layer alignment process is crucial to the performance of the circuit. Therefore, in the present application, a buried layer needs to be formed in the device area before the epitaxial layer in the device area is formed. Since there are many specific steps of the buried layer process in the related art, they are not described herein.

[0086] In conclusion, the application provides a photolithography process method, which covers photoresist layer on the device area, exposes alignment mark pattern 12 in the alignment mark area 13, and then patterns epitaxial layer 14 based on the alignment mark pattern 12, so as to obtain the preset target pattern. Since the alignment mark pattern 12 in the alignment mark area 13 is exposed, it is clear and can guarantee the accuracy of alignment, which is conducive to improving the accuracy of patterning epitaxial layer 14 in the device area and improving the overlay accuracy of the preset target pattern, so as to guarantee the good performance of the device. In this way, when the thickness of the epitaxial layer 14 exceeds 5 microns, since the alignment mark pattern 12 has been exposed before patterning the epitaxial layer 14, the preset target pattern will not have overlay deviation, that is, the photolithography process method provided by the application can expose the alignment mark pattern 12 before patterning the epitaxial layer 14, and the alignment accuracy will not be affected by the thickness of the epitaxial layer 14.

[0087] The technical features of the above-described embodiments can be combined in any manner. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described, but it should be considered that any combination of the technical features is within the scope of the present disclosure as long as the combination does not result in contradictions.

[0088] The above-described embodiments only express several embodiments of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the scope of the patent. It should be noted that for ordinary skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are within the scope of the present application. Therefore, the scope of protection of the present application should be subject to the appended claims.

Claims

1. A lithographic process method, characterized by, The method comprises the following steps: providing a semiconductor substrate; a first surface of the semiconductor substrate is provided with an alignment mark pattern located in an alignment mark area and an epitaxial layer located in a device area; covering a photoresist layer on the device area and exposing the alignment mark pattern located in the alignment mark area; based on the alignment mark pattern, patterning the epitaxial layer by means of the photoresist layer; the step of providing a semiconductor substrate specifically comprises: forming an alignment mark pattern on a first surface of a semiconductor substrate; forming the epitaxial layer on the first surface of the semiconductor substrate by a thermal growth process; removing the epitaxial layer on the alignment mark pattern by an etching process so that the epitaxial layer is located in the device area.

2. The photolithography process method of claim 1, wherein, the step of covering a photoresist layer on the device area and exposing the alignment mark pattern located in the alignment mark area comprises: covering a photoresist layer on the first surface of the semiconductor substrate; removing the photoresist layer located on the alignment mark area by an exposure and development process to expose the alignment mark pattern.

3. The photolithography process method of claim 1, wherein, before the step of providing a semiconductor substrate, the method further comprises: forming the alignment mark pattern on the first surface of the semiconductor substrate by an etching process; the alignment mark pattern is located in the alignment mark area.

4. The photolithography process method of claim 3, wherein, after the step of forming the alignment mark pattern on the first surface of the semiconductor substrate by an etching process, the method further comprises: forming a silicon dioxide layer on the alignment mark pattern.

5. The photolithography process method of claim 4, wherein, the step of forming a silicon dioxide layer on the alignment mark pattern comprises: forming a silicon dioxide layer on the first surface of the semiconductor substrate by a thermal growth process; removing the silicon dioxide layer located on the device area by an etching process.

6. The photolithography process method according to any one of claims 1-5, wherein, before the step of forming the epitaxial layer on the first surface of the semiconductor substrate by a thermal growth process, the method further comprises: forming a buried layer with a preset doping type on the first surface of the semiconductor substrate by a buried layer process; the buried layer is located in the device area.

7. The photolithography process method of claim 6, wherein, the preset doping type is N-type or P-type.

8. The photolithography process method according to any one of claims 1-5, wherein, the epitaxial layer is a silicon epitaxial layer.

9. The photolithography process method according to any one of claims 1-5, wherein, the alignment mark pattern is at least two, and the at least two alignment mark patterns are arranged at intervals.

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