Automatic control equalization circuit

Abstract

The present invention relates to the field of data storage and discloses an automatic control equalization circuit, comprising a first amplifier, a second amplifier, a feedback signal generator, a frequency delay signal generator, a feedback activator, an equalization control unit, and a gain control unit. The first amplifier is coupled to the second amplifier, the feedback signal generator is coupled to the second amplifier, the frequency delay signal generator is used to receive a frequency signal, the feedback activator is coupled to the frequency delay signal generator and the feedback signal generator, the equalization control unit is coupled to the feedback signal generator, the feedback activator, and the first amplifier, and the gain control unit is coupled to the feedback signal generator, the second input terminal of the first amplifier, and the output terminal of the first amplifier. The circuit can automatically adjust system gain and add equalization characteristics based on an input data signal, thereby optimizing energy consumption and resisting noise channels.

Description

Technical Field

[0001] The present invention relates to the field of data storage, and in particular to a self-controlled equalization circuit. Background Art

[0002] With the rapid advancement of technology, various volatile and non-volatile memory types have been incorporated into computer systems. Dynamic Random Access Memory (DRAM) is a type of semiconductor memory that falls under the volatile category. Its primary function is to use the amount of charge stored in a capacitor to represent whether a binary bit is 1 or 0. DRAM is a short-term data storage area in a computer system, storing information currently in use for quick access. DRAM offers high-speed transmission and bandwidth utilization.

[0003] However, since DRAM is required to have high-speed transmission and high bandwidth utilization, its power consumption also increases. Moreover, the channels with high-speed transmission and high bandwidth utilization are usually noisy channels, or the data may also have noise during sampling. Summary of the Invention

[0004] Therefore, the present invention provides a self-controlled equalization circuit to optimize the power consumption of DRAM and resist the interference of noise channels.

[0005] The above-mentioned invention objectives are mainly achieved through the following technical solutions:

[0006] The automatic control equalization circuit includes:

[0007] A first amplifier, a second amplifier, a feedback signal generator, a frequency delay signal generator, a feedback starter, an equalization control unit, and a gain control unit;

[0008] The first amplifier includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal, wherein the first input terminal is used to receive a data signal, and the second input terminal is used to receive a reference signal; the second amplifier includes a third input terminal, a fourth input terminal, a third output terminal, and a fourth output terminal; the feedback signal generator includes a fifth input terminal and a fifth output terminal, configured to delay the received signal and output a feedback signal; the frequency delay signal generator includes a sixth input terminal, a sixth output terminal, and a seventh output terminal, wherein the sixth input terminal is used to receive a frequency signal; the feedback activator includes a seventh input terminal, an eighth input terminal, a ninth input terminal, and an eighth output terminal, configured to output a feedback activation signal according to the received feedback signal; the equalization control unit includes a tenth input terminal, an eleventh input terminal, a twelfth input terminal, a thirteenth input terminal, and a ninth output terminal; and the gain control unit includes a fourteenth input terminal, a fifteenth input terminal, a sixteenth input terminal, and a tenth output terminal.

[0009] The first output terminal and the second output terminal are coupled to the third input terminal and the fourth input terminal, respectively; the fourth output terminal is coupled to the fifth input terminal; the fifth output terminal is coupled to the seventh input terminal, the tenth input terminal, and the fourteenth input terminal, respectively; the sixth output terminal and the seventh output terminal are coupled to the eighth input terminal and the ninth input terminal, respectively; the eighth output terminal is coupled to the thirteenth input terminal; the eleventh input terminal and the sixteenth input terminal are coupled to the first output terminal, respectively; the twelfth input terminal and the fifteenth input terminal are coupled to the second output terminal, respectively; and the ninth output terminal and the tenth output terminal are coupled to the second input terminal, respectively.

[0010] Compared with the existing technology, the invention has the following beneficial effects: by introducing a gain control unit and an equalization control unit, the system gain and additional equalization characteristics can be automatically adjusted according to the input data signal. Therefore, it has the function of optimizing energy consumption and resisting noise channels, and is suitable for high-speed computing DRAM. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] Figure 1 1 is a schematic structural diagram of an automatic control equalization circuit according to an embodiment of the present invention;

[0012] Figure 2 is a schematic structural diagram of a first amplifier in an embodiment of the present invention;

[0013] Figure 3 is a schematic structural diagram of a second amplifier in an embodiment of the present invention;

[0014] Figure 4 1 is a schematic structural diagram of a frequency delay signal generator according to an embodiment of the present invention;

[0015] Figure 5 2 is a schematic structural diagram of a feedback starter according to an embodiment of the present invention;

[0016] Figure 6 is a structural diagram of a feedback signal generator according to an embodiment of the present invention;

[0017] Figure 7 2 is a schematic structural diagram of an equalization control unit according to an embodiment of the present invention;

[0018] Figure 8 2 is a schematic structural diagram of a gain control unit in an embodiment of the present invention.

[0019] The description of the accompanying drawings is as follows:

[0020]

[0021] DETAILED DESCRIPTION

[0022] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0023] An embodiment of the present invention provides a self-controlled equalization circuit, which is applied to DRAM, such as Figure 1 As shown, the self-controlled equalization circuit 100 includes a first amplifier 10 , a second amplifier 11 , a feedback signal generator 12 , a frequency delay signal generator 13 , a feedback activator 14 , an equalization control unit 15 and a gain control unit 16 .

[0024] The first amplifier 10 includes a first input terminal, a second input terminal, a first output terminal and a second output terminal; the first input terminal is used to receive a data signal DIP, and the second input terminal is used to receive a reference signal DIN; the first output terminal is used to output a first output signal POUTB, and the second output terminal is used to output a second output signal POUT.

[0025] The second amplifier 11 includes a third input terminal, a fourth input terminal, a third output terminal and a fourth output terminal; the third input terminal and the fourth input terminal are coupled to the first output terminal and the second output terminal of the first amplifier 10, respectively; the third output terminal of the second amplifier 11 is used to output a third output signal PB, and the fourth output terminal of the second amplifier 11 is used to output a fourth output signal PT.

[0026] The feedback signal generator 12 includes a fifth input terminal and a fifth output terminal. The fifth input terminal is coupled to the fourth output terminal of the second amplifier 11 .

[0027] The frequency delay signal generator 13 includes a sixth input terminal, a sixth output terminal, and a seventh output terminal. The sixth input terminal is used to receive the frequency signal CLK.

[0028] The feedback enabler 14 includes a seventh input terminal, an eighth input terminal, a ninth input terminal, and an eighth output terminal. The seventh input terminal is coupled to the fifth output terminal of the feedback signal generator 12. The eighth input terminal and the ninth input terminal are coupled to the sixth output terminal and the seventh output terminal of the frequency delay signal generator 13, respectively.

[0029] The equalization control unit 15 includes a tenth input terminal, an eleventh input terminal, a twelfth input terminal, a thirteenth input terminal, and a ninth output terminal. The tenth input terminal is coupled to the fifth output terminal of the feedback signal generator 12, the eleventh input terminal is coupled to the first output terminal of the first amplifier 10, the twelfth input terminal is coupled to the second output terminal of the first amplifier 10, and the thirteenth input terminal is coupled to the eighth output terminal of the feedback actuator 14.

[0030] The gain control unit 16 includes a fourteenth input terminal, a fifteenth input terminal, a sixteenth input terminal, and a tenth output terminal. The fourteenth input terminal is coupled to the fifth output terminal of the feedback signal generator 12, the fifteenth input terminal is coupled to the second output terminal of the first amplifier 10, the sixteenth input terminal is coupled to the first output terminal of the first amplifier 10, and the tenth output terminal is coupled to the second input terminal of the first amplifier 10.

[0031] In the architecture of the self-controlled equalization circuit 100, a first amplifier 10, a second amplifier 11, a feedback signal generator 12, a feedback activator 14, an equalization control unit 15, and a gain control unit 16 form a circuit loop that automatically controls its gain and adds equalization characteristics. For example, after amplification by the first and second amplifiers 10 and 11, the data signal DIP is input to the feedback signal generator 12. The feedback signal generator 12 delays the signal to generate a feedback signal. After receiving the feedback signal, the feedback activator 14 generates a feedback activation signal. The output of the data signal DIP after passing through the first amplifier 10 can be subjected to additional equalization by the equalization control unit 15 based on the feedback activation signal and the feedback signal to reduce noise channel interference. Furthermore, the output of the data signal DIP after passing through the first amplifier 10 can be adjusted by the gain control unit 16 based on the feedback signal to optimize energy consumption. Therefore, this embodiment of the present invention can automatically adjust the system gain and add equalization characteristics based on the input data signal, optimizing energy consumption and combating noise channels.

[0032] Based on the above embodiment, in a more preferred embodiment, the self-controlled equalization circuit 100 further includes a sampling unit 17. Figure 1The sampling unit 17 includes a seventeenth input terminal, an eighteenth input terminal, an eleventh output terminal and a twelfth output terminal, the seventeenth input terminal is coupled to the third output terminal of the second amplifier 11, the eighteenth input terminal is coupled to the fourth output terminal of the second amplifier 11, the sampling unit 17 also includes a twenty-seventh input terminal, the twenty-seventh input terminal is coupled to the sixth input terminal of the frequency delay signal generator 13, the twenty-seventh input terminal is used to receive the frequency signal CLK, the eleventh output terminal is used to output the output signal E1 of the even index, and the twelfth output terminal is used to output the output signal O1 of the odd index.

[0033] On the basis of the above embodiment, in a more preferred embodiment, as Figure 2 As shown, the first amplifier 10 includes: a first transistor T1, including a first terminal, a second terminal and a first control terminal, the first terminal is used to receive the working voltage V DD The second transistor T2 includes a third terminal, a fourth terminal, and a second control terminal, the third terminal is used to receive the operating voltage, and the second control terminal is coupled to the first control terminal; the third transistor T3 includes a fifth terminal, a sixth terminal, and a third control terminal, the fifth terminal is coupled to the second terminal, and the third control terminal is used to receive the data signal DIP; the fourth transistor T4 includes a seventh terminal, an eighth terminal, and a fourth control terminal, the seventh terminal is coupled to the fourth terminal, the eighth terminal is coupled to the sixth terminal, and the fourth control terminal is used to receive the reference signal DIN; the fifth transistor T5 includes a ninth terminal, a tenth terminal, and a fifth control terminal, the ninth terminal is coupled to the eighth terminal, the tenth terminal is coupled to the ground terminal, and the fifth control terminal is used to receive the bias signal BIAS.

[0034] As explained herein, the bias signal BIAS can be a custom or preset voltage value used to control the conduction state of the fifth transistor T5. For example, when the fifth transistor T5 is an N-type metal-oxide-semiconductor field-effect transistor (N-type metal-oxide-semiconductor field-effect transistor), the voltage of the bias signal BIAS affects the conduction state of the fifth transistor T5. Therefore, the current flowing through the fifth transistor T5 of the first amplifier 10 can also be controlled by the bias signal BIAS. Furthermore, when the third transistor T3 and the fourth transistor T4 are in the linear region, and the first transistor T1 and the second transistor T2 are conductive, the two outputs of the first amplifier 10, namely the first output signal POUTB and the second output signal POUT, are also linearly amplified. It should be understood that the first output signal POUTB is located at the first terminal of the third transistor T3, and the second output signal POUT is located at the first terminal of the fourth transistor T4. Furthermore, the first output signal POUTB and the second output signal POUT are inversely proportional to each other.

[0035] On the basis of the above embodiment, in a more preferred embodiment, as Figure 3 As shown, the second amplifier 11 includes a third input terminal, a fourth input terminal, a third output terminal, and a fourth output terminal. The third input terminal and the fourth input terminal are coupled to the first output terminal and the second output terminal of the first amplifier 10, respectively. The third output terminal of the second amplifier 11 is used to output a third output signal PB, and the fourth output terminal of the second amplifier 11 is used to output a fourth output signal PT. Therefore, after the first output signal POUTB and the second output signal POUT are amplified by the second amplifier 11, they are respectively amplified into the third output signal PB and the fourth output signal PT. Furthermore, the third output signal PB and the fourth output signal PT can be inversely proportional to each other.

[0036] It should be noted that the first amplifier 10 and the second amplifier 11 of the self-controlled equalization circuit 100 are not limited by the circuit of the amplifier. For example, the first amplifier 10 and the second amplifier 11 can be a voltage amplifier, a current amplifier or a differential amplifier. Figure 2 In , the first amplifier 10 may be a differential amplifier. Figure 3 In FIG, the second amplifier 11 is also a differential amplifier, and its inputs are the first output signal POUTB and the second output signal POUT which are inversely proportional to each other.

[0037] On the basis of the above embodiment, in a more preferred embodiment, as Figure 4 As shown, the frequency delay signal generator 13 includes a first inverter unit, including a plurality of first inverters INV1 connected in series, the input end of the first inverter unit is used to receive the frequency signal CLK, and the output end of the first inverter unit outputs the frequency delay signal CLKD; a second inverter INV2, including a nineteenth input end and a thirteenth output end, the nineteenth input end is connected to the output end of the first inverter unit, the nineteenth input end is used to receive the frequency delay signal CLKD, and the thirteenth output end is used to output the inverse frequency delay signal CLKDB.

[0038] It is understood that there is no limit to the number of first inverters connected in series in the frequency delay signal generator 13. However, because the inverted frequency delay signal CLKDB passes through one more inverter than the frequency delay signal CLKD, the phases of the inverted frequency delay signal CLKDB and the frequency delay signal CLKD are opposite. Furthermore, because each inverter has its own time delay, the more inverters in the frequency delay signal generator 13, the greater the time delay.

[0039] On the basis of the above embodiment, in a more preferred embodiment, as Figure 5As shown, the feedback starter 14 includes: a third inverter INV3, including a 20th input terminal and a 14th output terminal, the 20th input terminal coupled to the fifth output terminal of the feedback signal generator 12 for receiving the feedback signal PT_FB1 output by the feedback signal generator 12; a first NOR gate NOR1, including a 21st input terminal, a 22nd input terminal, and a 15th output terminal, the 21st input terminal coupled to the output terminal of the first inverter unit, the 22nd input terminal coupled to the 13th output terminal of the frequency delay signal generator 13, the 21st input terminal for receiving the frequency delay signal CLKD, and the 22nd input terminal for receiving the inverse frequency delay signal CLKDB; a second NOR gate NOR2, including a 23rd input terminal, a 24th input terminal, and a 16th output terminal, the 23rd input terminal coupled to the 14th output terminal of the third inverter INV3, and the 24th input terminal coupled to the 15th output terminal of the first NOR gate NOR1. The fourth inverter INV4 includes a twenty-fifth input terminal and a seventeenth output terminal, wherein the twenty-fifth input terminal is coupled to the sixteenth output terminal of the second NOR gate NOR2. The fifth inverter INV5 includes a twenty-sixth input terminal and an eighteenth output terminal, wherein the twenty-sixth input terminal is coupled to the seventeenth output terminal of the fourth inverter INV4; the eighteenth output terminal is used to output the feedback enable signal PEAK_EN. Figure 5 In the example, the frequency-delayed signal CLKD and the inverse frequency-delayed signal CLKDB of the feedback enabler 14 are two inverse signals with fixed frequencies. Furthermore, the feedback signal PT_FB1 is related to the data signal DIP (passing through the first amplifier 10 and the second amplifier 11). Therefore, the feedback signal PT_FB1 varies with changes in the data signal DIP. The variation of the feedback enable signal PEAK_EN can be derived from the truth table of the inverter and the NOR gate, so it will not be further described here.

[0040] On the basis of the above embodiment, in a more preferred embodiment, as Figure 6 As shown, the feedback signal generator 12 includes: a second inverter unit, including a plurality of sixth inverters INV6 connected in series, the input end of the second inverter unit is coupled to the fourth output end of the second amplifier 11, and the second inverter unit is used to delay the signal output from the fourth output end to output the feedback signal PT_FB1. In other words, the fourth output signal PT output by the second amplifier 11 can be delayed by the feedback signal generator 12 to generate the feedback signal PT_FB1. Figure 6 There is no limit to the number of sixth inverters connected in series in the feedback signal generator 12. Moreover, since each inverter has its own time delay, the more inverters there are in the feedback signal generator 12, the greater the time delay will be.

[0041] On the basis of the above embodiment, in a more preferred embodiment, as Figure 7 As shown, the equalization control unit 15 includes: a sixth transistor T6, including an eleventh terminal, a twelfth terminal, and a sixth control terminal, the eleventh terminal coupled to the first output terminal of the first amplifier 10 for receiving the first output signal POUTB, the sixth control terminal coupled to the fifth output terminal of the feedback signal generator 12, and the sixth control terminal for receiving the feedback signal PT_FB1 output by the feedback signal generator, the feedback signal being a signal output by the feedback signal generator after delaying the signal output from the fourth output terminal; a seventh transistor T7, including a thirteenth terminal, a fourteenth terminal, and a seventh control terminal, the thirteenth terminal coupled to the second output terminal of the first amplifier 10 for receiving the second output signal POUT, the fourteenth terminal coupled to the twelfth terminal of the sixth transistor T6, and the seventh control terminal coupled to the second input terminal of the first amplifier 10 for receiving the reference signal DIN; a resistor The capacitor C includes a fifteenth terminal and a sixteenth terminal, the fifteenth terminal being coupled to the twelfth terminal of the sixth transistor T6, and the sixteenth terminal being coupled to the fourteenth terminal of the seventh transistor T7. The capacitor C includes a seventeenth terminal and an eighteenth terminal, the seventeenth terminal being coupled to the twelfth terminal of the sixth transistor T6, and the eighteenth terminal being coupled to the fourteenth terminal of the seventh transistor T7. The eighth transistor T8 includes a nineteenth terminal, a twentieth terminal, and an eighth control terminal, the nineteenth terminal being coupled to the fourteenth terminal of the seventh transistor T7, and the eighth control terminal being configured to receive the bias signal BIAS. The ninth transistor T9 includes a twenty-first terminal, a twenty-second terminal, and a ninth control terminal, the twenty-first terminal being coupled to the twentieth terminal of the eighth transistor T8, the twenty-second terminal being coupled to ground, the ninth control terminal being coupled to the eighteenth output terminal of the feedback enabler 14, and the ninth control terminal being configured to receive the feedback enable signal PEAK_EN.

[0042] It should be noted that the bias signal BIAS can be a custom or preset voltage value used to control the conduction state of the eighth transistor T8. For example, when the eighth transistor T8 is an N-type metal-oxide-semiconductor field-effect transistor, the voltage of the bias signal BIAS affects the conduction state of the eighth transistor T8. Therefore, the current flowing through the eighth transistor T8 in the equalization control unit 15 can also be controlled by the bias signal BIAS. Furthermore, the ninth transistor T9 can be considered a switch of the equalization control unit 15. For example, when the ninth transistor T9 is an N-type metal-oxide-semiconductor field-effect transistor and the feedback enable signal PEAK_EN is high, the ninth transistor T9 is on, and the equalization control unit 15 is considered in the on state. When the ninth transistor T9 is an N-type metal-oxide-semiconductor field-effect transistor and the feedback enable signal PEAK_EN is low, the ninth transistor T9 is off, and the equalization control unit 15 is considered in the off state. Furthermore, since the reference signal DIN is received by the control terminal of the seventh transistor T7, the voltage across the reference signal DIN and the second output signal POUT can control the conduction state of the seventh transistor T7. Similarly, since the feedback signal PT_FB1 is received by the control terminal of the sixth transistor T6, the voltage across the feedback signal PT_FB1 and the first output signal POUTB can control the conduction state of the sixth transistor T6. Furthermore, the equalization control unit 15 has an equalization effect, which can filter out noise or interference signals. For example, when the equalization control unit 15 is turned on and the sixth transistor T6 and the seventh transistor T7 are turned on, since the voltages of the first output signal POUTB and the second output signal POUT are opposite, the current between the first output signal POUTB and the second output signal POUT will pass through the resistor R and the capacitor C. Therefore, the high-frequency noise of the current between the first output signal POUTB and the second output signal POUT will be reduced. In other words, in the self-controlled equalization circuit 100, the noise of the signal output by the equalization control unit will be smaller than the noise of the signals output by the first amplifier 10 and the second amplifier 11.

[0043] On the basis of the above embodiment, in a more preferred embodiment, as Figure 8As shown, the gain control unit 16 includes: a tenth transistor T10, including a twenty-third terminal, a twenty-fourth terminal, and a tenth control terminal, the twenty-third terminal being coupled to the first output terminal of the first amplifier 10 for receiving the first output signal POUTB, the tenth control terminal being coupled to the fifth output terminal of the feedback signal generator 12, and the tenth control terminal being used to receive the feedback signal PT_FB1; an eleventh transistor T11, including a twenty-fifth terminal, a twenty-sixth terminal, and an eleventh control terminal, the twenty-fifth terminal being coupled to the second output terminal of the first amplifier 10, the twenty-sixth terminal being coupled to the twenty-fourth terminal of the tenth transistor T10, and the eleventh control terminal being coupled to the second input terminal of the first amplifier 10 for receiving the reference signal DIN; and a twelfth transistor T12, including a twenty-seventh terminal, a twenty-eighth terminal, and a twelfth control terminal, the twenty-seventh terminal being coupled to the twenty-sixth terminal of the eleventh transistor T11, the twenty-eighth terminal being coupled to the ground, and the twelfth control terminal being used to receive the bias signal BIAS.

[0044] It should be noted that the bias signal BIAS can be a custom or preset voltage value used to control the conduction state of the twelfth transistor T12. For example, when the twelfth transistor T12 is an N-type metal oxide semiconductor field effect transistor, the voltage of the bias signal BIAS will affect the conduction state of the twelfth transistor T12. Therefore, the current flowing through the twelfth transistor T12 of the gain control unit 16 can also be controlled by the bias signal BIAS. Similar to the above, since the reference signal DIN is received by the control terminal of the eleventh transistor T11, the voltage between the reference signal DIN and the second output signal POUT can control the conduction state of the eleventh transistor T11. Similarly, since the feedback signal PT_FB1 is received by the control terminal of the tenth transistor T10, the voltage between the feedback signal PT_FB1 and the first output signal POUTB can control the conduction state of the tenth transistor T10. For example, when the tenth transistor T10 and the eleventh transistor T11 are turned on, the voltages of the first output signal POUTB and the second output signal POUT are opposite, so a current is generated between the first output signal POUTB and the second output signal POUT. Furthermore, because the voltage of the bias signal BIAS affects the conduction state of the twelfth transistor T12, a portion of the current between the first output signal POUTB and the second output signal POUT can be directed to the ground terminal by the twelfth transistor T12. When the current magnitude changes, the gain control unit 16 can adjust the gain between the first output signal POUTB and the second output signal POUT.

[0045] In summary, the self-controlled equalization circuit described in the embodiments of the present invention incorporates a gain control unit and an equalization control unit, which automatically adjust its gain and provide equalization functions based on the input data signal to mitigate interference from noisy channels. Therefore, the self-controlled equalization circuit of the present invention is well-suited for high-speed dynamic random access memory applications.

[0046] The embodiments of the present invention are described in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core ideas. At the same time, for those skilled in the art, according to the ideas of the present invention, there may be changes in the specific implementation methods and application scopes. In summary, the contents of this specification should not be understood as limiting the present invention.

Claims

1. Automatic control equalization circuit, characterized in that, include: A first amplifier, a second amplifier, a sampling unit, a feedback signal generator, a frequency delay signal generator, a feedback starter, an equalization control unit, and a gain control unit; The first amplifier includes a first input terminal, a second input terminal, a first output terminal, and a second output terminal, wherein the first input terminal is used to receive a data signal, and the second input terminal is used to receive a reference signal; the second amplifier includes a third input terminal, a fourth input terminal, a third output terminal, and a fourth output terminal; the feedback signal generator includes a fifth input terminal and a fifth output terminal, configured to delay the received signal and output a feedback signal; the frequency delay signal generator includes a sixth input terminal, a sixth output terminal, and a seventh output terminal, wherein the sixth input terminal is used to receive a frequency signal; the feedback activator includes a seventh input terminal, an eighth input terminal, a ninth input terminal, and an eighth output terminal, configured to output a feedback activation signal according to the received feedback signal; the equalization control unit includes a tenth input terminal, an eleventh input terminal, a twelfth input terminal, a thirteenth input terminal, and a ninth output terminal; and the gain control unit includes a fourteenth input terminal, a fifteenth input terminal, a sixteenth input terminal, and a tenth output terminal. The first output terminal and the second output terminal are coupled to the third input terminal and the fourth input terminal, respectively; the fourth output terminal is coupled to the fifth input terminal; the fifth output terminal is coupled to the seventh input terminal, the tenth input terminal, and the fourteenth input terminal, respectively; the sixth output terminal and the seventh output terminal are coupled to the eighth input terminal and the ninth input terminal, respectively; the eighth output terminal is coupled to the thirteenth input terminal; the eleventh input terminal and the sixteenth input terminal are coupled to the first output terminal, respectively; The twelfth input terminal and the fifteenth input terminal are respectively coupled to the second output terminal; the ninth output terminal and the tenth output terminal are respectively coupled to the second input terminal; The sampling unit is coupled to the frequency delay signal generator.

2. The self-controlled equalization circuit according to claim 1, wherein: The sampling unit includes a seventeenth input terminal, an eighteenth input terminal, an eleventh output terminal, and a twelfth output terminal, wherein the eleventh output terminal is used to output an output signal with an even index, and the twelfth output terminal is used to output an output signal with an odd index; The seventeenth input terminal and the eighteenth input terminal are coupled to the third output terminal and the fourth output terminal respectively.

3. The self-controlled equalization circuit according to claim 1, wherein: The first amplifier comprises: A first transistor comprising a first terminal, a second terminal and a first control terminal, wherein the first terminal is configured to receive an operating voltage; a second transistor comprising a third terminal, a fourth terminal, and a second control terminal, wherein the third terminal is configured to receive an operating voltage, and the second control terminal is coupled to the first control terminal; a third transistor comprising a fifth terminal, a sixth terminal and a third control terminal, wherein the fifth terminal is coupled to the second terminal, and the third control terminal is used to receive the data signal; a fourth transistor comprising a seventh terminal, an eighth terminal, and a fourth control terminal, the seventh terminal being coupled to the fourth terminal, the eighth terminal being coupled to the sixth terminal, and the fourth control terminal being configured to receive the reference signal; The fifth transistor includes a ninth terminal, a tenth terminal and a fifth control terminal, the ninth terminal is coupled to the eighth terminal, the tenth terminal is coupled to the ground terminal, and the fifth control terminal is used to receive a bias signal.

4. The self-controlled equalization circuit according to claim 1, wherein: The frequency delay signal generator comprises: A first inverter unit, comprising a plurality of first inverters connected in series, wherein an input end of the first inverter unit is used to receive the frequency signal, and an output end of the first inverter unit outputs a frequency delay signal; The second inverter includes a nineteenth input terminal and a thirteenth output terminal, the nineteenth input terminal is connected to the output terminal of the first inverter unit, the nineteenth input terminal is used to receive the frequency delay signal, and the thirteenth output terminal is used to output an inverse frequency delay signal.

5. The self-controlled equalization circuit according to claim 4, wherein: The feedback starter includes: a third inverter comprising a twentieth input terminal and a fourteenth output terminal, wherein the twentieth input terminal is coupled to the fifth output terminal; a first NOR gate, comprising a twenty-first input terminal, a twenty-second input terminal, and a fifteenth output terminal, wherein the twenty-first input terminal is coupled to the output terminal of the first inverter unit, the twenty-second input terminal is coupled to the thirteenth output terminal, the twenty-first input terminal is used to receive the frequency delay signal, and the twenty-second input terminal is used to receive an inverse frequency delay signal; a second NOR gate comprising a twenty-third input terminal, a twenty-fourth input terminal, and a sixteenth output terminal, wherein the twenty-third input terminal is coupled to the fourteenth output terminal, and the twenty-fourth input terminal is coupled to the fifteenth output terminal; a fourth inverter comprising a twenty-fifth input terminal and a seventeenth output terminal, wherein the twenty-fifth input terminal is coupled to the sixteenth output terminal; The fifth inverter includes a twenty-sixth input terminal and an eighteenth output terminal, wherein the twenty-sixth input terminal is coupled to the seventeenth output terminal.

6. The self-controlled equalization circuit according to claim 5, wherein: The equalization control unit includes: a sixth transistor comprising an eleventh terminal, a twelfth terminal, and a sixth control terminal, the eleventh terminal being coupled to the first output terminal, the sixth control terminal being coupled to the fifth output terminal, the sixth control terminal being configured to receive a feedback signal output by the feedback signal generator, the feedback signal being a signal output by the feedback signal generator after delaying the signal output by the fourth output terminal; a seventh transistor comprising a thirteenth terminal, a fourteenth terminal, and a seventh control terminal, the thirteenth terminal being coupled to the second output terminal, the fourteenth terminal being coupled to the twelfth terminal, and the seventh control terminal being coupled to the second input terminal to receive the reference signal; a resistor, comprising a fifteenth terminal and a sixteenth terminal, wherein the fifteenth terminal is coupled to the twelfth terminal, and the sixteenth terminal is coupled to the fourteenth terminal; a capacitor, comprising a seventeenth terminal and an eighteenth terminal, wherein the seventeenth terminal is coupled to the twelfth terminal, and the eighteenth terminal is coupled to the fourteenth terminal; an eighth transistor comprising a nineteenth terminal, a twentieth terminal, and an eighth control terminal, wherein the nineteenth terminal is coupled to the fourteenth terminal, and the eighth control terminal is used to receive a bias signal; The ninth transistor includes a twenty-first terminal, a twenty-second terminal, and a ninth control terminal. The twenty-first terminal is coupled to the twenty-second terminal, the twenty-second terminal is coupled to the ground terminal, and the ninth control terminal is coupled to the eighteenth output terminal.

7. The self-controlled equalization circuit according to claim 6, wherein: The gain control unit includes: a tenth transistor comprising a twenty-third terminal, a twenty-fourth terminal, and a tenth control terminal, the twenty-third terminal being coupled to the first output terminal, the tenth control terminal being coupled to the fifth output terminal, and the tenth control terminal being configured to receive the feedback signal; an eleventh transistor comprising a twenty-fifth terminal, a twenty-sixth terminal, and an eleventh control terminal, the twenty-fifth terminal being coupled to the second output terminal, the twenty-sixth terminal being coupled to the twenty-fourth terminal, and the eleventh control terminal being coupled to the second input terminal to receive the reference signal; The twelfth transistor includes a twenty-seventh terminal, a twenty-eighth terminal and a twelfth control terminal, the twenty-seventh terminal is coupled to the twenty-sixth terminal, the twenty-eighth terminal is coupled to the ground terminal, and the twelfth control terminal is used to receive a bias signal.

8. The self-controlled equalization circuit according to claim 1, wherein: The feedback signal generator includes: The second inverter unit includes a plurality of sixth inverters connected in series. The input end of the second inverter unit is coupled to the fourth output end. The second inverter unit is used to delay the signal output from the fourth output end to output a feedback signal.

9. The self-controlled equalization circuit according to claim 1, wherein: Noise of the signals output by the first amplifier and the second amplifier is greater than noise of the signal output by the equalization control unit.

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