Complementary metal-oxide-semiconductor (CMOS) multi-well devices for cellular electrical assessment

Abstract

This document discloses CMOS-compatible wafer-level, multi-well platform semiconductor devices and methods of operation thereof for use in biomedical or other applications. In some embodiments, a circuit system is provided below the multi-well array for electrical docking with electrodes in the wells. For docking with electrodes in a large array, the circuit system can be fabricated on a single silicon (Si) wafer having dimensions at least the same as or greater than the dimensions of the multi-well array. According to one aspect of this disclosure, standard CMOS manufacturing processes, such as those known to be used in standard semiconductor foundries, can be used without the need for expensive customization of complex manufacturing processes. This can help reduce production costs in some cases.

Description

[0001] Cross-reference to related applications

[0002] This application claims the benefit of U.S. Provisional Patent Application Serial No. 63 / 040,412, entitled “Complementary Metal-Oxide-Semiconductor (CMOS) Multi-Well Apparatus for Electrical Cell Assessment”, filed June 17, 2020, which is incorporated herein by reference in its entirety. Technical Field

[0003] This disclosure relates to a semiconductor device for electrically evaluating cells or other biological samples in a multi-well array. Summary of the Invention

[0004] This document discloses CMOS-compatible wafer-level, multi-well platform semiconductor devices and methods of operation thereof for use in biomedical or other applications. In some embodiments, a circuit system is provided below the multi-well array for electrical docking with electrodes in the wells. For docking with electrodes in a large array, the circuit system can be fabricated on a single silicon (Si) wafer having dimensions at least the same as or greater than the dimensions of the multi-well array. According to one aspect of this disclosure, standard CMOS manufacturing processes, such as those known to be used in standard semiconductor foundries, can be used without the need for expensive customization of complex manufacturing processes. This can help reduce production costs in some cases.

[0005] Some embodiments relate to semiconductor devices for use with biochemical or other sensors. The semiconductor device may include a multi-well array. The semiconductor device may also include a wafer, and in some cases, at least two reticle regions deployed within the wafer. Some or all of the reticle regions may have multiple circuit systems of the same design. Some or all of the reticle regions may include at least one well circuit configured to be electrically connected to the wells of the multi-well array, routing circuitry configured to route a first type of signal along a first direction from a first side of the reticle region to a second side of the reticle region, and routing a second type of signal along a second direction different from the first direction from a third side of the reticle region to a fourth side of the reticle region.

[0006] In some embodiments, at least two grid regions of a semiconductor device can be in electrical communication with each other. The semiconductor device can include a plurality of cross-grid connections configured to place the at least two grid regions in electrical communication. The at least two grid regions can be disposed on a first surface of a wafer. The semiconductor device can include a redistribution layer (RDL) on the first surface, where at least a portion of the plurality of cross-grid connections can include conductors disposed in the RDL layer. The semiconductor device can include an interposer facing a second surface of the wafer opposite the first surface. The interposer can be a printed circuit board (PCB). The interposer can include a cavity and the wafer is mounted in the cavity. Some or all of the grid regions can have a rectangular shape with sides aligned with a first direction and a second direction. The first type of signal can be a digital signal and the second type of signal can be an analog signal. Routing circuitry in a first grid region can be configured to receive the first type of signal from a second grid region adjacent to the first grid region along the first direction. The routing circuitry in the first grid region can also be configured to receive the second type of signal from a third grid region adjacent to the first grid region along the second direction. The semiconductor device can be configured to be coupled underneath a multi-well array such that some or all of the well circuitry is in electrical communication with and disposed adjacent to a corresponding well in the multi-well array. The routing circuitry can include one or more shift registers configured to route the first type of signal. The routing circuitry can include at least one digital bus and at least one analog bus. At least one well circuitry can be configured to be in electrical communication with a plurality of electrodes in an electrode array disposed in a well. The plurality of electrodes can include at least 1000 electrodes. The plurality of electrodes can include at least 4000 electrodes. Some or all of the well circuitry can include a plurality of peripheral circuitries. Some or all of the peripheral circuitries can include stimulation circuitry and recording circuitry. The stimulation circuitry can include a current injector. The semiconductor device can include one or more switches configured to selectively couple a subset of the peripheral circuitries within a well circuitry to a subset of electrodes within the electrode array. The one or more switches can be further configured to selectively couple the subset of the peripheral circuitries to one or more optoelectronic components. The one or more optoelectronic components can include a light-emitting diode, a photodetector, or a combination thereof. An electrode in the subset of electrodes can be a reference electrode. The at least two grid regions can be an array of grid regions arranged in rows along the first direction and arranged in columns along the second direction, where adjacent grid regions in some or all of the rows are connected by an array of cross-grid connections arranged along the second direction and adjacent grid regions in some or all of the columns are connected by an array of cross-grid connections arranged along the first direction. The semiconductor device can be configured to be coupled underneath a multi-well array, where some or all of the grid regions are underneath a corresponding well of the multi-well array. Some or all of the grid regions can have a width of at least 9 mm. Some or all of the grid regions can have a width of at least 18 mm.Some or all of the reticle regions can include more than one well circuit. The multi-well array can have at least 96 wells. The wafer can have a lateral dimension equal to or greater than a maximum lateral extent of the multi-well array. The wafer can comprise silicon. Some or all of the reticle regions can be integrated circuits that can include complementary metal-oxide-semiconductor (CMOS) components.

[0007] Some embodiments relate to a method of operating a semiconductor device to test a biochemical sensor comprising a multi-well array. The semiconductor device comprises a wafer within which at least two reticle regions are disposed. Some or all of the reticle regions have a plurality of circuitry of a same design, and some or all of the reticle regions comprise at least one well circuit and a routing circuit. The method of operating can comprise placing the at least one well circuit in electrical communication with a well of the multi-well array; routing a first type of signal from a first side of the reticle region to a second side of the reticle region along a first direction using the routing circuit, and routing a second type of signal from a third side of the reticle region to a fourth side of the reticle region along a second direction different from the first direction.

[0008] In some embodiments, the first type of signal can be a digital signal and the second type of signal can be an analog signal. Routing the first type of signal and the second type of signal can comprise: transmitting the first type of signal from a second reticle region to a first reticle region adjacent to the second reticle region along the first direction; and transmitting the second type of signal from a third reticle region to the first reticle region, wherein the third reticle region is adjacent to the first reticle region along the second direction. Placing in electrical communication can comprise: providing one or more stimuli to a cell disposed in the multi-well array, measuring one or more properties of the cell, or a combination thereof. The one or more properties of the cell can comprise: impedance, adhesion, redox potential, action potential, conduction velocity, synaptic mapping, or a combination thereof. The one or more stimuli can comprise a current or a voltage. Some or all of the well circuits can comprise a plurality of peripheral circuits. Some or all of the peripheral circuits can comprise a stimulation circuit and a recording circuit, and wherein placing in electrical communication can further comprise: selectively coupling a subset of the peripheral circuits within the well circuit to a subset of electrodes within an electrode array in the well using one or more switches in the semiconductor device; providing the one or more stimuli to the cell via the subset of electrodes using the stimulation circuit in the subset of the peripheral circuits; and measuring the one or more properties of the cell via the subset of electrodes using the recording circuit in the subset of the peripheral circuits. The method can comprise: selectively coupling a photoelectric element to the peripheral circuit; and emitting a light signal to the cell disposed in the multi-well array or receiving a light signal from the cell disposed in the multi-well array using the photoelectric component.

[0009] Some embodiments relate to an apparatus for electrical evaluation of biological samples. The apparatus can include a plate having a multi-well array for housing a biological sample, each well of the multi-well array having a plurality of electrodes disposed therein; a wafer having a first surface facing a first side of the plate can include an array of reticle regions each having a plurality of circuitry of a same design, wherein each reticle region can include at least one well circuit configured to be in electrical communication with the electrodes in a well of the multi-well array; a routing circuit configured to route a first type of signal from a first side of a reticle region to a second side of the reticle region along a first direction and to route a second type of signal from a third side of the reticle region to a fourth side of the reticle region along a second direction different from the first direction. The apparatus can further include a first substrate having a wafer attachment surface facing a second surface of the wafer opposite the first surface, the first substrate can include a plurality of conductors electrically connecting at least a portion of the array of reticle regions to a plurality of pads disposed on a mounting surface of the first substrate opposite the wafer attachment surface.

[0010] In some embodiments, the first substrate is an interposer that can include a cavity, wherein the wafer attachment surface is disposed within the cavity, and wherein the second surface of the wafer is attached to the wafer attachment surface of the first substrate. The apparatus can include a cover coupled to a second side of the plate opposite the first side. The cover can include a plurality of reference electrodes. Some or all of the reference electrodes can extend into corresponding wells of the multi-well array. The cover can include a plurality of optoelectronic emitters. Some or all of the optoelectronic emitters can face corresponding wells of the multi-well array. The apparatus can include a second substrate having a plurality of conductive structures disposed at a first surface facing the mounting surface of the first substrate. Some or all of the conductive structures can be electrically connected to corresponding pads of the plurality of pads on the mounting surface of the first substrate. The second substrate and the first substrate can be coupled via magnetic force. The apparatus can include an enclosure surrounding the wafer and the plate on at least five sides. The biological sample can include a plurality of single cells. The plurality of electrodes within a well are configured to be in electrical communication with an interior of a single cell disposed in the well. The first type of signal can be a digital signal and the second type of signal is an analog signal. The routing circuit in a first reticle region can be configured to receive the first type of signal from a second reticle region adjacent to the first reticle region along the first direction, and the routing circuit in the first reticle region can be further configured to receive the second type of signal from a third reticle region adjacent to the first reticle region along the second direction. Some or all of the well circuits can include a plurality of peripheral circuits. Some or all of the peripheral circuits can include a stimulation circuit and a recording circuit, and the apparatus can further include one or more switches configured to selectively couple a subset of the peripheral circuits within the well circuits to a subset of the electrodes within the plurality of electrodes. BRIEF DESCRIPTION OF DRAWINGS

[0011] Various aspects and embodiments will be described with reference to the following figures. It should be understood that the figures are not necessarily drawn to scale. Items appearing in multiple figures are indicated by the same reference numerals in all figures in which they appear. In the figures:

[0012] Figure 1 This is a high-level block diagram illustrating an exemplary CMOS-multiwell platform according to some embodiments;

[0013] Figure 2A This is a high-level schematic diagram illustrating an exemplary CMOS-multiwell platform according to some embodiments;

[0014] Figure 2B This is a top view schematic diagram of an exemplary semiconductor device that can be used in a CMOS-multiwell platform according to some embodiments; Figure 2C yes Figure 2B A magnified view of a portion;

[0015] Figure 3 This is a schematic block diagram illustrating an exemplary apparatus for electrical evaluation of biological samples according to some embodiments;

[0016] Figure 4 This is a cross-sectional schematic diagram of an exemplary device according to some embodiments;

[0017] Figure 5 This is a cross-sectional schematic diagram of an exemplary device according to some embodiments that can interface with an external data acquisition system;

[0018] Figure 6 This is a schematic plan view of an exemplary environmental chamber according to some embodiments;

[0019] Figure 7 This is a top view schematic diagram of an exemplary chip according to some embodiments;

[0020] Figure 8 This is a top view schematic diagram of an example circuit design within the marked area according to some embodiments;

[0021] Figure 9 This is a schematic block diagram illustrating an exemplary trap circuit within the marked area 920 according to some embodiments;

[0022] Figure 10A and Figure 10B These are top and bottom view schematic diagrams of an example design of an environmental chamber cover with a reference electrode according to some embodiments;

[0023] Figure 11A , Figure 11B and Figure 11C Several exemplary applications of the apparatus as disclosed herein are illustrated. Detailed Implementation

[0024] This disclosure relates to a semiconductor device providing a CMOS-compatible wafer-level multi-well platform for use in biomedical or other applications, and methods of operation thereof. In some applications, a circuit system is provided beneath the multi-well array to electrically interface with electrodes in the wells. This platform may sometimes be referred to as a CMOS-multi-well platform. The inventors have recognized and understood that, in order to interface with electrodes in a large array, the circuit system can be fabricated on a single silicon (Si) wafer having dimensions at least the same or greater than the dimensions of the multi-well array. According to one aspect of this disclosure, standard CMOS fabrication processes, such as those known to be used in standard semiconductor foundries, can be used without the need for expensive customization of complex manufacturing processes, thus reducing production costs in some cases. The CMOS-multi-well platform according to some aspects of this disclosure can be used for applications including electrophysiological studies and general cell evaluation using electrical methods and / or in high-throughput formats (e.g., 24-, 96-, and 384-well plate formats).

[0025] In some embodiments, the Si wafer is part of a semiconductor device and has an array of marked regions, some or all of which have multiple circuit systems of the same design. The inventors have recognized and understood that, during manufacturing, the marked regions of the wafer can, in some cases, reuse the same photomask design repeated throughout the wafer, thereby reducing processing costs and increasing wafer manufacturing throughput.

[0026] According to one aspect, when a multi-well array is coupled to the top of a wafer, digital and analog circuitry systems within the marked area can be arranged to correspond to one or more wells. Therefore, some embodiments can reduce manufacturing costs by providing wafer-level integration with electrical connections to the multi-well array using non-diced wafers and / or standard-compatible manufacturing methods employing standard CMOS-compatible technologies.

[0027] Furthermore, according to some aspects, because the datum regions are spaced apart from each other according to the spacing of the multi-well array, cross-datum connections can be provided in the semiconductor device to route power and data signals between the datum regions. Cross-datum connections can be made using conductors deployed in a plane different from the datum regions, such as in a redistribution layer (RDL) deployed above or below the wafer.

[0028] To route large amounts of data signals across the wafer, some or all of the marked regions of the wafer may include well circuitry configured to route digital signals along a first direction (X-direction) across the marked regions and analog signals along a second direction (Y-direction), for example, such that digital and analog signals are cascaded from one marked region to the next until the edge of the wafer. Some or all of the marked regions may also include reconfigurable peripheral circuitry. Some or all of the peripheral circuitry may include stimulation circuitry, recording circuitry, or a combination of one or more of stimulation and recording circuitry. The semiconductor device may include addressable switches that can selectively couple a subset of the peripheral circuitry within the well circuitry to a subset of selected electrodes deployed in a well above the well circuitry. Optionally, and in addition to the electrodes, the switches may couple the peripheral circuitry to one or more optoelectronic components. The optoelectronic components may be photodetectors or light-emitting diodes, and in some embodiments may be provided in a 1:1 ratio to the number of electrode arrays, such that the function of each well above the marked regions can be programmed individually and independently to allow a range of different evaluations in a multi-well array. The aspects and embodiments described above, as well as other aspects and embodiments, are further described below. These aspects and / or embodiments may be used alone, together, or in any combination of two or more, as this disclosure is not limited in this respect.

[0029] Figure 1 This is a high-level block diagram illustrating an exemplary CMOS multiwell platform according to some embodiments. Figure 1 A semiconductor device 50 including a wafer 51 is shown. At least two tracing regions 52 are deployed within the wafer 51, wherein some or all of the tracing regions have multiple circuit systems of the same design. The circuit system within each tracing region 52 includes at least one well circuit 53 and a routing circuit 54. The routing circuit 54 routes a signal of type 55 along a first direction y from a first side 61 of the tracing region 52 toward a second side 62 of the tracing region 52, and routes a signal of type 56 along a second direction x from a third side of the tracing region 63 toward a fourth side of the tracing region 64. The semiconductor device 50 is configured for use with a biochemical sensor including a multi-well array. For example, the semiconductor device 50 may be coupled along the z-direction to a multi-well array 1 such that the well circuit 53 in the corresponding tracing region 52 is electrically connected to a corresponding well 2 in the multi-well array 1.

[0030] exist Figure 2AIn this embodiment, a 96-well plate 10 is provided as part of a biosensor for evaluating biological samples, such as single cells, deployed within an array of wells 12. The wells 12 may have an array of electrodes 14 deployed within the wells, for example, at the bottom surface of the well 12, to serve as probes that can dock with samples within the wells, either extracellularly or intracellularly. The 96-well plate 10 is attached to a semiconductor device 100, which includes a substrate 110 and an interposer 102. In some embodiments, the substrate 110 includes an integrated circuit (IC) and is bonded to the interposer printed circuit board (PCB) via wire bonding or flip-chip solder bump connections. Circuitry within the substrate 110 is located beneath each well 12 and is electrically communicated with the electrodes 14 deployed within the wells 12. It should be understood that the plate 10 is shown as a 96-well array for illustrative purposes only, and other aspects of this disclosure are not limited thereto, and may be adapted to, for example, 24-well, 384-well, or other suitable multi-well array formats known in the art.

[0031] Figure 2A This is a high-level schematic diagram illustrating an exemplary CMOS-multiwell platform according to some embodiments. Figure 2A In this embodiment, a 96-well plate 10 is provided as part of a biosensor for evaluating biological samples, such as single cells, deployed within an array of wells 12. The wells 12 may have an array of electrodes 14 deployed within the well, for example, at the bottom surface of the well 12, to serve as probes that can dock with samples within the well, either extracellularly or intracellularly. The 96-well plate 10 is attached to a semiconductor device 100, which includes a substrate 110 and an interposer 102. In some embodiments, the substrate 110 includes an integrated circuit (IC) and is bonded to the interposer printed circuit board (PCB) via wire bonding. Circuitry within the substrate 110 is located beneath each well 12 and is electrically communicated with the electrodes 14 deployed within the wells 12. It should be understood that the plate 10 is shown as a 96-well array for illustrative purposes only, and other aspects of this disclosure are not limited thereto, and may be adapted to, for example, 24-well, 384-well, or other suitable multi-well array formats known in the art.

[0032] The number of electrodes in electrode array 14 may be at least 1,000, at least 4,000, or in some embodiments at least 1 million, as aspects of this disclosure are not limited thereto. It should be understood that although electrode array 14 is shown deployed within well 12 of board 10, electrode array 14 need not be provided as part of a multi-well board or as a component separate from semiconductor device 100. In some embodiments, electrode array 14 may be deployed within semiconductor device 100, for example as a conductor exposed from an insulating surface of substrate 110 facing board 10. In some embodiments, electrode array 14 may be patterned on the surface of substrate 110 as part of a semiconductor manufacturing process to form semiconductor device 100, and may be metal pads comprising Au or Pt or alloys thereof. In such embodiments, substrate 110 may additionally include conductors vertically interconnecting the exposed electrode array 14 to circuitry within substrate 110.

[0033] Figure 2B This is a top view schematic diagram of an exemplary semiconductor device 200 that can be used in a CMOS multi-well platform according to some embodiments. Figure 2B In the substrate 210, there are 8 x 12 = 96 marker regions 220, and the substrate 210 can be referred to as a multi-well IC. The substrate 210 can be a Si wafer, and each marker region can have the same design, manufactured by stepping markers along the X and Y directions using standard photolithography processes without cutting the wafer. Each marker region can include multiple layers, including an active layer containing silicon components, and one or more layers containing conductors and dielectric materials as connections and interconnects. Figure 2C As shown in the magnified view image, each marked area may contain one or more identical trap circuits 230.

[0034] exist Figure 2B In the embodiment shown, each marking region 220 can be a CMOS chip and all 96 chips are connected by cross-marking connections that can be manufactured using standard semiconductor processing techniques.

[0035] Figure 3This is a schematic block diagram of an exemplary device 1000 for electrical evaluation of biological samples, illustrated according to some embodiments. Device 1000 may be an example of a CMOS-multi-well platform and includes a board 30 with a multi-well array. In some non-limiting examples, board 30 may be a standard 24, 96, or 384-well board. Board 30 is mechanically attached to wafer 310, which may be a multi-well IC. Wafer 310 may be a silicon wafer including a plurality of marker regions 320. Marker regions 320 may be arranged in an array on the surface of wafer 310 and may be uncut silicon dies. Adjacent marker regions are electrically connected to each other, for example, via cross-marker connections. Each marker region may have the same circuit design. In some embodiments, each marker region may have N identical well circuits 330. Figure 2B In the example shown, a well circuit is provided to electrically interface with an electrode in one of the wells of board 30. For example, when there are 24 marked regions, N can be 1 for a 24-well format, 4 for a 96-well format, and 16 for a 384-well format. However, it should be understood that the design of the marked and well circuits is not limited to providing a one-to-one correspondence with the wells, and more or fewer well circuits can be provided for each well. In some embodiments, the well circuits can be reconfigured, for example, by using multiple switches to couple to different wells.

[0036] Still referencing Figure 3 The wafer 310 is mechanically and electrically attached to the interposer 302. Any suitable bonding method known in the semiconductor packaging art can be used to couple the wafer 310 to the interposer 302, such as, but not limited to, flip-chip bonding or wire bonding. The apparatus 1000 may additionally and optionally include components for electrically evaluating biological samples deployed in the traps of the board 30. Such components may include a data acquisition system communicating with contact pads on the interposer 302, or one or more computers having a processor capable of executing programs stored in one or more storage media to implement methods for testing using the wafer 310. Furthermore, in some embodiments, robotics may be used in conjunction with the board 30 to provide automated sample handling and placement.

[0037] Figure 4 This is a cross-sectional schematic diagram of an exemplary device according to some embodiments. Figure 4 In this configuration, the first or top surface 422 of the multi-well IC 420 faces the well 42 in the board 40, while the second or bottom surface 424 of the multi-well IC faces the opposite well and the interposer layer. Multiple marked regions (not shown) are deployed in the top surface of the multi-well IC. The multi-well IC 420 is coupled to the interposer layer 402 at the wafer attachment surface 406. The interposer layer 402 may include, for example, Figure 4The cavity 404 shown may, in some examples, have a cavity height similar to the thickness of the wafer forming the multi-well IC 420. A wafer attachment surface 406 may be deployed at the bottom surface of the cavity 404, and the multi-well IC 420 is located within the cavity 404 and wire-bonded to the interposer 402. The input / output (I / O) connections of the multi-well IC 420 may be wire-bonded and routed to contact pads 408 deployed on a mounting surface 409 at the bottom of the interposer 402. It should be understood that the connection between the interposer and the multi-well IC is not limited to... Figure 4 The wire bonding shown in the example can be accomplished via flip-chip bonding or other techniques in some embodiments. Pad 408 can alternatively be implemented as a gold finger, cable, or connector (e.g., USB) instead of a contact pad. For example, a PCB with a central opening and pads aligned with the pads of a multi-well IC can be used for flip-chip bonding, where solder bumps directly connect the interposer pads to the pad array in the multi-well IC without wire bonding.

[0038] like Figure 4 As shown, well 42 is a bottom-open well that is attached to the multi-well IC 420 and the interposer 402, such that the interior of well 42 can be fluidly connected to the top surface 422 of the multi-well IC 420, but aspects of this disclosure are not limited to bottom-open wells.

[0039] Figure 5 This is a cross-sectional schematic diagram of an exemplary device, according to some embodiments, capable of interfacing with an external data acquisition system. Figure 5 In, with Figure 4 Similar components are indicated by the same reference numerals. Figure 5 In this configuration, an environmental chamber or incubator 506 with keyway features guides the alignment of the trap plate 40 with an array of spring-loaded contacts 504 on the second substrate 502 that have a matching pattern with the contact pads 408 on the interposer layer 402. The enclosed chamber 506 provides an isolated environment for the gas-controlled experimental trap 42. In some embodiments, the second substrate 502 can provide mechanical support and environmental sealing for the chamber 506. Furthermore, the second substrate 502 can provide electrical interconnection between the multi-well IC 420 within the chamber 506 and an external data acquisition system outside the chamber 506. The second substrate 502 can be physically secured to the interposer layer 402 using suitable clamping techniques. In some embodiments, the second substrate 502 is magnetically coupled to the interposer layer 402, for example using a pair of magnets deployed on the mounting surface 409 of the interposer layer 402 and the top surface of the second substrate 502, which provide tension / engagement forces to ensure adequate contact between the pads 408 and the spring-loaded contacts 504.

[0040] Figure 6 This is a plan view of an exemplary environmental chamber 606 according to some embodiments.Figure 6 The environmental chamber 606 is shown to include a cover 608 that can be snapped onto a housing 610 to create an outer shell having two bottom-facing openings, wherein opening 602 leads to a trap plate and opening 604 is used to provide gas control for the environmental chamber 606.

[0041] Figure 7 This is a top view schematic of an exemplary wafer 710 according to some embodiments. Wafer 710 may be a multi-well IC and, in the example shown, consists of 4x6 = 24 identical marker regions (e.g., 18mm x 18mm). The marker regions may be designed with a specific symmetry such that simple redistribution layer (RDL) connections between the I / O pads of adjacent marker regions will allow I / O signals to pass through the entire wafer. The RDL may include conductors such as metal traces, which serve as cross-marker connections to interconnect adjacent marker regions, and I / O pad leads deployed around the periphery of wafer 710 can then be wirebonded to an interposer layer, such as... Figure 4 As shown in the image.

[0042] Figure 8 This is a top view schematic diagram illustrating an example circuit design within the marked area according to some embodiments. Figure 8 In the diagram, the marked area contains four identical well circuits 830 positioned to allow alignment of a standard well plate (e.g., 9 mm apart), but it should be understood that any suitable number of well circuits... Figure 8 The variations of the design shown can be used for other multi-well arrays, such as 24-well and 384-well boards. For the 24-well version of the marker, only one well circuit should be located at the center of the marker in this example. For example, in the 384-well version of the marker area, 16 well circuits can be positioned to allow a standard 4.5mm well pitch.

[0043] exist Figure 8 In this design, the marking area 820 is designed with symmetrical I / O pads on its periphery, both horizontally and vertically, allowing signals to be routed across the marking area and into adjacent marking areas via the cross-marking signal bus 820. Each well circuit 830 within the marking area 820 may have a dedicated signal buffer to buffer global signals to its local well circuit, and vice versa. In one embodiment, different types of signals are routed along the X and Y directions to improve routing efficiency when daisy-chaining multiple rows and columns of marking areas. For example, the cross-marking signal bus 822 may be a routing circuit that routes digital signals from left to right along the X direction of the marking area and analog signals from top to bottom along the Y direction.

[0044] Figure 9This is a schematic block diagram illustrating an exemplary well circuit 930 within a marker region 920 according to some embodiments. In the well circuit 930, a plurality of peripheral circuits 934 are designed to be connected to all or a subset of an array of electrodes 936 within a multi-well array attached to the top of a wafer in which the marker region 920 is deployed. The electrode array may also be referred to as pixels, each pixel occupying a pixel area. In a non-limiting example, the well circuit 930 has 256 peripheral circuits. Through selective operation of a plurality of switches 932, all or a subset of the peripheral circuits can be connected to all or a subset of 4096 pixels in the well to allow high-density (HD), medium-density (MD), or low-density (LD) connections. By connecting the electrodes to a reference electrode bias (V... REF Any set of arbitrary pixels can also serve as a reference electrode. In the described non-limiting example, in the HD (MD) connection, a subset of 16x16 (32x32) pixels is recorded from the total 64x64 available pixels. This routing design allows scanning the recording area over the entire available effective area (64x64) (16x16 for HD and 32x32 for MD). This example design allows for well-tailored experimental setups.

[0045] In some embodiments, switch 932 may also selectively couple peripheral circuitry 934 to one or more optoelectronic components instead of electrodes. Examples of optoelectronic components include photodetectors or photoemitters, such as light-emitting diodes, such that the function of each well above the marker area can be programmed individually and independently to allow for a range of different evaluations to be performed within the multi-well array. In some embodiments, the optoelectronic component may be a photodiode fabricated on a wafer such as wafer 710 and deployed in a photosensitive region within a pixel region. In a non-limiting example, the lateral spatial span of the photosensitive region covers the same area as the electrode array in the pixel region, but it should be understood that other suitable placements or dimensions for the optoelectronic component may be used. In some embodiments, the optoelectronic interface has a 1:1 mapping to the electrical interface, and an optoelectronic component is provided for each electrode array or each pixel region, but a 1:1 mapping is not required.

[0046] Return to reference Figure 9The peripheral circuitry 934 may each include a stimulation circuit and a recording circuit. In some embodiments, the stimulation circuitry may include one or more current injectors. Some aspects of the peripheral circuitry design relate to current-based stimulators and related methods for electrogenic cells, such as those disclosed in International Application Publication No. WO2019 / 010343, Agent's File No. H0776.70105WO00, the disclosure of which is incorporated herein by reference in its entirety. Some aspects may also relate to electronic circuitry and related methods for analyzing electrogenic cells, such as those disclosed in International Application Publication No. WO2019 / 089495, Agent's File No. H0498.70647WO00, the disclosure of which is incorporated herein by reference in its entirety.

[0047] Still referencing Figure 9 In the design of the trap circuit, the global digital control and configuration signals can be routed from left to right from the center of the marker, while the global analog signals (output and control signals) are routed from top to bottom, also at the center of the marker. Figure 8 As shown in the diagram. In some embodiments, each well circuit buffers its local signals in and out of the global bus.

[0048] Digital Interface

[0049] According to one aspect of this disclosure, in order to allow for simple and rapid programming of multi-well ICs, such as... Figure 7 The chip 710 shown performs programming across all 24 tracks and can provide a three-level Serial Peripheral Interface (SPI). The highest-level SPI selects one or more specific wells from the multi-well IC to program the two lower-level SPIs. The inputs of this SPI (D...) IN The ) may originate from the I / O pads to the left of the marked area, and the output of this SPI (D) OUT The data is routed to the symmetrical I / O pads to the right of the marker area, which allows for simple RDL connections to daisy-chain the markers together. The lower two levels of SPI can share control signals throughout the multi-well IC. In some embodiments, the address-select SPI selects components within the well circuitry (e.g., peripheral circuitry and temperature control) for programming by the configuration SPI, which writes to the registers of the selected component in the selected well.

[0050] Analog output

[0051] Furthermore, according to embodiments of this disclosure, each marker area may have, for example, eight analog output buses routed from the top I / O pads to the bottom I / O pads. Analog outputs of peripheral circuitry in each well are multiplexed to one of the eight buses. Since each marker has four wells but eight analog buses, this design allows the top two rows (2x6) of the marker area to be read from the top side, and the bottom two rows (also 2x6) to be read from the bottom side of the marker area; however, aspects of this disclosure are not limited thereto and other suitable readout schemes may be used. The inventors have recognized and understand that the routing of analog and digital signals as described herein can advantageously improve signal routing efficiency by simplifying the routing design. However, it should be understood that other numbers of analog buses are also possible in other embodiments. Optionally or alternatively, after the analog signal is converted in an analog-to-digital converter within the marker, the signal may be routed entirely digitally and converted back to analog form using a digital-to-analog converter when stimulation is required.

[0052] Figure 10A and Figure 10B These are top and bottom schematic diagrams, respectively, of an example design of an environmental chamber cover with a reference electrode according to some embodiments. The cover may include an Ag / AgCl reference electrode, which the inventors have identified as an important reference electrode material for electrochemical applications. Figure 10A In the example shown, 24 / 96 / 384 reference electrodes and their control circuitry are integrated on a PCB cover with the same form factor as a standard trap board. The control circuitry can be programmed using SPI to allow for trap-by-trap customized experiments. The reference electrodes can measure solution / dielectric voltage / current and apply stimulation to the experimental traps. The cover design can additionally accommodate photodiodes or photoemitters for optical applications (e.g., optogenetics / optical electrochemical sensing).

[0053] application

[0054] Figure 11A , Figure 11B and Figure 11C Several exemplary applications of the device disclosed herein are illustrated. Beyond electrophysiological studies, the CMOS-multiwell platform described herein can also expand its applications using impedance and electrochemical measurements.

[0055] For example, CMOS multi-well platforms can be used for cell or tissue mapping, such as spatial characterization of one or more properties of cells or tissues deployed on a well surface. These properties may be associated with one or more phenomena, such as cell fusion, cell migration, cell viability / toxicity, and cell adhesion. In a non-limiting example, an impedance map between electrodes in an electrode array can be created, representing the spatial distribution of cells relative to the electrodes.

[0056] As another exemplary use case, the CMOS-multi-well platform described herein can be used to perform patterned redox electrochemistry in selected spatial regions by selectively activating selected patterns of electrodes within the wells. Patterned electrochemistry can be used to electrochemically interact with cellular patterns or to perform electrochemical sensing, such as sensing of pH, O2 levels, etc., in selectively patterned spatial regions.

[0057] As another example, CMOS-multi-well platforms can be used for single-cell measurements, including but not limited to single-cell action potential or ion channel measurements. In some non-limiting examples, single-cell measurements may also include network measurements to characterize conduction velocities in cardiac cells or synaptic mappings in neurons.

[0058] The following applications are incorporated herein by reference in their entirety: U.S. Provisional Patent Application Serial No. 63 / 040,439, filed June 17, 2020, by Park et al.; U.S. Provisional Patent Application Serial No. 63 / 040,424, filed June 17, 2020, by Ham et al.; and U.S. Provisional Patent Application Serial No. 63 / 040,412, filed June 17, 2020, by Ham et al. Additionally, the following applications are incorporated herein by reference in their entirety: PCT patent application filed June 16, 2021, entitled “Systems and Methods for Patterning and Spatial Electrochemical Mapping of Cells”; and PCT patent application filed June 16, 2021, entitled “Apparatuses for Cell Mapping Via Impedance Measurements and Methods to Operate the Same”.

[0059] Several aspects of at least one embodiment of the invention have been described thus; it should be understood that various changes, modifications, and improvements will readily occur to those skilled in the art. Such changes, modifications, and improvements are intended to be part of this disclosure and are intended to be within the spirit and scope of the invention. Furthermore, while advantages of the invention have been pointed out, it should be understood that not every embodiment of the technology described herein will include every described advantage. Some embodiments may not implement any of the features described herein as advantageous, and in some cases, one or more of the described features may be implemented to achieve further embodiments. Therefore, the foregoing description and figures are by way of example only.

[0060] Various aspects of the present invention can be used individually, in combination, or in various arrangements not specifically discussed in the foregoing embodiments, and are therefore not limited to their application to the details and arrangements of the components set forth in the foregoing description or illustrated in the drawings. For example, aspects described in one embodiment can be combined in any way with aspects described in other embodiments.

[0061] Furthermore, the present invention can be implemented as the method already provided as an example. The actions performed as part of the method can be ordered in any suitable manner. Therefore, embodiments in which actions are performed in an order different from that shown in the illustrations can be constructed, which may include performing some actions simultaneously, even if these actions are shown as consecutive actions in the exemplary embodiments.

[0062] The use of sequential terms such as “first,” “second,” and “third” in claims to modify a claim element itself does not imply any priority, order, or temporal sequence of action of one claim element relative to another claim element, but is merely used as a label to distinguish one claim element with a specific name from another element with the same name (but using ordinal terms) to differentiate claim elements.

[0063] The terms “approximately” and “about” can be used to indicate within +20% of the target value in some embodiments, within ±10% of the target value in some embodiments, within ±5% of the target value in some embodiments, and even within ±2% of the target value in some embodiments. The terms “approximately” and “about” can include the target value.

Claims

1. A semiconductor device for use with a biochemical sensor including a multi-well array, said semiconductor device comprising: Chips; At least two marking regions are deployed within the wafer, each marking region having multiple circuit systems of the same design, wherein each marking region includes: At least one well circuit is configured to be electrically connected to the wells of the multi-well array, and The routing circuit is configured to route a first type of signal along a first direction from a first side of the marking area toward a second side of the marking area, and to route a second type of signal, including the output signal of the marking area, along a second direction different from the first direction from a third side of the marking area toward a fourth side of the marking area.

2. The semiconductor device of claim 1, wherein the at least two marked regions are electrically connected to each other.

3. The semiconductor device of claim 2, further comprising a plurality of intersecting line connections configured to place the at least two line regions in an electrically connected manner.

4. The semiconductor device of claim 3, wherein the at least two marking regions are deployed on a first surface of the wafer, the semiconductor device further comprising a redistribution layer RDL on the first surface, wherein at least a portion of the plurality of intersecting markings connects to include conductors deployed in the RDL layer.

5. The semiconductor device of claim 4, further comprising an interposer layer facing a second surface of the wafer opposite to the first surface.

6. The semiconductor device of claim 5, wherein the interposer is a printed circuit board (PCB).

7. The semiconductor device of claim 6, wherein the interposer includes a cavity, and wherein the wafer is mounted in the cavity.

8. The semiconductor device according to any one of claims 1-7, wherein the first type of signal is a digital signal and the second type of signal is an analog signal.

9. The semiconductor device of any one of claims 1-8, wherein the routing circuitry in the first marking region is configured to receive a signal of the first type from a second marking region adjacent to the first marking region along the first direction.

10. The semiconductor device of claim 9, wherein the routing circuitry in the first marking region is further configured to receive a signal of the second type from a third marking region adjacent to the first marking region along the second direction.

11. The semiconductor device of any one of claims 1-10, wherein the routing circuitry includes one or more shift registers configured to route signals of the first type.

12. The semiconductor device according to any one of claims 1-11, wherein the routing circuit comprises at least one digital bus and at least one analog bus.

13. The semiconductor device according to any one of claims 1-12, wherein the at least one well circuit is configured to be electrically connected to a plurality of electrodes arranged in an electrode array in the well.

14. The semiconductor device of claim 13, wherein the plurality of electrodes comprises at least 1,000 electrodes.

15. The semiconductor device of claim 14, wherein the plurality of electrodes comprises at least 4,000 electrodes.

16. The semiconductor device according to any one of claims 13-15, wherein each well circuit includes a plurality of peripheral circuits, each peripheral circuit including a stimulation circuit and a recording circuit.

17. The semiconductor device of claim 16, wherein the stimulation circuit includes a current injector.

18. The semiconductor device of any one of claims 16 or 17, further comprising one or more switches configured to selectively couple a subset of peripheral circuitry within the trap circuitry to a subset of electrodes within the electrode array.

19. The semiconductor device of any one of claims 1-18, wherein the semiconductor device is configured to be coupled below the multi-well array such that each well circuit is electrically connected to and deployed adjacent to a corresponding well in the multi-well array.

20. The semiconductor device according to any one of claims 1-19, wherein each marked region includes more than one well circuit.

21. The semiconductor device of claim 18, wherein the one or more switches are further configured to selectively couple a subset of peripheral circuitry to one or more optoelectronic components.

22. The semiconductor device of claim 21, wherein the one or more optoelectronic components include a light-emitting diode, a photodetector, or a combination thereof.

23. The semiconductor device of any one of claims 18 or 21, wherein the electrode of a subset of the electrodes is a reference electrode.

24. The semiconductor device of any one of claims 3-7, wherein each marked region has a rectangular shape, the sides of the rectangular shape being aligned with the first direction and the second direction.

25. The semiconductor device of any one of claims 13-18, wherein the at least two marking regions are an array of marking regions arranged in rows along the first direction and columns along the second direction, wherein adjacent marking regions in each row are connected by an array of intersecting marking regions arranged along the second direction, and wherein adjacent marking regions in each column are connected by an array of intersecting marking regions arranged along the first direction.

26. The semiconductor device of claim 25, wherein the semiconductor device is configured to be coupled below the multi-well array, such that each marked region is located below the corresponding well of the multi-well array.

27. The semiconductor device of claim 25 or 26, wherein each marked area has a width of at least 9 mm.

28. The semiconductor device according to any one of claims 25-27, wherein each marked area has a width of at least 18 mm.

29. The semiconductor device according to any one of claims 1-28, wherein the multi-well array has at least 96 wells.

30. The semiconductor device according to any one of claims 1-29, wherein the wafer has a lateral dimension equal to or greater than the maximum lateral extent of the multi-well array.

31. The semiconductor device according to any one of claims 1-30, wherein the wafer comprises silicon.

32. The semiconductor device of claim 31, wherein each of the marked regions is an integrated circuit comprising a complementary metal-oxide-semiconductor (CMOS) component.

33. A method of operating a semiconductor device to evaluate a biochemical sensor comprising a multi-well array, said semiconductor device comprising a wafer and at least two datum regions disposed within said wafer, each datum region having a plurality of circuit systems of the same design, wherein each datum region includes at least one well circuit and a routing circuit, said method comprising: The at least one well circuit is electrically connected to the well of the multi-well array; as well as Using the routing circuit, a first type of signal is routed along a first direction from the first side of the marking area to the second side of the marking area, and a second type of signal, including the output signal of the marking area, is routed along a second direction different from the first direction from the third side of the marking area to the fourth side of the marking area.

34. The method of claim 33, wherein the first type of signal is a digital signal and the second type of signal is an analog signal.

35. The method of any one of claim 33 or 34, wherein routing the first type of signal and the second type of signal comprises: Transmit the signal of the first type from the second marking area to the first marking area adjacent to the second marking area along the first direction; as well as The signal of the second type is transmitted from the third marking area to the first marking area, wherein the third marking area is adjacent to the first marking area along the second direction.

36. The method of any one of claims 33-35, wherein being electrically connected to the trap comprises: One or more stimuli are provided to cells deployed in the multi-well array to measure one or more properties of the cells, or a combination thereof.

37. The method of claim 36, wherein the one or more characteristics of the cell include: Impedance, adhesion, redox potential, action potential, conduction velocity, synaptic mapping, or a combination thereof.

38. The method of any one of claims 36 or 37, wherein the one or more stimuli comprise current or voltage.

39. The method of any one of claims 36-38, wherein each trap circuit includes a plurality of peripheral circuits, each peripheral circuit including a stimulation circuit and a recording circuit, and wherein being electrically connected to the trap further includes: Using one or more switches in the semiconductor device, a subset of the peripheral circuitry within the trap circuit is selectively coupled to a subset of the electrodes within the electrode array in the trap; Using a subset of the peripheral circuitry's stimulation circuitry, one or more stimuli are delivered to the cells via a subset of the electrodes; and One or more properties of the cell are measured via a subset of the electrodes using a recording circuit within a subset of the peripheral circuitry.

40. The method of claim 39, further comprising: Selectively couple optoelectronic components to peripheral circuits; The photoelectric component is used to emit light signals to or receive light signals from cells deployed in the multi-well array.

41. An apparatus for electro-evaluating biological samples, comprising: A plate having a multi-well array for holding the biological sample, each well of the multi-well array having multiple electrodes deployed therein; A wafer having a first surface facing a first side of the plate, the wafer comprising: An array of marking regions, each marking region having multiple circuit systems of the same design, wherein each marking region includes: At least one well circuit is configured to be electrically connected to electrodes in the wells of the multi-well array, and The routing circuit is configured to route a first type of signal along a first direction from a first side of the marking area toward a second side of the marking area, and to route a second type of signal, including a signal output from the marking area, along a second direction different from the first direction from a third side of the marking area toward a fourth side of the marking area; and A first substrate having a wafer attachment surface facing the wafer and opposite to the first surface, the first substrate including a plurality of conductors electrically connecting at least a portion of the marking region array to a plurality of pads disposed on a mounting surface of the first substrate opposite to the wafer attachment surface.

42. The apparatus of claim 41, wherein the first substrate is an interposer including a chamber, wherein the wafer attachment surface is disposed within the chamber, and wherein the second surface of the wafer is attached to the wafer attachment surface of the first substrate.

43. The apparatus of any one of claims 41 or 42, further comprising a cover coupled to a second side of the plate opposite the first side.

44. The apparatus of claim 43, wherein the cover includes a plurality of reference electrodes, each reference electrode extending into a corresponding well of the multi-well array.

45. The apparatus of claim 43 or 44, wherein the cover comprises a plurality of photodetectors, each photodetector facing a corresponding well of the multi-well array.

46. ​​The apparatus of any one of claims 41-45, further comprising a second substrate having a plurality of conductive structures disposed on a first surface facing a mounting surface of the first substrate, each conductive structure being electrically connected to a corresponding pad among the plurality of pads on the mounting surface of the first substrate.

47. The apparatus of claim 46, wherein the second substrate and the first substrate are magnetically coupled.

48. The apparatus of any one of claims 41-47, further comprising a housing surrounding the wafer and the plate on at least five sides.

49. The apparatus of any one of claims 41-48, wherein the biological sample comprises a plurality of single cells.

50. The apparatus of claim 49, wherein the plurality of electrodes within the trap are configured to be in internal electrical communication with the interior of a single cell deployed within the trap.

51. The apparatus of any one of claims 41-50, wherein the first type of signal is a digital signal and the second type of signal is an analog signal.

52. The apparatus of claim 51, wherein the routing circuit in the first marking region is configured to receive a first type of signal from a second marking region adjacent to the first marking region along the first direction, and the routing circuit in the first marking region is further configured to receive a second type of signal from a third marking region adjacent to the first marking region along the second direction.

53. The apparatus of any one of claims 41-52, wherein each trap circuit includes a plurality of peripheral circuits, each peripheral circuit including stimulation circuitry and recording circuitry, and the apparatus further includes one or more switches configured to selectively couple a subset of the peripheral circuitry within the trap circuitry to a subset of the electrodes within the plurality of electrodes.

54. The apparatus of any one of claims 41-53, wherein each well has an opening open toward the wafer, and wherein the plurality of electrodes comprises an array of conductors deployed on an insulating surface of the wafer.

Images