Chip internal voltage control method, device, equipment and storage medium

Abstract

The application provides a chip internal voltage control method, device, equipment and storage medium. The chip internal voltage control method comprises the following steps: obtaining a clock source signal of a target chip, and performing frequency division on the clock source signal to obtain a frequency division signal; inputting the frequency division signal into a delay unit of the target chip, and collecting a corresponding number of delay signal values at a corresponding clock edge based on the frequency division signal and preset delay configuration parameters of the delay unit; and controlling an internal output voltage of the target chip according to the corresponding number of delay signal values and the preset delay configuration parameters, so that the internal output voltage is stabilized in a preset range. The method can monitor the output voltage inside the chip, and adjust the output voltage when the output voltage fluctuates greatly, so that the chip can work continuously and stably.

Description

Technical Field

[0001] The present application belongs to the field of chip technology, and specifically relates to a chip internal voltage control method, device, equipment and storage medium. Background Art

[0002] With the development of computer technology, the application range of chips is becoming wider and wider, and the performance requirements of chips are also becoming higher and higher. For example, the working stability of chips is generally required to ensure that the voltage module of the chip can output a stable voltage to ensure stable operation of the chip.

[0003] However, most of the chips currently used will cause the voltage output by the voltage module inside the chip to change due to environmental (such as temperature) changes, which will cause the chip to malfunction and bring inevitable losses to users.

[0004] Therefore, how to control the output voltage inside the chip is a key issue that needs to be solved urgently to ensure the chip can operate stably. Summary of the Invention

[0005] The present application proposes a chip internal voltage control method, device, equipment and storage medium. The method can monitor the output voltage inside the chip and adjust it when the output voltage fluctuates greatly, so that the chip can operate continuously and stably.

[0006] The first embodiment of the present application provides a method for controlling internal voltage of a chip, including:

[0007] Obtaining a clock source signal of a target chip, and frequency-dividing the clock source signal to obtain a frequency-divided signal;

[0008] Inputting the frequency-divided signal into the delay unit of the target chip, and collecting a corresponding number of delay signal values ​​at corresponding clock edges based on the frequency-divided signal and preset delay configuration parameters of the delay unit;

[0009] According to the corresponding number of delay signal values ​​and the preset delay configuration parameters, the internal output voltage of the target chip is controlled so that the internal output voltage is stabilized within a preset range.

[0010] In some embodiments of the present application, collecting a corresponding number of delay signal values ​​at corresponding clock edges based on the frequency-divided signal and the preset delay configuration parameters of the delay unit includes:

[0011] Determining a target clock edge for collecting a corresponding number of delayed signals based on a relationship between the frequency-divided signal and the clock source signal;

[0012] Determining the number of delay gears of the delay unit based on the preset delay configuration parameters, and determining the number of delay gears as the target number of delay signals to be collected;

[0013] At the target time, the target number of delayed signal values ​​are collected.

[0014] In some embodiments of the present application, determining the target clock edge for acquiring a corresponding number of delayed signals based on the relationship between the frequency-divided signal and the clock source signal includes:

[0015] Determining a first frequency of the clock source signal and a second frequency of the frequency-divided signal, and calculating a ratio of the first frequency to the second frequency;

[0016] Based on the ratio, the rising edge or the falling edge of the clock source signal is determined as the target time for collecting the delayed signal.

[0017] In some embodiments of the present application, controlling the internal output voltage of the target chip according to the corresponding number of delay signal values ​​and the preset delay configuration parameter so that the internal output voltage is stable within a preset range includes:

[0018] Obtaining a delay threshold for each delay gear in the preset delay configuration parameters, wherein the delay threshold includes an upper delay limit value and a lower delay limit value;

[0019] Determining whether the internal output voltage of the target chip exceeds the preset range according to the corresponding number of delay signal values ​​and the delay threshold of the corresponding delay gear;

[0020] If so, the internal output voltage is adjusted so that the internal output voltage is stable within a preset range.

[0021] In some embodiments of the present application, determining whether the internal output voltage of the target chip exceeds the preset range based on the corresponding number of delay signal values ​​and the delay threshold of the corresponding delay gear includes:

[0022] Determining whether the corresponding number of delay signal values ​​meets a preset adjustment condition based on a relationship between the corresponding number of delay signal values ​​and a delay threshold value of a corresponding delay gear;

[0023] If so, it is determined whether the internal output voltage of the target chip exceeds the preset range.

[0024] In some embodiments of the present application, determining whether the corresponding number of delay signal values ​​satisfies a preset adjustment condition based on a relationship between the corresponding number of delay signal values ​​and a delay threshold of a corresponding delay gear includes:

[0025] Determine whether each delay signal value exceeds the delay threshold of the corresponding delay gear;

[0026] If so, it is determined that the corresponding number of delayed signal values ​​meet the preset adjustment condition.

[0027] In some embodiments of the present application, determining whether the corresponding number of delay signal values ​​satisfies a preset adjustment condition based on a relationship between the corresponding number of delay signal values ​​and a delay threshold of a corresponding delay gear includes:

[0028] Determining whether any of the corresponding number of delay signal values ​​exceeds a delay threshold of a corresponding delay gear;

[0029] If so, calculating the number of delay signal values ​​exceeding the delay threshold of the corresponding delay gear, and determining whether the number is greater than or equal to a preset threshold;

[0030] If so, it is determined that the corresponding number of delayed signal values ​​meet the preset adjustment condition.

[0031] In some embodiments of the present application, adjusting the internal output voltage so that the internal output voltage is stable within a preset range includes:

[0032] determining an adjustment direction of the internal output voltage;

[0033] Based on the adjustment direction, the configuration parameters of the power module of the target chip are adjusted to stabilize the internal output voltage within a preset range.

[0034] In some embodiments of the present application, determining the adjustment direction of the internal output voltage includes:

[0035] When the delay signal value is less than the delay lower limit of the corresponding delay gear, determining to adjust the internal output voltage upward;

[0036] When the delay signal value is greater than the delay upper limit of the corresponding delay gear, it is determined to adjust the internal output voltage downward.

[0037] An embodiment of a second aspect of the present application provides a chip internal voltage control device, including:

[0038] A frequency division module is used to obtain a clock source signal of a target chip and perform frequency division on the clock source signal to obtain a frequency division signal;

[0039] an acquisition module, configured to input the frequency-divided signal into the delay unit of the target chip, and acquire a corresponding number of delay signal values ​​at corresponding clock edges based on the frequency-divided signal and preset delay configuration parameters of the delay unit;

[0040] The control module is used to control the internal output voltage of the target chip according to the corresponding number of delay signal values ​​and the preset delay configuration parameters, so that the internal output voltage is stable within a preset range.

[0041] An embodiment of the third aspect of the present application provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps described in the first aspect when executing the computer program.

[0042] An embodiment of the fourth aspect of the present application provides a computer-readable storage medium having a computer program stored thereon, wherein the program is executed by a processor to implement the method described in the first aspect.

[0043] The technical solutions provided in the embodiments of this application have at least the following technical effects or advantages:

[0044] The chip internal voltage control method provided in an embodiment of the present application inserts a frequency-divided signal of a clock source signal into a delay unit of a target chip, thereby generating multiple delayed signals. Based on the frequency-divided signal and preset delay configuration parameters of the delay unit, multiple signal values ​​of the multiple delayed signals are collected at corresponding clock edges. Based on these multiple signal values ​​and the preset delay configuration parameters, the chip's internal output voltage can be monitored, thereby enabling timely detection and rapid adjustment of the chip's internal output voltage when the chip is operating abnormally. Furthermore, this method is independent of the chip system and does not affect the normal operation of the chip, making its application more flexible. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Various other advantages and benefits will become apparent to those skilled in the art upon reading the detailed description of the preferred embodiment below. The accompanying drawings are for illustration purposes only and are not to be considered as limiting the present application. Throughout the accompanying drawings, the same reference numerals are used to denote the same components.

[0046] In the attached figure:

[0047] Figure 1 A schematic flow chart of a chip internal voltage control method according to an embodiment of the present application is shown;

[0048] Figure 2 A schematic diagram of a clock source signal and its divided-by-two frequency signal in an embodiment of the present application is shown;

[0049] Figure 3 Schematic diagram showing the normal timing of the delay signal in an embodiment of the present application;

[0050] Figure 4 A schematic diagram showing the error timing of the delay signal in the embodiment of the present application is shown.

[0051] Figure 5 Schematic diagram of the process of step S3 in one embodiment of the present application is shown;

[0052] Figure 6 A schematic flow chart of another chip internal voltage control method provided in one embodiment of the present application is shown;

[0053] Figure 7 A schematic structural diagram of a chip internal voltage control device provided by an embodiment of the present application is shown;

[0054] Figure 8 A schematic structural diagram of an electronic device provided in one embodiment of the present application is shown;

[0055] Figure 9 A schematic diagram of a storage medium provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0056] The following describes exemplary embodiments of the present application in more detail with reference to the accompanying drawings. Although exemplary embodiments of the present application are shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the embodiments described herein. Instead, these embodiments are provided to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0057] It should be noted that, unless otherwise specified, the technical or scientific terms used in this application should have the common meanings understood by those skilled in the art to which this application belongs.

[0058] In existing related technologies, the internal output voltage of a chip is typically calibrated only during factory inspection. Therefore, if the chip experiences operational instability during use, the user must design a dedicated voltage regulation circuit based on their needs to dynamically adjust the internal output voltage of the chip. Currently, dynamic voltage regulation methods fall into two broad categories: one that uses analog circuits to ensure dynamic stability of the output voltage, and the other that uses digital circuits to control the configuration parameters of the analog circuits to achieve dynamic voltage changes. Regardless of the approach, the user must configure an additional regulation circuit, increasing the application cost of the chip. Furthermore, these regulation circuits are often only capable of adjustment and cannot monitor the internal output voltage of the chip. Adjustment is often performed only after the chip malfunctions. This lag in regulation inevitably results in losses due to voltage instability.

[0059] In order to solve the above problems, the embodiments of the present application propose a chip internal voltage control method, device, equipment and storage medium. The chip in this embodiment can be applied to any chip with an internal power module, which can be an analog chip or a digital chip, and this embodiment does not specifically limit this. The control method inserts the frequency-divided signal of the clock source signal into the delay unit of the target chip, thereby generating multiple delay signals, and then collects multiple signal values ​​of the multiple delay signals at the clock edge, and monitors the internal output voltage of the chip based on the multiple signal values, so that it can be discovered in time when the chip is not working normally, and the internal output voltage of the chip can be adjusted quickly. Moreover, this method can be independent of the chip system, will not affect the normal operation of the chip, and is more flexible in application.

[0060] Please refer to Figure 1 , is a flow chart of the chip internal voltage control method provided in an embodiment of the present application, such as Figure 1 As shown, the method includes the following steps:

[0061] Step S1: Acquire a clock source signal of a target chip, and perform frequency division on the clock source signal to obtain a frequency-divided signal.

[0062] The execution subject of this embodiment can be a control device that is independent of the target chip and is set separately. It can be integrated with the target chip on the same circuit board or be set on other devices, as long as the control device can connect to the target chip and obtain and modify the configuration parameters of the target chip.

[0063] The target chip can be any chip as long as the method can be applied to control the internal voltage. The clock source signal clk can be a square wave pulse signal, such as Figure 2 As shown, for a specific chip, the clock source signal has a fixed frequency and amplitude, and in this embodiment, it can be composed of alternating high-level signals and low-level signals. Dividing the clock source signal means reducing the frequency of the clock source signal, and specifically reducing it by an integer multiple. The frequency-divided signal is the signal obtained after reducing the frequency of the clock source signal. This embodiment takes the two-frequency-divided signal of the clock source signal as an example to provide a detailed description of the chip internal voltage control method provided in this embodiment. The two-frequency-divided signal clk_div2 of the clock source signal is also shown in FIG. Figure 2 As shown in .

[0064] It is understandable that the above-mentioned two-frequency divided signal is only one implementation of this embodiment, and this embodiment is not limited thereto. It can also be divided by other multiples as long as the delay signal value is subsequently collected at the corresponding clock edge of the clock source signal.

[0065] Step S2: input the divided frequency signal into the delay unit of the target chip, and based on the divided frequency signal and the preset delay configuration parameters of the delay unit, collect a corresponding number of delayed signal values ​​at corresponding clock edges.

[0066] Among them, the delay unit is a functional module configured when the chip leaves the factory. The preset delay configuration parameters of the delay unit may include the number of delay gears and the delay threshold corresponding to each delay gear. The delay threshold may include an upper delay limit value and a lower delay limit value. When the chip is working normally, when a signal is inserted into the delay unit, the signal value of each delayed signal generated by the delay unit should be within the corresponding delay threshold, that is, the delay signal value is between the upper delay limit value and the lower delay limit value. It can be understood that the delay threshold of each delay gear can be the same or different, and this embodiment can be set as needed.

[0067] like Figure 3 , which is a normal timing diagram of 16 delayed signals with different delays generated after the divided-by-two frequency signal of the clock source signal is inserted into a delay unit with 16 delay positions.

[0068] In some embodiments, based on the preset delay configuration parameters of the frequency-divided signal and the delay unit, when collecting a corresponding number of delayed signal values ​​at a corresponding clock edge, the target clock edge for collecting the corresponding number of delayed signals can be first determined based on the relationship between the frequency-divided signal and the clock source signal; then, the number of delay gears of the delay unit is determined based on the preset delay configuration parameters, and the number of delay gears is determined as the target number of delay signals to be collected; and the target number of delay signal values ​​are collected at the target time.

[0069] like Figure 3 As shown in the figure, after the divided-by-two signal of the clock source signal is inserted into the delay unit, when the divided-by-two signal is synchronized with the clock source signal, the rising edge of the clock source signal corresponds to the rising or falling edge of the divided-by-two signal, and the falling edge of the clock source signal is located in the middle of the half-cycle of the divided-by-two signal. When the internal output voltage of the chip is unstable, the delay of the delay signal will exceed the preset threshold. At this time, at the rising or falling edge of the divided-by-two signal, the signal value of the delay signal whose delay exceeds the preset threshold will change significantly, such as from a high level to a low level, as shown in the figure. Figure 4 As shown in Figure 2. The falling edge of the clock source signal corresponds to the middle of a half-cycle of the divided-by-two signal. Due to the delay of the delay signal, its normal timing may also correspond to a wider threshold range. Therefore, when the chip is operating unstably, the delay signal value may also be within the normal threshold range. Therefore, the delay signal value can be collected on the rising edge of the clock source signal, so that the acquired delay signal value can accurately reflect the changes in the chip's internal output voltage.

[0070] In addition, the preset delay configuration parameters may not include the number of delay gears of the delay unit. The target number of delay signals to be collected can be determined based on the number of bits of the delay upper limit and / or the delay lower limit. Specifically, the number of bits of the delay upper limit and / or the delay lower limit can be obtained first; then the power operation result with 2 as the base and the number of bits as the exponent is calculated, and the power operation result is determined as the target number.

[0071] Specifically, based on the relationship between the frequency-divided signal and the clock source signal, the step of determining the target clock edge for collecting a corresponding number of delayed signals may include the following processing: determining the first frequency of the clock source signal and the second frequency of the frequency-divided signal, and calculating the ratio of the first frequency to the second frequency; based on the ratio, determining the rising edge or falling edge of the clock source signal as the target time for collecting the delayed signal.

[0072] Based on the principle of collecting delay signals in the case of a two-way frequency division, regardless of the frequency division ratio of the divided signal, the delay signal can be collected on the rising or falling edge of the divided signal. Therefore, based on the ratio of the clock source signal frequency to the divided signal frequency, the rising / falling edge of the clock source signal corresponding to the same rising or falling edge of the divided signal can be determined. By collecting the delay signal at this rising / falling edge, a delay signal value that accurately reflects the changes in the chip's internal output voltage can be obtained, thereby accurately monitoring the chip's internal output voltage in real time.

[0073] Step S3 , controlling the internal output voltage of the target chip according to the corresponding number of delay signal values ​​and the preset delay configuration parameters, so that the internal output voltage is stabilized within a preset range.

[0074] The preset range may be any range of the internal output voltage of the chip, and may be set according to actual conditions. This embodiment does not impose any specific limitation on this.

[0075] In practical applications, the internal output voltage of the chip can be judged whether it is stably output based on the corresponding number of delay signal values ​​and the preset delay configuration parameters, so as to perform real-time detection of the internal output voltage of the chip. When an abnormal internal output voltage is found, the internal output voltage of the chip can be adjusted in time to stabilize the internal output voltage within the preset range.

[0076] In other embodiments, Figure 5 As shown, the above step S3 may include the following steps:

[0077] Step S31, obtaining the delay threshold of each delay gear in the preset delay configuration parameters;

[0078] Step S32, determining whether the internal output voltage of the target chip exceeds a preset range based on the corresponding number of delay signal values ​​and the delay threshold of the corresponding delay gear;

[0079] In step S33 , if yes, the internal output voltage is adjusted to stabilize the internal output voltage within a preset range.

[0080] In this embodiment, for the two-frequency signal, the 16 delay signals with different delays generated may have different delay signal values ​​at the same time, but each has a corresponding delay threshold (including an upper delay limit and a lower delay limit). When the collected delay signal value exceeds the delay threshold of the corresponding delay gear, it may be caused by a change in the internal output voltage of the chip. For example, if the internal output voltage increases, the delay signal may change faster, causing the collected delay signal value to be greater than the upper delay limit; or if the internal output voltage decreases, the delay signal may change slower, causing the collected delay signal value to be less than the lower delay limit. Therefore, conversely, as long as the relationship between the delay signal value and the delay threshold of the corresponding delay gear is used, it can be determined whether the internal output voltage of the target chip exceeds the preset range, thereby accurately monitoring the internal output voltage of the chip. If the internal output voltage exceeds the preset range, the internal output voltage is adjusted in a timely manner to stabilize the internal output voltage within the preset range, thereby ensuring that the chip can operate normally.

[0081] Furthermore, the above step S32 may include the following processing: based on the relationship between the corresponding number of delay signal values ​​and the delay threshold of the corresponding delay gear, determine whether the corresponding number of delay signal values ​​meet the preset adjustment conditions; if so, determine whether the internal output voltage of the target chip exceeds the preset range.

[0082] Based on the above description, it can be seen that when the relationship between each delay signal value and the delay threshold of the corresponding delay gear meets certain conditions, it can be determined whether the internal output voltage of the target chip exceeds a preset range. Therefore, this condition parameter can be pre-configured in the control device. When the user uses the chip, simply activate the control device and, based on the relationship between each delay signal value and the delay threshold of the corresponding delay gear, the user can determine in real time whether the internal output voltage of the target chip has changed and whether the chip is operating normally.

[0083] In some embodiments, when a slight change in the internal output voltage significantly impacts chip operation, the preset adjustment condition may be such that, as long as one delayed signal value exceeds the corresponding delay threshold, a determination is made as to whether a corresponding number of delayed signal values ​​satisfy the preset adjustment condition. Therefore, the above-mentioned step of determining whether a corresponding number of delayed signal values ​​satisfy the preset adjustment condition based on the relationship between the corresponding number of delayed signal values ​​and the delay threshold of the corresponding delay gear may include the following processing: determining whether each delayed signal value exceeds the delay threshold of the corresponding delay gear; if so, determining that the corresponding number of delayed signal values ​​satisfy the preset adjustment condition. In this way, it is possible to quickly determine whether the internal output voltage of the target chip exceeds the preset range, and the output value of the internal output voltage can also be made more accurate.

[0084] In other embodiments, when a slight change in the internal output voltage has little effect on the operation of the chip, the preset adjustment condition can also be that a plurality of delay signal values ​​exceed the corresponding delay threshold value before determining whether the corresponding number of delay signal values ​​meet the preset adjustment condition. Therefore, the above-mentioned step of determining whether the corresponding number of delay signal values ​​meet the preset adjustment condition based on the relationship between the corresponding number of delay signal values ​​and the delay threshold value of the corresponding delay gear can also include the following steps: determining whether there is a delay signal value that exceeds the delay threshold value of the corresponding delay gear among the corresponding number of delay signal values; if so, calculating the number of delay signal values ​​that exceed the delay threshold value of the corresponding delay gear, and determining whether the number is greater than or equal to the preset threshold value; if so, determining that the corresponding number of delay signal values ​​meet the preset adjustment condition. In this way, it is possible to quickly determine whether the internal output voltage of the target chip exceeds the preset range, and it is also possible to save some unnecessary adjustments, which can save resources to a certain extent.

[0085] In other embodiments, step S33 may include the following: first determining the adjustment direction of the internal output voltage; then, based on the adjustment direction, adjusting the configuration parameters of the power module of the target chip to adjust the internal output voltage so that the internal output voltage is stabilized within a preset range. In this way, after determining the voltage adjustment direction, the internal output voltage of the chip can be quickly adjusted so that the internal output voltage is stabilized within the preset range.

[0086] Furthermore, the step size for adjusting the internal output voltage can be set each time. After adjusting the step size, a certain amount of time (determined according to the specific situation) can be waited to allow the chip's power module to output a stable voltage. Then, according to steps S1 to S3 above, the chip's internal output voltage is continuously monitored and the configuration parameters of the power module are adjusted until the output voltage of the power module meets the requirements.

[0087] Specifically, when determining the adjustment direction of the internal output voltage, if the delay signal value is less than the delay lower limit of the corresponding delay gear, it means that the delay signal changes slowly and the voltage output by the power module may be small. In this case, the internal output voltage can be adjusted upward. If the delay signal value is greater than the delay upper limit of the corresponding delay gear, it means that the delay signal changes quickly and the voltage output by the power module may be large. In this case, the internal output voltage can be adjusted downward.

[0088] The following is combined with Figure 3 -Attached Figure 4 , and attached Figure 6 , taking the binary frequency signal as an example, the voltage control process of this embodiment is described in detail. First, before executing the control method, the delay configuration parameters of the chip can be set. For the delay signal of each gear, two 4-bit parameters can be configured first, representing the upper and lower limits of the delay gear, namely the upper limit value dly_gate_up and the lower limit value dly_gate_down. Then, as Figure 6 As shown, you can follow the following process:

[0089] 1) The control device is enabled and starts working, dividing the clock source signal by 2 and inserting the divided signal into the delay unit to form 16 delayed signals with different delays.

[0090] 2) On the rising edge of the clock source signal clk (such as Figure 3 and 4 As shown in FIG, 16 signal values ​​of the delayed signals are collected, and it is determined whether each signal value is between dly_gate_up and dly_gate_down.

[0091] 3) When the collected signal value is not between dly_gate_up and dly_gate_down, the control device generates an interrupt and determines whether to adjust the voltage upward or downward based on the current collected signal value and the above configuration parameters, and makes corresponding adjustment strategies.

[0092] Specifically, when judging whether the collected signal value is between the configured values ​​dly_gate_up and dly_gate_down to meet expectations, assuming that a set of collected data is the variable sample_rslt, and the upper and lower limits of the configuration gear are the variables dly_gate_up and dly_gate_down, the corresponding judgment is as follows:

[0093] Conditions for adjusting the gear upwards (meet any one of the following conditions):

[0094] case(sample_rslt)

[0095] 16’bxxxx_xxxx_xxxx_xxx1:dly_gate_down>4’h0

[0096] 16’bxxxx_xxxx_xxxx_xx10:dly_gate_down>4’h1

[0097] 16’bxxxx_xxxx_xxxx_x100:dly_gate_down>4’h2

[0098] 16’bxxxx_xxxx_xxxx_1000:dly_gate_down>4’h3

[0099] 16’bxxxx_xxxx_xxx1_0000:dly_gate_down>4’h4

[0100] 16’bxxxx_xxxx_xx10_0000:dly_gate_down>4’h5

[0101] 16’bxxxx_xxxx_x100_0000:dly_gate_down>4’h6

[0102] 16’bxxxx_xxxx_1000_0000:dly_gate_down>4’h7

[0103] 16’bxxxx_xxx1_0000_0000:dly_gate_down>4’h8

[0104] 16’bxxxx_xx10_0000_0000:dly_gate_down>4’h9

[0105] 16’bxxxx_x100_0000_0000:dly_gate_down>4’ha

[0106] 16’bxxxx_1000_0000_0000:dly_gate_down>4’hb

[0107] 16’bxxx1_0000_0000_0000:dly_gate_down>4’hc

[0108] 16’bxx10_0000_0000_0000:dly_gate_down>4’hd

[0109] 16’bx100_0000_0000_0000:dly_gate_down>4’he

[0110] Conditions for adjusting the gear downward (meet any one of the following conditions):

[0111] case(sample_rslt)

[0112] 16'bxxxx_xxxx_xxxx_xxx1:dly_gate_up<4'h0

[0113] 16'bxxxx_xxxx_xxxx_xx10:dly_gate_up<4'h1

[0114] 16'bxxxx_xxxx_xxxx_x100:dly_gate_up<4'h2

[0115] 16'bxxxx_xxxx_xxxx_1000:dly_gate_up<4'h3

[0116] 16'bxxxx_xxxx_xxx1_0000:dly_gate_up<4'h4

[0117] 16'bxxxx_xxxx_xx10_0000:dly_gate_up<4'h5

[0118] 16'bxxxx_xxxx_x100_0000:dly_gate_up<4'h6

[0119] 16'bxxxx_xxxx_1000_0000:dly_gate_up<4'h7

[0120] 16'bxxxx_xxx1_0000_0000:dly_gate_up<4'h8

[0121] 16'bxxxx_xx10_0000_0000:dly_gate_up<4'h9

[0122] 16'bxxxx_x100_0000_0000:dly_gate_up<4'ha

[0123] 16'bxxxx_1000_0000_0000:dly_gate_up<4'hb

[0124] 16'bxxx1_0000_0000_0000:dly_gate_up<4'hc

[0125] 16'bxx10_0000_0000_0000:dly_gate_up<4'hd

[0126] 16'bx100_0000_0000_0000:dly_gate_up<4'he

[0127] 16'b1000_0000_0000_0000:dly_gate_up<4'hf

[0128] 4'h0-4'hf represent the 16 collected signal values, each of which is 4-bit hexadecimal data. 16'bxxxx_xxxx_xxxx_xxx1-16'b1000_0000_0000_0000 represent the 16 delayed signals, each of which is 16-bit binary data. 16'bxxxx_xxxx_xxxx_xxx1:dly_gate_down>4'h0 indicates that the collected signal value 4'h0 of the delayed signal 16'bxxxx_xxxx_xxxx_xxx1 is less than the delay lower limit dly_gate_down of the delayed signal 16'bxxxx_xxxx_xxxx_xxx1.

[0129] 4) Wait for a certain period of time (depending on the specific situation) to allow the power module to output a stable voltage again.

[0130] 5) Continue to monitor the internal output voltage of the chip and adjust the power module gear in time until the requirements are met.

[0131] In summary, the chip internal voltage control method of this embodiment inserts the frequency-divided signal of the clock source signal into the delay unit of the target chip, thereby generating multiple delayed signals. Based on the frequency-divided signal and the preset delay configuration parameters of the delay unit, multiple signal values ​​of the multiple delayed signals are collected at corresponding clock edges. Based on these multiple signal values ​​and the preset delay configuration parameters, the chip's internal output voltage can be monitored. This allows for timely detection of abnormal chip operation and rapid adjustment of the chip's internal output voltage. Furthermore, this method is independent of the chip system and does not affect the normal operation of the chip, making its application more flexible.

[0132] Based on the same concept as the above chip internal voltage control method, this embodiment also provides a chip internal voltage control device, such as Figure 7 As shown, the control device includes:

[0133] The frequency division module is used to obtain the clock source signal of the target chip and divide the clock source signal to obtain a divided signal;

[0134] An acquisition module is used to input the frequency-divided signal into the delay unit of the target chip, and based on the frequency-divided signal and the preset delay configuration parameters of the delay unit, acquire a corresponding number of delay signal values ​​at the corresponding clock edge;

[0135] The control module is used to control the internal output voltage of the target chip according to the corresponding number of delay signal values ​​and the preset delay configuration parameters, so that the internal output voltage is stable within a preset range.

[0136] The chip internal voltage control device provided in this embodiment is based on the same concept as the above-mentioned chip internal voltage control method, so it can at least achieve the above-mentioned beneficial effects, and any of the above-mentioned implementation methods can be applied to the chip internal voltage control device provided in this embodiment, which will not be repeated here.

[0137] The present application also provides an electronic device to implement the above chip internal voltage control method. Figure 8 , which shows a schematic diagram of an electrical device provided by some embodiments of the present application. Figure 8 As shown, the electrical device 40 includes: a processor 400, a memory 401, a bus 402 and a communication interface 403. The processor 400, the communication interface 403 and the memory 401 are connected via the bus 402; the memory 401 stores a computer program that can be run on the processor 400, and when the processor 400 runs the computer program, it executes the chip internal voltage control method provided in any of the aforementioned embodiments of the present application.

[0138] The memory 401 may include high-speed random access memory (RAM) and may also include non-volatile memory, such as at least one disk storage. The communication connection between the device network element and at least one other network element is achieved through at least one communication interface 403 (which may be wired or wireless), and may use the Internet, a wide area network, a local area network, a metropolitan area network, etc.

[0139] Bus 402 may be an ISA bus, a PCI bus, or an EISA bus. Buses may be classified as address buses, data buses, and control buses. Memory 401 is used to store programs, and processor 400 executes the programs upon receiving execution instructions. The chip internal voltage control method disclosed in any of the aforementioned embodiments of the present application may be applied to processor 400 or implemented by processor 400.

[0140] The processor 400 may be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method can be completed by hardware integrated logic circuits in the processor 400 or by software instructions. The above processor 400 may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it may also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), an off-the-shelf field programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the various methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor may be a microprocessor or any conventional processor. The steps of the method disclosed in conjunction with the embodiments of this application can be directly implemented and executed by a hardware decoding processor, or by a combination of hardware and software modules in the decoding processor. The software module can be located in a storage medium mature in the art, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, etc. The storage medium is located in the memory 401 , and the processor 400 reads the information in the memory 401 and completes the steps of the above method in combination with its hardware.

[0141] The electrical equipment provided in the embodiment of the present application and the chip internal voltage control method provided in the embodiment of the present application are based on the same inventive concept and have the same beneficial effects as the methods adopted, operated or implemented therein.

[0142] The present application also provides a computer-readable storage medium corresponding to the chip internal voltage control method provided in the above embodiment. Figure 9 The computer-readable storage medium shown is a CD 30 on which a computer program (ie, a program product) is stored. When the computer program is run by a processor, the chip internal voltage control method provided by any of the aforementioned embodiments will be executed.

[0143] It should be noted that examples of computer-readable storage media may also include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other optical or magnetic storage media, which are not listed here one by one.

[0144] The computer-readable storage medium provided in the above-mentioned embodiments of the present application and the chip internal voltage control method provided in the embodiments of the present application are based on the same inventive concept and have the same beneficial effects as the methods adopted, run or implemented by the application programs stored therein.

[0145] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some or all of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application, and they should all be included in the scope of the claims and specification of the present application. In particular, as long as there is no structural conflict, the various technical features mentioned in the various embodiments can be combined in any way. The present application is not limited to the specific embodiments disclosed herein, but includes all technical solutions that fall within the scope of the claims.

Claims

1. A chip internal voltage control method, characterized in that: include: Obtaining a clock source signal of a target chip, and frequency-dividing the clock source signal to obtain a frequency-divided signal; Inputting the frequency-divided signal into the delay unit of the target chip, and collecting a corresponding number of delay signal values ​​at corresponding clock edges based on the frequency-divided signal and preset delay configuration parameters of the delay unit; controlling an internal output voltage of the target chip according to the corresponding number of delay signal values ​​and the preset delay configuration parameter, so that the internal output voltage is stabilized within a preset range; It includes: Obtaining a delay threshold for each delay gear in the preset delay configuration parameters, wherein the delay threshold includes an upper delay limit value and a lower delay limit value; Determining whether the internal output voltage of the target chip exceeds the preset range according to the corresponding number of delay signal values ​​and the delay threshold of the corresponding delay gear; If so, the internal output voltage is adjusted so that the internal output voltage is stable within a preset range.

2. The method according to claim 1, characterized in that The collecting a corresponding number of delay signal values ​​at corresponding clock edges based on the frequency-divided signal and the preset delay configuration parameters of the delay unit includes: Determining a target clock edge for collecting a corresponding number of delayed signals based on a relationship between the frequency-divided signal and the clock source signal; Determining the number of delay gears of the delay unit based on the preset delay configuration parameters, and determining the number of delay gears as the target number of delay signals to be collected; At a target time, the target number of delayed signal values ​​are collected.

3. The method according to claim 2, characterized in that The determining, based on the relationship between the frequency-divided signal and the clock source signal, a target clock edge for collecting a corresponding number of delayed signals comprises: Determining a first frequency of the clock source signal and a second frequency of the frequency-divided signal, and calculating a ratio of the first frequency to the second frequency; Based on the ratio, the rising edge or the falling edge of the clock source signal is determined as the target time for collecting the delayed signal.

4. The method according to claim 1, wherein The determining, based on the corresponding number of delay signal values ​​and the delay threshold of the corresponding delay gear, whether the internal output voltage of the target chip exceeds the preset range includes: Determining whether the corresponding number of delay signal values ​​meets a preset adjustment condition based on a relationship between the corresponding number of delay signal values ​​and a delay threshold value of a corresponding delay gear; If so, it is determined whether the internal output voltage of the target chip exceeds the preset range.

5. The method according to claim 4, characterized in that The determining whether the corresponding number of delay signal values ​​satisfies a preset adjustment condition based on a relationship between the corresponding number of delay signal values ​​and the delay threshold of the corresponding delay gear includes: Determine whether each delay signal value exceeds the delay threshold of the corresponding delay gear; If so, it is determined that the corresponding number of delayed signal values ​​meet the preset adjustment condition.

6. The method according to claim 4, characterized in that The determining whether the corresponding number of delay signal values ​​satisfies a preset adjustment condition based on a relationship between the corresponding number of delay signal values ​​and the delay threshold of the corresponding delay gear includes: Determining whether any of the corresponding number of delay signal values ​​exceeds a delay threshold of a corresponding delay gear; If so, calculating the number of delay signal values ​​exceeding the delay threshold of the corresponding delay gear, and determining whether the number is greater than or equal to a preset threshold; If so, it is determined that the corresponding number of delayed signal values ​​meet the preset adjustment condition.

7. The method according to claim 1, characterized in that The adjusting the internal output voltage so that the internal output voltage is stable within a preset range includes: determining an adjustment direction of the internal output voltage; Based on the adjustment direction, the configuration parameters of the power module of the target chip are adjusted to stabilize the internal output voltage within a preset range.

8. The method according to claim 7, characterized in that The determining the adjustment direction of the internal output voltage includes: When the delay signal value is less than the delay lower limit of the corresponding delay gear, determining to adjust the internal output voltage upward; When the delay signal value is greater than the delay upper limit of the corresponding delay gear, it is determined to adjust the internal output voltage downward.

9. A chip internal voltage control device, characterized in that: include: A frequency division module is used to obtain a clock source signal of a target chip and perform frequency division on the clock source signal to obtain a frequency division signal; an acquisition module, configured to input the frequency-divided signal into the delay unit of the target chip, and acquire a corresponding number of delay signal values ​​at corresponding clock edges based on the frequency-divided signal and preset delay configuration parameters of the delay unit; a control module, configured to control an internal output voltage of the target chip according to the corresponding number of delay signal values ​​and the preset delay configuration parameter, so that the internal output voltage is stabilized within a preset range; It includes: obtaining the delay threshold of each delay gear in the preset delay configuration parameters, the delay threshold including the delay upper limit value and the delay lower limit value; determining whether the internal output voltage of the target chip exceeds the preset range based on the corresponding number of delay signal values ​​and the delay threshold of the corresponding delay gear; if so, adjusting the internal output voltage so that the internal output voltage is stable within the preset range.

10. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein: When the processor executes the computer program, the method according to any one of claims 1 to 8 is implemented.

11. A computer-readable storage medium having a computer program stored thereon, characterized in that: The program is executed by a processor to implement the method according to any one of claims 1 to 8.

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