Multi-bit quantization method for memory using error correction code
By combining multi-bit quantization and error correction codes, the problem of low read margin in the quantization decision circuit is solved, the read accuracy is improved and the decoding complexity is reduced, realizing the advantages of low cost and low power consumption of the memory.
Patent Information
- Application Number
- CN202310082543.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-01-29
- Publication Date
- 2026-01-27
- Estimated Expiration
- 2043-01-29
AI Technical Summary
In the existing technology, the read margin of the quantization decision circuit is low, which leads to a low read accuracy of the error correction code encoding and decoding scheme and a high decoding computation complexity. Especially when the read margin of the memory unit is extremely low, the error correction code decoding operation cannot be effectively implemented. In addition, the circuit area and power consumption of the high-precision analog-to-digital converter are large, which affects the low cost and low power consumption advantages of the memory.
A multi-bit quantization method is adopted, which generates a multi-bit quantization result by comparing the analog output value with multiple resistance quantization decision thresholds, and then uses error correction codes to decode it to determine the softness and resistance quantization decision thresholds. Combined with a sensitive amplifier, multi-level quantization decision is performed to optimize the channel model, thereby improving read accuracy and reducing decoding complexity.
It improves the read accuracy of the error correction code encoding and decoding scheme, reduces the computational complexity of decoding, reduces circuit area and power consumption, and enhances the low cost and low power consumption advantages of memory, especially in the fact that error correction code decoding can still be effectively implemented under low read margin conditions.
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Abstract
Description
Technical Field
[0001] This application relates to the field of storage device technology, and more specifically, to a multi-bit quantization method for a memory employing error-correcting codes. Background Technology
[0002] Memory, such as memory based on magnetic tunnel junction devices, memory based on resistive switching materials, memory based on ferroelectric capacitor devices, and memory based on amorphous oxide thin film transistor devices, uses arrays based on memory device cells to store data, saving the data in a certain form, such as charge, resistive state, or magnetic state, representing the information stored in the cell.
[0003] Memory is an electronic device that may encounter errors during data writing or reading. These errors mainly include write errors, read interference errors, and read decision errors. Error correction codes (ECC) and sensitive amplifiers are commonly used to reduce the error rate.
[0004] Error-correcting code (ECC) technology is one of the important methods for solving memory reliability problems. Currently, ECC encoding schemes applied in memory include single-error-correcting Hamming codes, Reed-Solomon (BCH) codes that can correct multiple bit errors, low-density parity-check (LDPC) codes, and polar codes, which can fully leverage the read / write advantages of memory and effectively reduce implementation complexity and overhead. When obtaining the discrete values of the read output, ECC decoding (or "decoding") is also required to detect or correct output data errors.
[0005] A sense amplifier is an important component of a memory. Its main function is to amplify the small signals generated during the memory reading process, thereby distinguishing the data stored in the memory and completing the reading operation.
[0006] The read margin of the decision circuit is the difference between the analog values of current or voltage generated by the sensitive amplifier when it senses the memory cell and the decision threshold within the decision threshold region.
[0007] In the channel model analysis of memory, it is necessary to establish a channel model based on the read and write error rate of its basic units. The channel model is a prerequisite for channel coding and quantization design schemes, and it is very important to design a channel quantizer suitable for memory.
[0008] Quantization refers to the process of sampling a continuous signal into a discrete signal. In this scheme, quantization refers to converting analog circuit signals into digital logic signals for use in ECC decoding operations.
[0009] For the error correction performance of a given decision threshold in a channel model, it is usually derived by calculating the finite-length performance bound (PPVB) values of maximum mutual information (MMI), maximum cutoff frequency (MCR), and minimum mean square error.
[0010] Currently, existing technologies have at least the following problems:
[0011] When the read margin of the quantization decision circuit is low, the read accuracy of the error correction code encoding / decoding scheme based on a one-bit quantization circuit is low, and the required decoding computation complexity is high. When the read margin of the object storage unit is extremely low (<3σ0), the output of the quantization decision circuit cannot be used to implement error correction code decoding computation. Quantizers based on information theory require high-precision analog-to-digital converters (ADCs) as quantization schemes, which not only result in large circuit area and power consumption overhead and poor robustness, but also fail to leverage the low cost and low power consumption advantages of memory. Summary of the Invention
[0012] In some examples, the analog output value is compared with multiple resistance quantization decision thresholds to generate a multi-bit quantization result, and then a set of discrete values is output. The method further includes:
[0013] The stored data is obtained by decoding the multi-bit quantization result using the error correction code.
[0014] In some examples, the decision thresholds include a soft quantization decision threshold and a resistance quantization decision threshold; before comparing the analog output value with multiple resistance quantization decision thresholds to generate a multi-bit quantization result, the method further includes determining the soft quantization decision threshold and determining the resistance quantization decision threshold. The comparison operation is performed by a quantization decision circuit that includes a sensitive amplifier.
[0015] In some examples, the number of discrete values is equal to or greater than the power of the number of digits in the radix of the encoding scheme determined by the ECC.
[0016] In some examples, determining the soft metric decision threshold includes:
[0017] Based on the characteristics of write errors, read interference errors, and read decision errors of the resistive storage devices, a corresponding cascaded channel model is determined;
[0018] After obtaining the cascaded channel model, the mean and variance of the high and low resistances of the resistive storage device are determined, and the write error rate of the resistive storage device is determined.
[0019] The error correction performance judgment method based on the maximum mutual information of channel capacity, or the maximum cutoff frequency, or the minimum mean square error finite-length performance boundary, within a specified range of parameters such as temperature, or tunnel magnetoresistance ratio (TMR), or resistance fluctuation of the storage device, or operating voltage, uses dynamic programming algorithm or differential evolution algorithm to find the optimal boundary of error correction performance value in the cascaded channel model, and determines the soft metric decision threshold set.
[0020] In some examples, determining the resistance quantization decision threshold includes:
[0021] The set of candidate resistor quantization decision thresholds is determined based on a set of reference cells that use resistive storage devices with the same parameters and dimensions as the storage array.
[0022] Based on the selected error correction code, the resistance quantization decision threshold is determined from the candidate resistance quantization decision threshold set by a set of soft metric decision thresholds;
[0023] The number of determined resistance quantization decision thresholds is equal to the number of softness decision thresholds. In some examples, the error correction code is a polar coordinate code, and encoding the stored data with the error correction code and storing it in memory includes:
[0024] The stored data is encoded using polar coordinates and then placed into the memory.
[0025] In the technical solution provided by the embodiments of this application, a multi-bit quantization method for a memory employing error-correcting codes is disclosed. The method includes: receiving stored data; encoding the stored data using error-correcting codes and storing it in a memory; reading the analog output value of the stored data in the memory; and comparing the analog output value with multiple resistive quantization decision thresholds to generate a multi-bit quantization result. The comparison with multiple resistive quantization decision thresholds yields a multi-bit quantization result, which has a lower error rate than single-bit quantization, thus improving accuracy. The comparison operation is performed by a quantization decision circuit, which includes a sensitive amplifier. When the read margin of the quantization decision circuit is low, compared with an error-correcting code encoding / decoding scheme based on a single-bit quantization circuit, the multi-bit quantization method can provide a better read accuracy for the error-correcting code encoding / decoding scheme and requires lower decoding computational complexity.
[0026] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description
[0027] Figure 1 This is a schematic diagram illustrating a multi-bit quantization method for a memory employing error-correcting codes, as shown in an exemplary embodiment of this application.
[0028] Figure 2 This is a schematic diagram of a write error channel model illustrated in an exemplary embodiment of this application.
[0029] Figure 3 This is a schematic diagram of a read interference error channel model, which is an exemplary embodiment of this application.
[0030] Figure 4 This is a schematic diagram of a read decision error channel model, which is an exemplary embodiment of this application.
[0031] Figure 5 This is a schematic diagram of a cascaded channel model shown in an exemplary embodiment of this application.
[0032] Figure 6 This is an exemplary embodiment of the present application illustrating a combination of seven resistor networks.
[0033] Figure 7 This is an exemplary embodiment of the present application, showing a comparison of the resistance values of the decision thresholds of seven resistor networks with those of three soft-measure decision thresholds.
[0034] Figure 8 This is a schematic diagram illustrating the readout margin range of a full margin sensitive amplifier, as shown in an exemplary embodiment of this application. Figure 9 This is an exemplary embodiment of the present application, illustrating a comparison of read decision errors between a resistor network decision threshold and a soft-metric decision threshold.
[0035] Figure 10 This is an exemplary embodiment of the present application, showing an error comparison diagram of a resistor network decision threshold and a soft-metric decision threshold after ECC decoding.
[0036] Figure 11 This is an exemplary embodiment of the present application illustrating a simulation comparison diagram of one-bit quantization and two-bit quantization. Detailed Implementation
[0037] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings denote the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of this application as detailed in the appended claims.
[0038] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities can be implemented in software, in one or more hardware modules or integrated circuits, or in different network and / or processor devices and / or microcontroller devices.
[0039] The flowcharts shown in the accompanying drawings are merely illustrative and do not necessarily include all content and operations / steps, nor do they necessarily have to be performed in the described order. For example, some operations / steps can be broken down, while others can be combined or partially combined; therefore, the actual execution order may change depending on the specific circumstances.
[0040] It should also be noted that "multiple" as mentioned in this application refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.
[0041] like Figure 1 As shown, Figure 1 This application illustrates a multi-bit quantization method for a memory employing error-correcting codes, as shown in one embodiment. The multi-bit quantization method for the memory employing error-correcting codes includes:
[0042] S101. Receive stored data and encode the stored data with error correction code and put it into the memory;
[0043] S102. Read the analog output value of the stored data in the memory;
[0044] S103. The analog output value is compared with multiple resistance quantization decision thresholds to generate a multi-bit quantization result and then a set of discrete values is output.
[0045] The method further includes comparing the simulated output value with multiple resistance quantization decision thresholds to generate a multi-bit quantization result and then outputting a set of discrete values.
[0046] The number of discrete values is determined based on the algorithm for selecting the error correction code, and the output is determined accordingly.
[0047] The output discrete value is decoded using the error correction code to obtain the stored data.
[0048] In some examples, before comparing the analog output value with multiple resistance quantization decision thresholds to generate a multi-bit quantization result, the method further includes:
[0049] The resistance quantization decision threshold is determined based on the selected error correction code.
[0050] In some examples, the resistance quantization decision threshold is determined based on a selected error correction code, and the method further includes:
[0051] Based on the selected error correction code, determine the number of resistance quantization decision thresholds;
[0052] The set of candidate resistor quantization decision thresholds is determined based on a set of reference cells that use resistive storage devices with the same parameters and dimensions as the storage array.
[0053] Based on the selected error correction code, the resistance quantization decision threshold is determined from the candidate resistance quantization decision threshold set by a set of soft metric decision thresholds;
[0054] The number of soft quantization decision thresholds is equal to the number of resistance quantization decision thresholds.
[0055] In some examples, the method further includes determining a set of candidate resistor quantization decision thresholds based on a set of reference cells using resistive memory devices with parameters and dimensions consistent with the memory array.
[0056] One or more resistive storage devices with two or more resistance values are connected in series and parallel to obtain a set of corresponding reference cell values with different resistance values.
[0057] Based on one or more of the aforementioned reference cell values, a quantization decision threshold value for the candidate resistor is obtained.
[0058] In some examples, the method for determining the soft metric decision threshold further includes:
[0059] Based on the read / write error characteristics of the resistive storage device, the corresponding cascaded channel model is determined;
[0060] After obtaining the cascaded channel model, the mean and variance of the resistance values of different resistive states related to the resistive storage device are determined, and the write error rate of the resistive storage device is determined.
[0061] The error correction performance value judgment method based on the finite-length performance bound of the maximum mutual information of channel capacity, or the maximum cutoff frequency, or the minimum mean square error, searches for the optimal boundary of error correction performance value in the cascaded channel model within a specified range of parameters such as temperature, tunnel magnetoresistance ratio, resistance fluctuation of the storage device, or operating voltage, and determines the soft metric decision threshold set.
[0062] In some examples, based on the read / write error characteristics associated with the resistive storage device, a corresponding cascaded channel model is determined, wherein...
[0063] The read / write error characteristics include write errors, read interference errors, and read decision errors associated with the resistive storage device;
[0064] The cascaded channel model has an asymmetric channel model and a Gaussian channel model;
[0065] The simulation results of the cascaded channel model can approximately describe the read / write error characteristics of the resistive storage device and its related peripheral circuits.
[0066] In some examples, the method for determining the soft metric decision threshold further includes:
[0067] The number of resistance quantization decision thresholds and the number of soft quantization decision thresholds are equal and correspond one-to-one;
[0068] After obtaining the set of candidate resistance quantization decision thresholds and the set of soft quantization decision thresholds, at least one soft quantization decision threshold value is selected and replaced with an equal number of candidate resistance quantization decision threshold values, and the error correction performance value in the cascaded channel model is obtained within the specified parameter range.
[0069] After determining the error correction performance value, the global difference of the error correction performance value is obtained by comparing it with the optimal boundary of the error correction performance value. The candidate resistance quantization decision threshold value with the smallest global difference of the error correction performance value is selected and determined as the resistance quantization decision threshold value corresponding to the selected softness decision threshold value.
[0070] Repeat the above steps until all soft metric decision thresholds in the soft metric decision threshold set have their corresponding resistance quantization decision threshold values determined.
[0071] In some examples, the comparison operation is performed by a quantization decision circuit that includes a sensitive amplifier, and the method further includes:
[0072] The quantization decision circuit needs to perform multi-level quantization decision operations;
[0073] Each level of quantization decision operation requires calling at least one of the single-level decision circuits and selecting at least one of the resistance quantization decision thresholds from the decision threshold set. After performing the single-level quantization decision operation, one bit of quantization result is output.
[0074] The quantization decision circuit has at least one single-stage decision circuit composed of a sensitive amplifier.
[0075] The multi-bit quantization method for memory is applied to a memory cell array. The memory cell array includes multiple memory blocks, each of which includes multiple memory cells, which may include one or more types of memory cells. These memory cells include, but are not limited to, devices based on magnetic tunnel junctions, devices based on resistive switching materials, devices based on ferroelectric capacitors, and devices based on amorphous oxide thin-film transistors. Each memory cell contains at least one memory device, and each memory device has two or more resistive states that can switch between different resistive states.
[0076] In some examples, the different resistive states have different resistance values;
[0077] In some examples, the resistive state is characterized by non-volatility.
[0078] In some examples, a storage cell array module may include one or more storage cells.
[0079] In some examples, the memory cell is programmed with N resistive states to store one bit of N-ary information, where μ i (i = 1, 2, ..., N) represents the average resistance value of the i-th resistive state in a group of memory cells. Due to factors such as process variations, the resistance value of the i-th resistive state fluctuates. The statistical variance of the resistance value of the i-th resistive state in a group of memory cells is denoted as σ. i .
[0080] In some examples, the TMR of an MRAM with binary storage cells is defined as TMR = (μ1 - μ0) / μ0.
[0081] The read margin is the difference between the analog values of current or voltage generated by the sensitive amplifier when it senses the memory cell and the decision threshold within the decision threshold region.
[0082] Focusing on the example of a binary memory cell, the cell is programmed with two resistive states, where μ1 corresponds to a high-resistance state and μ0 corresponds to a low-resistance state. When the decision threshold resistance is 'a', the read margin is defined as min[(μ1-a) / σ1,(a–μ0) / σ0)]. Typically, the read margin can be considered equal to (a–μ0) / σ0.
[0083] In some examples, the overall read accuracy of a 32Mb memory array with a 6σ0 read margin is 96.74%.
[0084] In some examples, having a read margin of ≥3σ0 is a prerequisite for implementing error-correcting code operations.
[0085] In some examples, the stored data is encoded with error-correcting codes and placed in the memory. The error-correcting code encoding schemes include: single error-correcting Hamming codes, BCH codes that can correct multiple bit errors, LDPC codes, and Polar codes.
[0086] In some examples, the analog output value is compared with multiple resistive quantization decision thresholds to generate a multi-bit quantization result and then output a set of discrete values. The comparison operation is performed by the quantization decision circuit, that is, the quantization decision circuit and the resistive quantization decision thresholds constitute a multi-bit quantizer.
[0087] In some examples, the quantization decision circuit includes a sensitive amplifier that performs the following operations:
[0088] The analog output value stored in the storage unit is compared step by step with the decision threshold value in the resistance decision threshold set;
[0089] The number of discrete values is equal to or greater than the power of the number of digits in the encoding method determined by the ECC.
[0090] After determining that the simulated output value is within a certain decision threshold region, a discrete value corresponding to the region is output.
[0091] In some examples, the quantization decision circuit has one or more sub-decision circuits, and at least one sub-decision circuit has full margin decision function, characterized in that:
[0092] During the quantization process, the decision circuit can select to perform one or more levels of decision operations depending on the specific quantization method being implemented.
[0093] Optionally, when performing multi-level decisions, at least two levels of decision quantization operations need to be performed. Each level of decision quantization operation needs to call at least one of the sub-decision circuits and select at least one of the decision thresholds from the decision threshold set. Its characteristic is:
[0094] The analog output value in the storage unit is compared with a decision threshold value in the decision threshold set; further, the selection of the decision threshold of the second-level and subsequent sub-decision circuits is determined by the output result of the previous sub-decision circuit.
[0095] In some examples, the quantization decision circuit includes a sensitive amplifier with full margin decision capability, characterized in that when the sensitive amplifier with full margin decision capability senses the memory cell and the decision threshold, the analog values of the current or voltage generated have the maximum difference within the decision threshold region.
[0096] In some examples, the resistance quantization decision threshold is characterized by:
[0097] The resistance quantization decision threshold is composed of reference cells of the memory arranged according to a certain relationship; the resistance range of the memory cells is divided into multiple decision threshold regions, and this decision threshold has the smallest global difference with the soft quantization decision threshold with the best error correction performance under the same channel model conditions.
[0098] In some examples, determining the soft metric decision threshold includes:
[0099] The error correction performance judgment method based on the maximum mutual information of channel capacity, or the maximum cutoff frequency, or the minimum mean square error finite-length performance boundary, uses a dynamic programming algorithm or differential evolution algorithm to find the optimal boundary of error correction performance value in the cascaded channel model within a specified range of parameters such as temperature, or TMR, or resistance fluctuation of the storage device, or operating voltage, and determines the soft metric decision threshold set.
[0100] In some examples, the multi-bit quantizer can be applied to binary input additive white Gaussian noise (BI-AWGN) channels, i.e., read-out decision error channels.
[0101] In some examples, the output discrete value is decoded using the error correction code to obtain the stored data. The error correction code decoding scheme includes: sequential deletion (SC), cyclic redundancy check serial cancellation list (CRC-SCL) method, time-domain iteration (BM) method, confidence propagation (BP) method, reliability-based minimum sum (RB-MS) method, and reliability-based hierarchical confidence (RB-LBP) method.
[0102] This example provides a multi-bit quantization method for a memory using error-correcting codes, comprising: receiving stored data; encoding the stored data with error-correcting codes and storing it in the memory; reading the analog output value of the stored data in the memory; comparing the analog output value with multiple resistive quantization decision thresholds to generate a multi-bit quantization result and then outputting a set of discrete values; the comparison operation is performed by a quantization decision circuit, which includes a sensitive amplifier. The output discrete values are decoded based on a selected error-correcting code. Under conditions where the quantization decision thresholds have low read margins, the error-correcting code decoding scheme based on the provided multi-bit quantization method can achieve better read accuracy and lower decoding computational complexity than that based on a single-bit quantization circuit. When the read margin of the target memory cell is extremely low (<3σ0), the output result of the quantization decision circuit using a sensitive amplifier with full margin decision function can be used to perform multi-bit error-correcting code decoding operations.
[0103] To better understand the present invention, this embodiment provides a more specific example;
[0104] The quantizer for the channel model is implemented using a combination of three resistor networks and a full-margin sensitive amplifier.
[0105] The multi-bit quantization method using error-correcting codes in memory mainly consists of three parts: encoding, channel modeling, and decoding. First, the input signal is encoded and sent to the channel model in the memory to obtain the initial bit error rate of the channel. The log-likelihood ratio (LLR) is usually used to characterize the channel reliability. Finally, the signal is sent to the decoder for decoding.
[0106] The log-likelihood ratio is defined as:
[0107]
[0108] Where j = 0, 1, 2, 3, the two-bit quantizer quantizes the output into y0, y1, y2, y3, and x is the input signal.
[0109] Figure 2 A schematic diagram of a write error channel model is shown. Figure 3 A schematic diagram of a read interference error channel model is shown. Write errors and read interference errors can be described using a binary asymmetric channel (BAC). When the read current direction is consistent with the write "0" current direction, the crossover probability of the BAC can be expressed as:
[0110]
[0111]
[0112] Where q0 and q1 are the accuracy rates of transmitting 0 and 1 respectively, and p0 and p1 are the total probabilities of errors occurring when transmitting a 0→1 state (corresponding to a write "1" operation) and a 1→0 state (corresponding to a write "0" operation). P0 and P1 are the write error rates of writing "1" operations and writing "0" operations respectively. r0 Let P be the read interference error rate. Assuming that the probability of writing "1" and writing "0" is 50% each, the crossover probabilities of BAC in the 0→1 and 1→0 states can be given as P0 / 2 and P1 / 2, respectively.
[0113] Figure 4 A schematic diagram of a read decision error channel model is shown.
[0114] Since the resistance distributions of MTJ (magnetic tunnel junction) devices in both high and low resistance states approximately follow a Gaussian distribution, a GMC can be used to describe the read decision error, and its error rate can be expressed as:
[0115]
[0116] Where j = 0, 1, 2, 3, 4, a0 = -∞ and a4 = +∞, are the quantization interval boundaries. i = 0, 1, Let a1, a2, a3 ∈ [μ0, μ1] be the right-tail function of the Gaussian distribution, and let a1, a2, a3 ∈ [μ0, μ1] be the decision thresholds of the quantizer.
[0117] Figure 5 A schematic diagram of a cascaded channel model is shown.
[0118] Composed of a BAC and a GMC, write errors and read interference errors can be described using a cascaded BAC, while read decision errors are described using the GMC. The crossover probability of the cascaded BAC can be expressed as:
[0119]
[0120]
[0121] Where q0 and q1 are the accuracy rates of transmitting 0 and 1, respectively, and p0 and p1 are the total probabilities of errors occurring when transmitting the 0→1 state and the 1→0 state, respectively. Assuming that the probability of writing "1" and writing "0" is 50% each, the crossover probabilities of BAC in transmitting the 0→1 and 1→0 states can be expressed as P0 / 2 and P1 / 2, respectively.
[0122] Combining BAC and GMC yields the cascaded channel model, whose total probability can be expressed as:
[0123]
[0124]
[0125] Figure 6 Seven proposed combinations of resistor networks are presented as decision threshold sets.
[0126] Resistor network combinations are achieved by connecting a set of MTJ resistors with parameters and dimensions identical to those of the memory array in series and parallel. Since the selected MTJ devices are of the same size, the minimum number of MTJ resistors should be used to ensure good tracking performance and the lowest read error rate of the corresponding hard-decision resistor quantization scheme over a wide temperature range and a large process variation range. The seven network combinations designed in this paper all use no more than six MTJ resistors, thus controlling the area size of the resistor network. Specifically, R... P +(R P / / R AP / / R AP ), (R P +R AP ) / / (R P +R AP ), R P +(R AP / / R P / / R P ), (RP / / R AP )+R AP / 3、2(R P / / R AP ), R AP / 3+R AP / 3 and (R) P / / R AP )+(R P / / R AP / / R AP The optimal three sets of resistor network combinations are selected by comparing how closely they resemble the MCR quantizer under process fluctuations and temperature changes.
[0127] like Figure 7 As shown, Figure 7 The figure shows a comparison of the resistance values of the decision thresholds for seven resistor networks and three soft-weight decision thresholds. Figure 7 The left side (a) shows a comparison of the decision threshold and softness decision threshold resistance values of seven resistor networks at different temperatures with a 10% process deviation. The resistor R with the best quantization resistance for cutoff rate is selected. P +(R P / / R AP / / R AP ), 2(R P / / R AP ) and (R P / / R AP )+(R P / / R AP / / R AP ) serves as the two-bit quantization decision threshold for the proposed channel quantizer.
[0128] Figure 7 The right side (b) shows a comparison of the decision threshold and softness decision threshold values of the seven resistor networks at different temperatures with a 12% process deviation, selecting the resistor R that best follows the cutoff rate quantization resistance. P +(R P / / R AP / / R AP ), 2(R P / / R AP ) and (R P / / R AP )+(R P / / R AP / / R AP ) serves as the two-bit quantization decision threshold for the proposed channel quantizer.
[0129] Figure 8This is a schematic diagram illustrating the read margin range of a binary two-bit quantizer, as shown in an exemplary embodiment of this application. It demonstrates a comparison-type PCSA used as the decision circuit for the first and second stages of quantization in a two-bit quantization method. Here, a2' is the first-stage resistive quantization decision threshold, and a1' and a3' are the second-stage resistive quantization decision thresholds. In the second-stage quantization, considering TMR = 88% and σ0 / μ0 = 10%, when the resistance of the resistive storage device is greater than a2', the read margin of the PCSA is approximately Δa3' = a3' – a2' = 1.79σ0; when the resistance of the resistive storage device is less than a2', the read margin of the PCSA is only approximately Δa1' = a1' – μ0 = 1.34σ0. Both cases are far below 3σ0, making subsequent error correction code operations impossible.
[0130] When using an IMB-CSA with full margin decision capability as the decision circuit for the second-stage quantization, the read margin for the second-stage quantization decision does not depend on the selection of the second-stage resistive quantization decision threshold, but directly uses the values of μ1, a2', and μ0 as the full margin decision threshold. Correspondingly, considering TMR = 88% and σ0 / μ0 = 10%, when the resistance of the resistive storage device is greater than a2', the read margin of the IMB-CSA is approximately μ1–a2' = 5.73σ0; when the resistance of the resistive storage device is less than a2', the read margin of the IMB-CSA is approximately Δa1' = a2'–μ0 = 3.05σ0. Both cases are greater than 3σ0, allowing for subsequent error correction code operations.
[0131] like Figure 9 As shown, Figure 9 The figure shown is a comparison of read decision errors between a resistor network decision threshold and a soft-metric decision threshold. Figure 9 The left side (a) shows a comparison of read decision errors of the resistive network decision threshold and the soft metric decision threshold at different temperatures during two-dimensional quantization. Polar_MCR represents the read decision error of the soft metric decision threshold, and Polar_R represents the read decision error of the resistive network decision threshold. The error rate increases with increasing temperature. At temperatures of 233K-400K and a process deviation of 12%, the difference between the read decision errors of the resistive network decision threshold and the soft metric decision threshold is small.
[0132] Figure 9 The right side (b) shows a comparison of read decision errors of the resistive network decision threshold and the soft metric decision threshold under different process deviations during two-dimensional quantization. Polar_MCR represents the read decision error of the soft metric decision threshold, and Polar_R represents the read decision error of the resistive network decision threshold. The error rate increases with the increase of process deviation. Under the conditions of process deviation of 6%-20%, temperature of 300K and TMR=88%, the difference between the read decision errors of the resistive network decision threshold and the soft metric decision threshold is small.
[0133] like Figure 10 As shown, Figure 10 This is a comparison chart of errors after ECC decoding of the decision thresholds of a resistor network and the decision thresholds of a soft-measuring network. Figure 10 The attached figure on the left (a) shows the error comparison of the resistive network decision threshold and the soft metric decision threshold obtained by maximizing mutual information, maximizing cutoff rate, and minimizing finite length performance bound under different temperatures during the two-bit quantization provided by this invention, after ECC decoding. Taking Polar code with a code rate of 0.7 as an example, the decoding algorithm adopts the serial cancellation decoding algorithm, the temperature is 233K-400K, and the process deviation is 12%. Polar_MMI represents maximizing mutual information, Polar_PPV represents minimizing finite length performance bound, Polar_MCR represents maximizing cutoff rate, and Polar_R represents the proposed resistive quantizer. As can be seen from the figure, the frame error rate increases with the increase of temperature. The performance of the proposed quantizer exceeds the maximization of mutual information and the minimization of finite length performance bound, and approaches the maximization of cutoff rate.
[0134] Figure 10 The attached figure on the right (b) shows the error comparison between the soft metric decision threshold obtained by maximizing mutual information, maximizing cutoff rate, and minimizing finite length performance bounds obtained by the present invention and ECC decoding under different process deviations during two-bit quantization. Taking Polar code with a code rate of 0.7 as an example, with process deviations of 6%-20%, temperature of 300K and TMR=88%, it can be seen from the figure that the frame error rate increases with the increase of process deviation. The performance of the proposed quantizer exceeds the performance of maximizing mutual information and minimizing finite length performance bounds, and approaches the performance of maximizing cutoff rate.
[0135] like Figure 11 As shown, Figure 11 This is a comparison chart of one-dimensional and two-dimensional quantization simulations. Figure 11 The attached figure on the left (a) shows a comparison of simulation results of one-bit quantization and two-bit quantization at different temperatures provided by the present invention. Taking Polar code with a code rate of 0.7 as an example, the decoding algorithm adopts the serial cancellation decoding algorithm. Polar_MCR represents the simulation result of two-bit maximum cutoff rate quantization, Polar_R represents the simulation result of the proposed two-bit resistive quantization, 1bit_Polar_MCR represents the simulation result of one-bit maximum cutoff rate quantization, and 1bit_Polar_R represents the simulation result of one-bit resistive quantization. As can be seen from the figure, two-bit resistive quantization has better following performance for the soft quantization decision threshold than one-bit quantization. At the same time, with a temperature of 233K to 400K and a process deviation of 12%, the error rate of two-bit quantization is reduced by nearly an order of magnitude compared with one-bit quantization.
[0136] Figure 11The attached figure on the right (b) shows a simulation comparison of one-bit quantization and two-bit quantization under different process deviations provided by the present invention. Taking Polar code with a code rate of 0.7 as an example, the decoding algorithm adopts the serial cancellation decoding algorithm, and the parameter representation method is the same as... Figure 11 The same applies to the left side (a). As can be seen from the figure, two-bit resistance quantization has better following performance for soft-measure decision thresholds than one-bit quantization. At the same time, with process deviations of 6-16%, temperatures of 300K, and TMR of 88%, the error rate of two-bit quantization is reduced by nearly an order of magnitude compared to one-bit quantization.
[0137] Other embodiments of this application will readily conceive of by considering the specification and practicing the embodiments disclosed herein. This application is intended to cover any variations, uses, or adaptations of this application that follow the general principles of this application and include common knowledge or customary techniques in the art not disclosed herein.
[0138] The above content is merely a preferred exemplary embodiment of this application and is not intended to limit the implementation of this application. Those skilled in the art can easily make corresponding modifications or alterations based on the main concept and spirit of this application. Therefore, the scope of protection of this application should be determined by the scope of protection claimed in the claims.
Claims
1. A multi-bit quantization method for a memory employing error-correcting codes, characterized in that, The multi-bit quantization method for the memory employing error-correcting codes includes: Receive stored data, encode the stored data with error correction code, and put it into the memory; Read the analog output value of the stored data in the memory; The simulated output value is compared with multiple resistance quantization decision thresholds to generate a multi-bit quantization result, and then a set of discrete values is output. The comparison operation is performed by a quantization decision circuit, which includes a sensitive amplifier. The method further includes determining the resistance quantization decision threshold based on the selected error correction code, and the method also includes: Based on the selected error correction code, determine the number of resistance quantization decision thresholds; The set of candidate resistor quantization decision thresholds is determined based on a set of reference cells that use resistive storage devices with the same parameters and dimensions as the storage array. Based on the selected error correction code, the resistance quantization decision threshold is determined from the candidate resistance quantization decision threshold set by a set of soft metric decision thresholds; The number of soft quantization decision thresholds is equal to the number of resistance quantization decision thresholds; The method further includes determining a set of candidate resistor quantization decision thresholds based on a set of reference cells using resistive memory devices with parameters and dimensions identical to those of the memory array, and further comprising: One or more resistive storage devices with two or more resistance values are connected in series and parallel to obtain a set of corresponding reference cell values with different resistance values. Based on one or more of the aforementioned reference cell values, obtain a quantization decision threshold value for the candidate resistor; The method for determining the soft metric decision threshold further includes: Based on the read / write error characteristics of the resistive storage device, the corresponding cascaded channel model is determined; After obtaining the cascaded channel model, the mean and variance of the resistance values of different resistive states related to the resistive storage device are determined, and the write error rate of the resistive storage device is determined. The error correction performance value judgment method based on the finite-length performance bound of the maximum mutual information of channel capacity, or the maximum cutoff frequency, or the minimum mean square error, searches for the optimal boundary of error correction performance value in the cascaded channel model within a specified range of parameters such as temperature, tunnel magnetoresistance ratio, resistance fluctuation of the storage device, or operating voltage, and determines the soft metric decision threshold set.
2. The multi-bit quantization method for a memory employing error-correcting codes according to claim 1, characterized in that, The method further includes comparing the simulated output value with multiple resistance quantization decision thresholds to generate a multi-bit quantization result and then outputting a set of discrete values. The number of discrete values is determined based on the algorithm for selecting the error correction code, and the output is determined accordingly. The stored data is obtained by decoding the output discrete value using the error correction code.
3. The multi-bit quantization method for a memory employing error-correcting codes according to claim 2, characterized in that, Based on the read / write error characteristics associated with the resistive storage devices, a corresponding cascaded channel model is determined, wherein... The read / write error characteristics include write errors, read interference errors, and read decision errors associated with the resistive storage device; The cascaded channel model has an asymmetric channel model and a Gaussian channel model; The simulation results of the cascaded channel model can describe the read / write error characteristics of the resistive storage device and its related peripheral circuits.
4. The multi-bit quantization method for a memory employing error-correcting codes according to claim 3, characterized in that, The method for determining the soft metric decision threshold further includes: The number of resistance quantization decision thresholds and the number of soft quantization decision thresholds are equal and correspond one-to-one; After obtaining the set of candidate resistance quantization decision thresholds and the set of soft quantization decision thresholds, at least one soft quantization decision threshold value is selected and replaced with an equal number of candidate resistance quantization decision threshold values, and the error correction performance value in the cascaded channel model is obtained within the specified parameter range. After determining the error correction performance value, the global difference of the error correction performance value is obtained by comparing it with the optimal boundary of the error correction performance value. The candidate resistance quantization decision threshold value with the smallest global difference of the error correction performance value is selected and determined as the resistance quantization decision threshold value corresponding to the selected softness decision threshold value. Repeat the above steps until all soft metric decision thresholds in the soft metric decision threshold set have their corresponding resistance quantization decision threshold values determined.
5. The multi-bit quantization method for a memory employing error-correcting codes according to claim 1, characterized in that, The comparison operation is performed by a quantization decision circuit, which includes a sensitive amplifier, and the method further includes: The quantization decision circuit needs to perform multi-level quantization decision operations; Each level of quantization decision operation requires calling at least one single-level decision circuit and selecting at least one of the resistor quantization decision thresholds from the decision threshold set. After executing the single-level quantization decision operation, one bit of quantization result is output. The quantization decision circuit has at least one single-stage decision circuit composed of a sensitive amplifier.