A controller that uses a serial-to-serial method to increase serial communication speed

Abstract

The present invention discloses a controller that utilizes a serial-to-serial method to increase the speed of serial communication. The controller belongs to the field of devices related to input and output circuits and includes a clock generation unit and a signal temporary storage unit. The clock generation unit converts the original clock signal and the high-speed clock signal transmitted via the chip select data line into the required high-speed and low-speed clock signals, respectively. The signal temporary storage unit is divided into a low-speed write storage unit and a high-speed read storage unit. The present invention achieves the function of increasing the serial transmission speed by controlling the low-speed write storage unit and the high-speed read storage unit differently through such a scheme. By using two-level registers and gate circuit control, the time of controlling the switch is greatly saved. In particular, when used in the actual application of serial chips with speed limits, the controller can significantly increase the transmission speed.

Description

Technical Field

[0001] The present invention relates to the field of input and output circuit devices, and in particular to a controller that utilizes a serial-to-serial method to increase serial communication speed. Background Art

[0002] The interfaces used to connect I / O devices typically perform the following functions: Device identification and selection: Each peripheral device is assigned its own universal and specific identifiers during manufacture, and the host computer also assigns an I / O address to the interface circuit. The host computer uses this function to identify and select the device with which to exchange information from multiple peripherals. Data buffering and control (transmission protocol): The data processing speed of the external device often differs significantly from that of the host computer. Even if the speeds are the same, synchronization between the two is difficult due to the lack of a shared clock signal. One or more data buffer registers and controllers are typically included in the interface circuit to enable efficient transmission and reception of various data between the two. Control command and status information transmission: When the CPU needs to start a peripheral device, it first sends a start command to the peripheral through the command register in the interface. When the peripheral is ready, a "ready" status message is sent back to the status register in the interface for the CPU to read. Only then can data exchange between the host and the peripheral begin. Data conversion and transmission: The data format of each device often varies. The interface circuit must convert the data according to the requirements of the other device to ensure that the data is valid and readable. Such as serial / parallel conversion, analog / digital conversion, and conversion between binary code and ASCII code, etc. In addition to the above functions, the interface usually also has error detection and correction, interrupt, timing control and other functions.

[0003] Some serial chips today, such as AD chips, are relatively slow and cannot support high-speed transmission. To increase the transmission speed of these serial chips, the serial interface is typically converted to a parallel interface, as described in patent (CN200610005024.1). This approach increases the speed by increasing the number of data lines, significantly improving transmission speeds, but is not cost-effective. Summary of the Invention

[0004] In response to the existing problems, the present invention aims to provide a controller that utilizes a serial-to-serial method to increase the serial communication speed, so as to solve the problems raised in the above background technology.

[0005] To achieve the above object, the present invention provides the following technical solutions:

[0006] A controller that uses a serial-to-serial method to increase the speed of serial communication, including a clock generation unit and a signal temporary storage unit; the clock generation unit converts the original clock signal and the high-speed clock signal transmitted through the chip select data line into the required high-speed and low-speed clock signals;

[0007] The signal temporary storage unit is divided into a low-speed write storage unit and a high-speed read storage unit. The low-speed write storage unit of the signal temporary storage unit includes a signal receiving interface and a received signal temporary storage module. The signal receiving interface is responsible for the connection between the signal and the received signal temporary storage unit; the received signal temporary storage module is used to store the signal that needs to be accelerated.

[0008] The high-speed reading storage unit of the signal temporary storage unit includes a sending signal storage unit and a sending signal interface. The sending signal storage unit is used to store the signal to be accelerated and is connected to the sending signal interface. The receiving signal temporary storage unit is used to store the serial signal transmitted slowly. The sending signal temporary storage unit is used to store the serial signal that needs to be sent quickly.

[0009] The controller generates two clock signals, a slow clock signal is provided to the receiving signal temporary storage unit, and a fast clock signal is provided to the high-speed reading storage unit; the controller stores the signals of multiple channels that need to be converted at the same time, and then reads them out in sequence at high speed.

[0010] As a further preferred solution of the present invention, the serial signal converted by the signal temporary storage unit supports multiple simultaneous inputs and high-speed readout of a single channel in sequence, and several times more signals can be read out in the same time.

[0011] As a further preferred solution of the present invention, the low-speed write storage unit and the high-speed read storage unit of the signal temporary storage unit are isolated through different registers.

[0012] As a further preferred solution of the present invention, the data storage and sending units of the signal temporary storage unit are both in a first-in-first-out data storage mode.

[0013] As a further preferred embodiment of the present invention, the high-speed read storage unit of the signal temporary storage unit includes two levels of registers, wherein multiple registers of the first level are connected end to end, and the output end of the last register of the first level is connected to the input end of the second level register; the clock of the first level register is a slow clock signal, and the clock of the second register is a high-speed clock signal.

[0014] Compared with the prior art, the beneficial effects of the present invention are as follows: the present invention is particularly useful in situations where the overall circuit interface is not easily changed. In order to increase the serial speed without changing the original data line, a serial-to-serial method is used directly. This method mainly temporarily stores the serial data to be converted and then reads it at high speed, which can speed up the serial data. Through such a scheme, the present invention achieves the function of increasing the serial transmission speed by controlling the different clocks for writing low-speed write storage units and high-speed read storage units. By using two-level registers, the gate circuit control greatly saves the time of controlling the switch. In particular, when used in practical applications of serial chips with speed limits, the controller can greatly increase the transmission speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 A control flow diagram of a controller that uses a serial-to-serial method to increase the serial communication speed and adds an acceleration controller.

[0016] Figure 2 This is a schematic diagram of the overall flow of the internal structure of a controller that uses a serial-to-serial method to increase the speed of serial communication.

[0017] Figure 3 This is a flow chart of the internal structure of the signal temporary storage unit in the accelerator of the controller that uses the serial-to-serial method to increase the serial communication speed.

[0018] Figure 4 This is a comparison chart of the process and clock of a controller with and without an accelerator that uses the serial-to-serial method to increase the serial communication speed.

[0019] Figure 5 The invention discloses a data storage mode and a data reading mode of a controller that uses a serial-to-serial method to improve the serial communication speed. DETAILED DESCRIPTION

[0020] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of the present invention.

[0021] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "provided with," "connected," and "connected" should be understood in a broad sense; for example, they may refer to fixed connections, detachable connections, or integral connections; they may refer to mechanical connections or electrical connections; they may refer to direct connections or indirect connections via an intermediate medium; and they may refer to internal communication between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention in specific contexts.

[0022] See also Figure 1-5 A controller that uses a serial-to-serial method to increase the speed of serial communication includes a clock generation unit and a signal temporary storage unit; the clock generation unit converts the original clock signal and the high-speed clock signal transmitted through the chip select data line into the required high-speed and low-speed clock signals;

[0023] The signal temporary storage unit is divided into a low-speed write storage unit and a high-speed read storage unit. The low-speed write storage unit of the signal temporary storage unit includes a signal receiving interface and a received signal temporary storage module. The signal receiving interface is responsible for the connection between the signal and the received signal temporary storage unit; the received signal temporary storage module is used to store the signal that needs to be accelerated.

[0024] The high-speed reading storage unit of the signal temporary storage unit includes a sending signal storage unit and a sending signal interface. The sending signal storage unit is used to store the signal to be accelerated and is connected to the sending signal interface. The receiving signal temporary storage unit is used to store the serial signal transmitted slowly. The sending signal temporary storage unit is used to store the serial signal that needs to be sent quickly.

[0025] The controller generates two clock signals, a slow clock signal is provided to the receiving signal temporary storage unit, and a fast clock signal is provided to the high-speed reading storage unit; the controller stores the signals of multiple channels that need to be converted at the same time, and then reads them out in sequence at high speed.

[0026] The converted serial signal of the signal temporary storage unit supports multiple channels of simultaneous input and high-speed readout of a single channel in sequence, and several times more signals can be read out in the same time.

[0027] The low-speed write storage unit and the high-speed read storage unit of the signal temporary storage unit are isolated through different registers.

[0028] The data storage and sending units of the signal temporary storage unit are both in a first-in-first-out data storage mode.

[0029] The high-speed read storage unit of the signal temporary storage unit includes two levels of registers, wherein multiple registers of the first level are connected end to end, and the output end of the last register of the first level is connected to the input end of the second level register; the clock of the first level register is a slow clock signal, and the clock of the second register is a high-speed clock signal.

[0030] The present invention is a controller for serial communication speed using a serial-to-serial method. The entire controller is divided into: a clock generating unit: converting the original clock signal and the high-speed clock signal transmitted through the chip select data line into the required high-speed and low-speed clock signals respectively. A signal temporary storage unit: divided into a low-speed write storage unit and a high-speed read storage unit. A low-speed write storage unit: including a signal receiving interface: responsible for the connection between the signal and the receiving signal temporary storage unit; a receiving signal temporary storage module: storing the signal that needs to be accelerated. A high-speed read storage unit: including a sending signal storage unit and a sending signal interface, the sending signal storage unit is used to store and connect the signal to be accelerated to the sending signal interface. There are two different clock signals in the present invention, wherein the slow clock is provided to the receiving signal storage unit, and the fast clock is provided to the sending signal storage unit.

[0031] In this example, the high-speed clock signal can reach 10 times the slow clock signal, such as Figure 3 As shown, T0 is 10 times T1, and the receiving signal unit and the sending signal unit are separated between different registers. The data storage and sending units are both in first-in-first-out data storage mode. Figure 4 As shown, the data storage unit consists of two levels of registers. The multiple registers of the first level are connected end to end, and the output end of the last register of the first level is connected to the input end of the second level register; the clock of the first level register is a slow clock signal, and the clock of the second register is a high-speed clock signal.

[0032] The acceleration controller and the accelerated serial signal share a chip select data line. The high-speed clock in the acceleration controller is transmitted through the chip select signal line, and is converted into a high-speed clock by the internal clock generation unit and used.

[0033] like Figure 3 As shown, before acceleration, data is read sequentially at a low speed, taking n*8T0. After acceleration, data is read simultaneously at a low speed and stored, and then read sequentially at a high speed, taking 8T0 + n*8T1. Since T0 is 10 times T1, the conversion transmission time is 8T0 + 0.8n*T0. This rule allows for a more significant speed increase when the number of conversion paths exceeds two.

[0034] The present invention is particularly useful in situations where the overall circuit interface is difficult to change. In order to increase the serial speed without changing the original data line, a serial-to-serial method is directly used. This method mainly temporarily stores the serial data to be converted and then reads it at high speed, which can speed up the serial data.

[0035] The present invention utilizes this scheme to improve serial transmission speed by controlling the clocks for low-speed writes and high-speed reads separately. By utilizing two-stage registers and gate circuit control, the controller significantly reduces switching time. This controller can significantly increase transmission speed, particularly in applications with speed-limited serial chips.

[0036] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above and that the invention can be embodied in other specific forms without departing from the spirit or essential characteristics of the invention. The embodiments should, therefore, be considered in all respects as illustrative and non-restrictive. The scope of the invention is defined by the appended claims rather than the foregoing description, and all changes coming within the meaning and range of equivalents of the claims are intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim to which it relates.

[0037] In addition, it should be understood that although this specification is described in terms of implementation methods, not every implementation method contains only one independent technical solution. This narrative method of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment can also be appropriately combined to form other implementation methods that can be understood by those skilled in the art.

Claims

1. A controller that uses a serial-to-serial method to increase serial communication speed, characterized in that: It includes a clock generation unit and a signal temporary storage unit; the clock generation unit converts the original clock signal and the high-speed clock signal transmitted through the chip select data line into the required high-speed and low-speed clock signals; The signal temporary storage unit is divided into a low-speed write storage unit and a high-speed read storage unit. The low-speed write storage unit of the signal temporary storage unit includes a signal receiving interface and a received signal temporary storage module. The signal receiving interface is responsible for the connection between the signal and the received signal temporary storage unit; the received signal temporary storage module is used to store the signal that needs to be accelerated. The high-speed reading storage unit of the signal temporary storage unit includes a sending signal storage unit and a sending signal interface. The sending signal storage unit is used to store the signal to be accelerated and is connected to the sending signal interface. The receiving signal temporary storage unit is used to store the serial signal transmitted slowly. The sending signal temporary storage unit is used to store the serial signal that needs to be sent quickly. The controller generates two clock signals, a slow clock signal is provided to the receiving signal temporary storage unit, and a fast clock signal is provided to the high-speed reading storage unit; the controller stores the signals of multiple channels that need to be converted at the same time, and then reads them out in sequence at high speed.

2. The controller for improving serial communication speed by using a serial-to-serial method according to claim 1, characterized in that: The converted serial signal of the signal temporary storage unit supports multiple channels of simultaneous input and high-speed readout of a single channel in sequence, and several times more signals can be read out in the same time.

3. The controller for improving serial communication speed by using a serial-to-serial method according to claim 2, characterized in that: The low-speed write storage unit and the high-speed read storage unit of the signal temporary storage unit are isolated through different registers.

4. The controller for improving serial communication speed by using a serial-to-serial method according to claim 3, characterized in that: The data storage and sending units of the signal temporary storage unit are both in a first-in-first-out data storage mode.

5. The controller for improving serial communication speed by using a serial-to-serial method according to claim 4, characterized in that: The high-speed read storage unit of the signal temporary storage unit includes two levels of registers, wherein multiple registers of the first level are connected end to end, and the output end of the last register of the first level is connected to the input end of the second level register; the clock of the first level register is a slow clock signal, and the clock of the second register is a high-speed clock signal.

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