Modeling Method of Multi-Core Processor Based on AADL

Abstract

The present invention provides a method for modeling a multi-core processor based on AADL. The multi-core processor is modeled using the Architecture Analysis and Design Language AADL. Different types of AADL components such as system components, process components, memory components, device components, and abstract components are established to model the overall multi-core processor and various parts inside the multi-core processor, including the processor part, memory part, device part, cluster structure, etc. Interaction ports port, data components data, connections connection, etc. are established to ensure the type correctness and flow correctness of data transmission. Referring to the physical composition structure of the multi-core processor, the inclusion relationship and interaction connection relationship between components are checked, so as to use the established model to experiment with the capabilities of the multi-core processor on an open-source and free platform, achieving the purpose of liberating human resources and saving financial expenditures.

Description

Technical Field

[0001] The present invention belongs to the technical field of simulation modeling methods, and particularly relates to a multi-core processor modeling method based on AADL. Background Art

[0002] When conducting scientific experiments using hardware represented by multi-core processors as a typical example, experimenters often use devices in the real physical world for research. In recent years, with the rapid development of computer science and technology, different manufacturers have actively explored according to the needs of industry development and their own understandings, and an endless stream of different models of multi-core processors has emerged, with an increasingly accelerating pace of replacement, resulting in a sharp increase in the human input required for hardware experiments and a huge financial expenditure. For each batch of actual products of multi-core processors produced, a batch needs to be purchased for research and experiments, which requires a large amount of financial and human resources. The existing research method of real physics in the prior art results in high experimental costs and low efficiency. Summary of the Invention

[0003] In view of this, the present invention provides a multi-core processor modeling method based on AADL, which models different models of multi-core processors in a virtual modeling manner, and conducts research on the simulated multi-core processors modeled, so as to reduce the costs of research and experiments.

[0004] A multi-core processor modeling method based on AADL includes the following steps:

[0005] Establish multiple system components through AADL components for multiple different models of multi-core processors, and each system component corresponds to a different type;

[0006] At least establish a processor sub-component, a memory sub-component, a device sub-component, and an abstract sub-component inside the system component, and all system components and sub-components are configured with an interaction port port and a data component;

[0007] Obtain the parameters of the processor to be simulated and input them into the system component for simulation.

[0008] Advantageous Effects:

[0009] In view of the problem of the sharp increase in human input and huge financial expenditure required for current hardware experiments, the present invention proposes a method for modeling a multi-core processor based on AADL. The architecture analysis and design language AADL is used to model the multi-core processor. Different types of AADL components are established to model the overall multi-core processor and its internal parts. The established model can be used to effectively experiment on the capabilities of the multi-core processor from various dimensions such as latency, power consumption, reliability, and security on an open-source and free platform, without the need to invest a large number of hardware personnel and physical hardware during the experimental stage, thus liberating human resources and saving financial expenditure. Description of the Drawings

[0010] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0011] Figure 1 It is an AADL diagram of the overall structure of a multi-core processor provided by an embodiment of the present application;

[0012] Figure 2 It is an AADL diagram of the processor structure of a multi-core processor provided by an embodiment of the present application;

[0013] Figure 3 It is an AADL diagram of the FTC653 core structure of a multi-core processor provided by an embodiment of the present application;

[0014] Figure 4 It is an AADL diagram of the L3Cache structure of a multi-core processor provided by an embodiment of the present application;

[0015] Figure 5 It is an AADL diagram of the cluster structure of a multi-core processor provided by an embodiment of the present application. Detailed Embodiments

[0016] The embodiments of the present disclosure will be described in detail below with reference to the drawings.

[0017] The following describes the embodiments of the present disclosure through specific examples. Those skilled in the art can easily understand other advantages and effects of the present disclosure from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. The present disclosure can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present disclosure. It should be noted that, without conflict, the following embodiments and the features in the embodiments can be combined with each other. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present disclosure without creative efforts belong to the scope of protection of the present disclosure.

[0018] It should be noted that the following describes various aspects of the embodiments within the scope of the appended claims. It should be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is illustrative only. Based on the present disclosure, those skilled in the art should understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects described herein can be used to implement the device and / or practice the method. In addition, this device and / or this method can be implemented using other structures and / or functions in addition to one or more of the aspects described herein.

[0019] As Figure 1 shown in the AADL - based multi - core processor modeling method, includes the following steps:

[0020] S101: For multiple multi - core processors of different models, establish multiple system components through AADL components, and each system component corresponds to a different type. Specifically:

[0021] Establish a processor sub - component, including: the calculation rules and property sets customized by the AADL language. When the calculation rules and property sets customized by the AADL language cannot meet the calculation requirements, according to the actual situation, expand the property set that meets the AADL syntax, and meet the calculation by associating the expanded property set. The AADL component configures the interface for external data interaction, and pre - stores multiple calculation models and the rules for establishing the models. When the stored calculation models cannot meet the calculation requirements, import the externally input calculation models through the data interaction interface;

[0022] For the actual situation of the physical entity of the processor part, define the attribute names and assign attribute values within the processor sub-component, and establish a memory sub-component internally to model the memory entity inside the processor. Or, continue to establish a subordinate memory sub-component within the memory sub-component to model the sub-memory entity inside the memory entity;

[0023] S102: At least establish a processor sub-component, a memory sub-component, a device sub-component, and an abstract sub-component inside the system component. All system components and sub-components are configured with an interaction port port and a data component. Specifically:

[0024] Establish the device sub-component to model the physical entity of the device part in the multi-core processor. At least set a watchdog counter and a temperature sensor. Define the attribute names and assign attribute values within the device sub-component according to the actual situation of the physical entity of the device part. Establish the abstract sub-component to model the cluster structure in the multi-core processor, and the sub-component name can be determined according to the actual situation.

[0025] An interaction port port and a data component associated with the interaction port are established for the processor sub-component, memory sub-component, device sub-component, and abstract sub-component of the system component. The names of the interaction port port and the data component match the type of the multi-core processor being simulated. Among them: The system component and each sub-component include multiple inflow ports with different functions, multiple outflow ports with different functions, and multiple general-purpose ports with different functions. Among them:

[0026] Each inflow port is used for the inflow of the corresponding data type;

[0027] Each outflow port is used for the outflow of the corresponding data type;

[0028] The general-purpose port is used for the inflow and outflow of the corresponding data type;

[0029] When the type of the data component is consistent with the type of the inflow and outflow ports, a connection capable of data interaction can be established. The internal data flow of multiple processors has one-way transfer type and two-way transfer type;

[0030] Further, for the data stream to enter the system component corresponding to the multi-core processor model, the system component sends the data to the corresponding sub-component. And when the type of the data component is consistent with the types of the inflow and outflow ports, a data interaction path is formed, and a connection is established inside the system component. The connection name is determined according to the actual situation. The connection is divided into a unidirectional connection or a bidirectional connection. When establishing a unidirectional connection, the connection start point and the connection end point are determined;

[0031] When establishing a bidirectional connection, there is no need to distinguish between the source and the sink. The interactive ports as the source include outflow ports and general ports, or the interactive ports as the sink include inflow ports and general ports.

[0032] The connection is divided into a unidirectional connection and a bidirectional connection. Different types of connection models are established according to the objective distribution of physical entities to ensure the correctness of the data flow direction in the multi-core processor. Among them, when establishing a unidirectional connection model, the connection start point (abbreviated as "source") and the connection end point (abbreviated as "sink") are determined; Effect: When establishing a bidirectional connection, there is no need to distinguish between the source and the sink. The interactive ports that can be used as the source include outflow ports and general ports, or the interactive ports as the sink include inflow ports and general ports.

[0033] S103: Obtain the processor parameters to be simulated and input them into the system component for simulation.

[0034] Embodiment 1

[0035] The technical solution of the present invention: Provide a multi-core processor modeling method based on AADL. Taking a domestic multi-core processor as an example, the following main steps are described in detail:

[0036] Step 1: Apply the system component to model the overall structure of the multi-core processor.

[0037] Specifically, the domestic multi-core processor includes 1 main processor, 1 on-chip memory, 1 DDR3 memory, 1 DDR3L memory, 1 DDR4 memory, 1 SD2.0 memory, 1 QSPI memory, 2 watchdog counter devices, 1 temperature sensor device, and 1 cryptographic acceleration engine device. The overall structure of the domestic multi-core processor is modeled by the system component named S. The modeling within S is as follows: The processor component named P models the main processor, the memory components named OnChipMemory, DDR3, DDR3L, DDR4, SD2point0, and QSPI model the on-chip memory, DDR3 memory, DDR3L memory, DDR4 memory, SD2.0 memory, and QSPI memory respectively, the device components named WDT_01 and WDT_02 model the 2 watchdog counter devices respectively, and the device components named TempSensor and EncryptionAndDecryptionEngineTRNG model the temperature sensor device and the cryptographic acceleration engine device respectively. Connections are established through interaction ports according to the actual data flow. As Figure 1 shown.

[0038] Step 2: Model the processor part of the multi-core processor using the process component.

[0039] Specifically, the main processor includes 2 cluster structures and 1 L3Cache memory. The modeling of the main processor is shown in Step 1. The modeling within P is as follows: The abstract components named Cluster_01 and Cluster_02 are used to model the 2 cluster structures respectively, and the memory component named L3Cache models the L3Cache memory. Connections are established through interaction ports according to the actual data flow. As Figure 2 shown.

[0040] Specifically, the FTC663 core includes 1 L1Cache. The modeling of the FTC663 core is shown in Step 5. The modeling within FTC663 is as follows: The memory component named L1Cache is used to model the L1Cache memory. Connections are established through interaction ports according to the actual data flow. As Figure 3 shown.

[0041] Step 3: Model the memory part of the multi-core processor using the memory component.

[0042] Specifically, the modeling of on-chip memory, DDR3 memory, DDR3L memory, DDR4 memory, SD2.0 memory, and QSPI memory is described in Step 1. The modeling of L1Cache memory and L3Cache memory is described in Step 2. The modeling of L2Cache memory is described in Step 5.

[0043] Specifically, the L3Cache contains 8 Bank memories. The modeling within the L3Cache is as follows: Memory components with application names Bank_01, Bank_02, Bank_03, Bank_04, Bank_05, Bank_06, Bank_07, and Bank_08 are used to model the 8 Bank memories respectively. Connections are established through the interaction ports according to the actual data flow direction. As Figure 4 shown.

[0044] Specifically, the storage sizes of the Bank memory, L2Cache memory, L3Cache memory, and on-chip memory are 512KByte, 2MByte, 4MByte, and 128KByte respectively. Therefore, an attribute named Memory_Size is defined in the memory components named Bank_01, Bank_02, Bank_03, Bank_04, Bank_05, Bank_06, Bank_07, and Bank_08, with a value of 512KByte. An attribute named Memory_Size is defined in the memory component named L2Cache, with a value of 2MByte. An attribute named Memory_Size is defined in the memory component named L3Cache, with a value of 4MByte. An attribute named Memory_Size is defined in the memory component named OnChipMemory, with a value of 128KByte.

[0045] Step 4: Use the device component to model the device part of the multi-core processor.

[0046] Specifically, the modeling of the watchdog counter device, temperature sensor device, and cryptographic acceleration engine device is described in Step 1.

[0047] Step 5: Use the abstract component to model the cluster structure of the multi-core processor.

[0048] Specifically, the modeling of the cluster structure is shown in Step 2. The modeling within the cluster is as follows: The processor components with application names FTC663_01 and FTC663_02 respectively model two FTC663 cores, and the memory component named L2Cache models the L2Cache memory. Connections are established through the interaction ports according to the actual data flow direction. As Figure 5 shown.

[0049] Step 6: Use the data component and the interaction port port to ensure the correctness of the data type.

[0050] Specifically, this step runs through Steps 1 to 5. According to the actual data flow direction, specific types of interaction ports port need to be established within all components in Steps 1 to 5, and a strongly related data component is equipped for each interaction port.

[0051] Step 7: Use the interaction port port and the connection connection to ensure the correctness of the data flow direction.

[0052] Specifically, this step runs through Steps 1 to 5. According to the actual data flow direction, specific types of interaction ports port need to be established within all components in Steps 1 to 5, and appropriate interaction ports port are used as the source and sink of each connection connection.

[0053] Step 8: Check the inclusion relationship and the interaction connection relationship between components.

[0054] Specifically, referring to the physical composition structure of this domestic multi-core processor, check the inclusion relationship and the interaction connection relationship between components.

[0055] In summary, this application provides a method for modeling a multi-core processor based on AADL. Use the Architecture Analysis and Design Language AADL to model the multi-core processor, establish different types of AADL components such as system components, process components, memory components, device components, and abstract components to model the overall multi-core processor and various parts inside the multi-core processor, including the processor part, the memory part, the device part, the cluster structure, etc., establish interaction ports port, data components data, connections connection, etc. to ensure the type correctness and flow correctness of data transmission, and refer to the physical composition structure of the multi-core processor to check the inclusion relationship and the interaction connection relationship between components, in order to use the established model to experiment with the capabilities of the multi-core processor on an open-source and free platform, achieving the purpose of liberating human resources and saving financial expenditures.

[0056] As described above, this is only a specific implementation manner of the present disclosure. However, the protection scope of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed by the present disclosure should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A modeling method for multi-core processors based on AADL, characterized in that, It includes the following steps: For multiple multi-core processors of different models, establish multiple system components through AADL components, with each system component corresponding to a different model; Inside the system component, at least establish a processor sub-component, a memory sub-component, a device sub-component, and an abstract sub-component. All system components and sub-components are configured with an interactive port port and a data component. Among them, establishing the processor sub-component includes: configuring the interface for external data interaction by the AADL component, the calculation rules and property sets customized by the AADL language. When the calculation rules and property sets customized by the AADL language cannot meet the calculation requirements, according to the actual situation, expand the property set that meets the AADL syntax, and meet the calculation by associating the expanded property set; define the property name and assign the property value inside the processor sub-component according to the actual situation of some physical entities of the processor, and establish a memory sub-component for modeling the memory entity inside the processor. Or, continue to establish a subordinate memory sub-component in the memory sub-component for modeling the sub-memory entity inside the memory entity; The established device sub-component is used to model the physical entities of the device part in the multi-core processor, and at least set a watchdog counter and a temperature sensor. Define the property name and assign the property value inside the device sub-component according to the actual situation of the physical entities of the device part; establish an abstract sub-component and use it to model the cluster structure in the multi-core processor. The name of the abstract sub-component is set according to the actual situation; Obtain the processor parameters to be simulated and input them into the system component for simulation. The system component, the processor sub-component, the memory sub-component, the device sub-component, and the abstract sub-component all establish an interactive port port and a data component of the interactive port. The names of the interactive port port and the data component are matched according to the type of the actual multi-core processor being simulated. Among them: The system component and each sub-component each include multiple inflow ports with different functions, multiple outflow ports with different functions, and multiple general ports with different functions. Among them: Each inflow port is used for the inflow of the corresponding data type; Each outflow port is used for the outflow of the corresponding data type; The general port is used for the inflow and outflow of the corresponding data type; A connection for data interaction can be established only when the type of the data component is consistent with the types of the inflow and outflow ports; The system component is used for the data flow to enter the corresponding multi-core processor model. The system component sends the data to the corresponding sub-component. And when the type of the data component is consistent with the types of the inflow and outflow ports, a data interaction path is formed. A connection connection is established inside the system component, and the connection name is self-determined according to the actual situation; The said connection is divided into a unidirectional connection or a bidirectional connection. When establishing a unidirectional connection, the connection start point and the connection end point are determined; when establishing a bidirectional connection, there is no need to distinguish between the source and the sink. The interaction ports as the source include outflow ports and general ports, or the interaction ports as the sink include inflow ports and general ports.

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