Semiconductor substrate structures and devices

Abstract

The present invention provides a semiconductor substrate structure and device, comprising a substrate, a conductive column, a lateral insulating layer and a vertical insulating layer. Vertical electrical conduction can be achieved through the conductive column, and electrical insulation can be achieved through the lateral insulating layer and the vertical insulating layer. The semiconductor substrate structure of the present invention can realize 3D interconnection, has the advantages of strong process compatibility, flexible design, and suitability for high-temperature processes. It can be used as a substrate structure of an integrated circuit device to achieve isolation between circuit element structures, reduce parasitic capacitance between transistors or between leads, and enhance the radiation resistance of the device; it can also be used in the design of MEMS devices to achieve electrical lead-out of the device, simplify the packaging structure of the device, and enhance the array capability of the device; it can also be used in, for example, CMOS-MEMS monolithic integrated devices to improve device integration, reduce crosstalk between IC circuits and MEMS devices, and improve substrate utilization.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductors and relates to a semiconductor substrate structure and a device. Background Art

[0002] In the semiconductor field, single crystal silicon materials are usually used as substrates, and various semiconductor devices are prepared based on the single crystal silicon substrates. However, single crystal silicon substrates also have some technical limitations. Therefore, silicon on insulator (SOI) substrates are widely used as functional substrates because they have an intermediate insulating layer, which can provide an electrical isolation layer in IC integrated circuits, reduce device leakage current, strengthen device irradiation characteristics, and provide an etch stop layer in MEMS processes to increase process uniformity. However, the existing conventional SOI substrates only contain horizontal insulating layers and cannot be electrically conductive in the vertical direction.

[0003] With the improvement of the integration of semiconductor devices, more and more semiconductor devices need to be vertically electrically interconnected, that is, the components or structures on the front and back sides of the substrate need to be electrically interconnected through the substrate itself. The existing practice of vertical electrical interconnection is usually to use a through silicon via (TSV) substrate. However, the existing through silicon via technology is mostly achieved by etching deep holes on the substrate and filling them with electroplated metal. Such through silicon via substrates are only suitable for low-temperature processes below 500°C and are mostly used as electrical packaging substrates. They are not compatible with front-end high-temperature processes above 700°C; secondly, they only contain vertical insulation and conduction structures and do not have the advantages of SOI substrates. Summary of the invention

[0004] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a semiconductor substrate structure and device to solve the problem of substrate application limitations in the prior art.

[0005] To achieve the above objectives and other related objectives, the present invention provides a semiconductor substrate structure, comprising:

[0006] A substrate, the substrate comprising a first surface and an opposite second surface;

[0007] A conductive column, wherein the conductive column extends from the first surface of the substrate to the second surface of the substrate;

[0008] A lateral insulating layer, the lateral insulating layer is located in the substrate and is arranged at intervals or continuously in a lateral direction of the substrate;

[0009] A vertical insulating layer is located in the substrate, arranged at intervals along the vertical direction of the substrate, runs from the first surface of the substrate to the second surface of the substrate and is located at the periphery of the conductive column, and there is a spacing between the vertical insulating layer and the horizontal insulating layer.

[0010] Optionally, the material of the conductive pillar includes one or a combination of single crystal silicon, polycrystalline silicon, silicon dioxide, and silicon nitride; the resistivity of the conductive pillar is less than 5×10 -3 Ω·cm.

[0011] Optionally, the material of the substrate includes one or a combination of single crystal silicon, polycrystalline silicon, silicon carbide, diamond and III-V group semiconductors; the thickness of the substrate includes 100 μm to 800 μm.

[0012] Optionally, an angle between the transverse insulation layer and the vertical insulation layer is 30° to 150°.

[0013] Optionally, the cross-sectional shape of the conductive column includes one or a combination of a circle, an ellipse, an arc and a polygon; the cross-sectional shape of the lateral insulating layer includes one or a combination of a circle, an ellipse, an arc and a polygon; the cross-sectional shape of the vertical insulating layer includes one or a combination of a circle, an ellipse, an arc and a polygon.

[0014] Optionally, the material of the lateral insulating layer includes one or a combination of oxides, nitrides, carbides and polymers; the material of the vertical insulating layer includes one or a combination of oxides, nitrides, carbides and polymers; wherein the oxide includes silicon oxide, the nitride includes silicon nitride, and the carbide includes silicon carbide.

[0015] Optionally, the semiconductor substrate structure is suitable for a process temperature ranging from 25°C to 1200°C.

[0016] Optionally, in any of the above-mentioned semiconductor substrate structures, the lateral insulating layer is composed of a combination of an insulating dielectric shell and a cavity.

[0017] The present invention also provides a semiconductor device, which includes any of the above-mentioned semiconductor substrate structures.

[0018] Optionally, the semiconductor device includes one or a combination of a MEMS device or an integrated circuit device.

[0019] As described above, the semiconductor base structure of the present invention includes the substrate, the conductive pillars, the lateral insulating layer and the vertical insulating layer. The conductive pillars can be used to achieve vertical electrical conduction on the upper and lower surfaces of the substrate, the lateral insulating layer can be used to achieve isolation of the component structures on the upper and lower surfaces of the substrate, and the vertical insulating layer can be used to electrically insulate the conductive pillars from the substrate.

[0020] The semiconductor substrate structure of the present invention can realize 3D interconnection, and has the advantages of strong process compatibility, flexible design, and suitability for high-temperature processes. It can be used as a substrate structure of integrated circuit devices, such as CMOS, to achieve isolation between component structures in the circuit, reduce parasitic capacitance between transistors or between leads, and enhance the radiation resistance of the device; it can also be used in the design of MEMS devices to achieve electrical lead-out of the device, simplify the packaging structure of the device, and enhance the array capability of the device; it can also be used, for example, in CMOS-MEMS monolithic integrated devices to improve device integration, reduce crosstalk between IC circuits and MEMS devices, and improve substrate utilization. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 Shown is a schematic structural diagram of a semiconductor substrate structure provided in Embodiment 1 of the present invention.

[0022] Figure 2 Display as Figure 1 A schematic diagram of a partial top view of a semiconductor substrate structure.

[0023] Figure 3 Display as Figure 1 Another partial top view structural schematic diagram of the semiconductor substrate structure.

[0024] Figure 4 Shown is a schematic structural diagram of a semiconductor substrate structure provided in Embodiment 2 of the present invention.

[0025] Figure 5 Shown is a schematic diagram of the structure of an integrated circuit device provided in Embodiment 3 of the present invention.

[0026] Figure 6 Shown is a schematic structural diagram of a MEMS device provided in Embodiment 4 of the present invention.

[0027] Component number description

[0028] 100 Substrate

[0029] 101 lateral insulation layer

[0030] 1011 Insulating dielectric housing

[0031] 1012 Cavity

[0032] 102 Conductive Column

[0033] 103 Vertical insulation layer

[0034] 110 Integrated Circuit Components

[0035] 111 First MEMS Component

[0036] 112 Second MEMS element

[0037] 113 Rewiring Layer

[0038] 114 Electrical extraction electrode DETAILED DESCRIPTION

[0039] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0040] For example, when describing the embodiments of the present invention in detail, for the sake of convenience, the cross-sectional view showing the device structure will not be partially enlarged according to the general scale, and the schematic view is only an example, which should not limit the scope of protection of the present invention. In addition, in actual production, the three-dimensional space dimensions of length, width and depth should be included.

[0041] For ease of description, spatial relational terms such as "under", "below", "below", "below", "above", "on", etc. may be used herein to describe the relationship between an element or feature shown in the drawings and other elements or features. It will be understood that these spatial relational terms are intended to include other directions of the device in use or operation in addition to the directions depicted in the drawings. In addition, when a layer is referred to as being "between" two layers, it may be the only layer between the two layers, or there may be one or more intervening layers. Among them, when an element is referred to as being "fixed to" or "disposed on" another element, it may be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it may be directly connected to the other element or indirectly connected to the other element.

[0042] Here, expressions such as "between..." may be used, which indicates that the two end points are included, and expressions such as "plurality" may be used, which indicates two or more, unless otherwise clearly and specifically limited. In addition, the terms "first" and "second" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features.

[0043] It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and therefore the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0044] Embodiment 1

[0045] See also Figure 1 This embodiment provides a semiconductor base structure, which includes a substrate 100, a lateral insulating layer 101, a conductive column 102 and a vertical insulating layer 103.

[0046] The substrate 100 includes a first surface and an opposite second surface; the conductive pillars 102 extend from the first surface of the substrate 100 to the second surface of the substrate 100 to expose the opposite ends of the conductive pillars 102, so that the upper and lower surfaces of the substrate 100 can be vertically electrically connected through the conductive pillars 102; the lateral insulating layers 101 are located in the substrate 100 and are arranged at intervals along the lateral direction of the substrate 100 as shown in FIG. Figure 2 As shown, or arranged continuously along the lateral direction of the substrate 100 as shown Figure 3 As shown, the lateral insulating layer 101 can be used to isolate the component structures on the upper and lower surfaces of the substrate 100, and can define the distance from the lateral insulating layer 101 to the upper and lower surfaces of the substrate 100; the vertical insulating layer 103 is located in the substrate 100, and is arranged along the vertical intervals of the substrate 100, penetrating from the first surface of the substrate 100 to the second surface of the substrate 100, and surrounding the periphery of the conductive column 102. The vertical insulating layer 103 can realize electrical insulation between the conductive column 102 and the substrate 100, and there is a distance between the vertical insulating layer 103 and the lateral insulating layer 101, that is, the lateral insulating layer 101 and the vertical insulating layer 103 are independently arranged without contact with each other, so that the semiconductor base structure can have good mechanical properties and electrical properties.

[0047] As an example, the material of the substrate 100 may include one or a combination of single crystal silicon, polycrystalline silicon, silicon carbide, diamond, and Group III-V semiconductors.

[0048] Specifically, the material of the substrate 100 can be selected according to needs. For example, the substrate 100 can be a single-layer substrate, such as any one of a single crystal silicon substrate, a polycrystalline silicon substrate, a silicon carbide substrate, a diamond substrate and a III-V semiconductor substrate, or the substrate 100 is a composite laminated substrate, that is, it is composed of a stacked combination of two or more layers of different materials. Preferably, the thickness of the substrate 100 is 100μm to 800μm, such as 100μm, 200μm, 400μm, 600μm, 800μm, etc., which can be selected according to needs. Regarding the specific material and structure of the substrate 100, no excessive restrictions are made here.

[0049] As an example, the material of the lateral insulating layer 101 may include one or a combination of oxides, nitrides, carbides and polymers; the material of the vertical insulating layer 103 may include one or a combination of oxides, nitrides, carbides and polymers; wherein the oxide may include silicon oxide, the nitride may include silicon nitride, and the carbide may include silicon carbide.

[0050] Specifically, the material of the horizontal insulation layer 101 can be the same as or different from that of the vertical insulation layer 103, and there is no excessive restriction here. The specific type, size, distribution and morphology of the horizontal insulation layer 101 and the vertical insulation layer 103 can be selected as needed, and there is no excessive restriction here.

[0051] As an example, the angle between the transverse insulating layer 101 and the vertical insulating layer 103 is 30° to 150°.

[0052] Specifically, in order to shorten the transmission path and reduce the loss, the lateral insulation layer 101 is preferably arranged along the horizontal direction of the substrate 100, and the vertical insulation layer 103 is arranged perpendicular to the lateral insulation layer 101, so that there is a vertical angle between the lateral insulation layer 101 and the vertical insulation layer 103, but it is not limited to this. According to needs, the angle between the lateral insulation layer 101 and the vertical insulation layer 103 can also be 30°, 45°, 60°, 135°, 150°, etc., so as to provide a flexibly changeable 3D interconnected semiconductor substrate. The value of the angle between the lateral insulation layer 101 and the vertical insulation layer 103 is not excessively restricted here.

[0053] As an example, the material of the conductive pillar 102 may include one or a combination of single crystal silicon, polycrystalline silicon, silicon dioxide, and silicon nitride; wherein the resistivity of the conductive pillar 102 is less than 5×10 -3 Ω·cm.

[0054] Specifically, the material of the conductive pillar 102 is a doped silicon-based material, so as to provide the conductive pillar 102 with a low resistivity for electrical connection. The resistivity of the conductive pillar 102 is preferably less than 5×10 -3 Ω·cm, such as 4.5×10 -3 Ω·cm、2×10 -3 Ω·cm、1×10 -3 Ω·cm, etc. The material of the conductive pillar 102 is doped silicon rather than metal, such as copper metal, which can make the semiconductor substrate structure have a larger temperature adaptability range on the basis of satisfying electrical connection, so that the semiconductor substrate structure can be suitable for high temperature environment, such as processing technology above 700°C in semiconductor process, such as processing environment of 700°C, 800°C, 900°C, 1000°C, 1200°C, etc. Of course, the semiconductor substrate structure can also be suitable for normal temperature or low temperature environment, such as 25°C, 100°C, 200°C, 400°C, 500°C, 600°C, etc.

[0055] As an example, the shape of the cross section of the conductive pillar 102 may include one or a combination of a circle, an ellipse, an arc and a polygon; the shape of the cross section of the lateral insulating layer 101 may include one or a combination of a circle, an ellipse, an arc and a polygon; the shape of the cross section of the vertical insulating layer 103 may include one or a combination of a circle, an ellipse, an arc and a polygon.

[0056] Specifically, Figure 2 and Figure 3 , the shape of the cross section of the conductive pillar 102 can be circular, elliptical, arc-shaped, triangular, quadrilateral, hexagonal, etc. as required; similarly, the shape of the cross section of the lateral insulating layer 101 can include circular, elliptical, arc-shaped, triangular, quadrilateral, hexagonal, etc.; the shape of the cross section of the vertical insulating layer 103 can also include circular, elliptical, arc-shaped, triangular, quadrilateral, hexagonal, etc., which can be selected according to the needs, and no excessive restrictions are made here. The semiconductor base structure in this embodiment can provide the substrate 100 with a lateral isolation layer, reduce the leakage current of the device, strengthen the radiation characteristics of the device, and can be used as an etching stop layer to ensure the uniformity of etching; the conductive pillar 102 and the vertical insulating layer 103 can expand the applicable temperature range of the semiconductor base structure while implementing vertical electrical interconnection, especially high temperature process; the lateral insulating layer 101 and the vertical insulating layer 103 arranged at intervals can also make the semiconductor base structure have good mechanical properties and electrical properties.

[0057] Embodiment 2

[0058] See also Figure 4 This embodiment provides a semiconductor substrate structure, which is different from the first embodiment mainly in that the lateral insulating layer 101 in the semiconductor substrate structure is composed of an insulating medium shell 1011 and a cavity 1012. In this embodiment, the materials and structures of the substrate 100, the conductive pillar 102 and the vertical insulating layer 103 in the semiconductor substrate structure can all refer to the first embodiment, and will not be described in detail here.

[0059] The material of the insulating dielectric shell 1011 can be the same as the lateral insulating layer in the first embodiment, such as one or a combination of oxide and silicon nitride, and the oxide can include one or a combination of silicon oxide, aluminum oxide, titanium oxide, and hafnium oxide. The cavity 1012 can be a vacuum sealed cavity, and the vacuum degree of the cavity 1012 can be set as required. Of course, the cavity 1012 can also be only a sealed cavity, or an open cavity, which is not overly limited here. The specific size, distribution and morphology of the insulating dielectric shell 1011 and the cavity 1012 can be selected as required, which is not overly limited here.

[0060] Based on the first embodiment, the present embodiment provides the cavity 1012 so that the semiconductor substrate structure has a good heat dissipation channel and can be applied to devices such as integrated circuits, CMOS and MEMS, so as to expand the application range of the semiconductor substrate structure.

[0061] Embodiment 3

[0062] See also Figure 5 This embodiment provides a semiconductor device, which adopts the semiconductor substrate structure in the first embodiment. The semiconductor device includes the semiconductor substrate structure, an integrated circuit element 110 located on the first surface of the substrate 100, such as a CMOS, and a rewiring layer 113 located on the second surface of the substrate 100 and an electrical extraction electrode 114 electrically connected to the rewiring layer 113, so as to achieve electrical conduction in a vertical direction through the semiconductor substrate structure.

[0063] The types of device elements disposed on the semiconductor substrate structure are not limited thereto, and may be passive elements, such as resistors, capacitors, etc., or active elements, such as MEMS elements, or a combination of integrated circuit elements and MEMS elements, etc. The position of the rewiring layer 113 is also not limited thereto, and the rewiring layer 113 may also be disposed on the first surface of the semiconductor substrate structure or on two opposite surfaces of the semiconductor substrate structure at the same time, which is not limited here and may be disposed as required.

[0064] Embodiment 4

[0065] See also Figure 6 This embodiment provides a semiconductor device, which adopts the semiconductor substrate structure with the cavity 1012 in the second embodiment. The semiconductor device includes the semiconductor substrate structure, a first MEMS element 111 and a second MEMS element 112 located on the first surface of the substrate 100, and a rewiring layer 113 located on the second surface of the substrate 100 and an electrical extraction electrode 114 electrically connected to the rewiring layer 113, so as to achieve electrical conduction in a vertical direction through the semiconductor substrate structure.

[0066] The types of device elements disposed on the semiconductor substrate structure are not limited thereto, and may be passive elements, such as resistors, capacitors, etc., or active elements, such as integrated circuit elements, or a combination of integrated circuit elements and MEMS elements, etc. The position of the rewiring layer 113 is also not limited thereto, and the rewiring layer 113 may also be disposed on the first surface of the semiconductor substrate structure or on two opposite surfaces of the semiconductor substrate structure at the same time, which is not limited here and may be disposed as required.

[0067] To summarize, the semiconductor base structure of the present invention includes the substrate, the conductive pillars, the lateral insulating layer and the vertical insulating layer. The conductive pillars can be used to achieve vertical electrical conduction on the upper and lower surfaces of the substrate, the lateral insulating layer can be used to achieve isolation of the component structures on the upper and lower surfaces of the substrate, and the vertical insulating layer can be used to electrically insulate the conductive pillars from the substrate.

[0068] The semiconductor substrate structure of the present invention can realize 3D interconnection, and has the advantages of strong process compatibility, flexible design, and suitability for high-temperature processes. It can be used as a substrate structure of integrated circuit devices, such as CMOS, to achieve isolation between component structures in the circuit, reduce parasitic capacitance between transistors or between leads, and enhance the radiation resistance of the device; it can also be used in the design of MEMS devices to achieve electrical lead-out of the device, simplify the packaging structure of the device, and enhance the array capability of the device; it can also be used, for example, in CMOS-MEMS monolithic integrated devices to improve device integration, reduce crosstalk between IC circuits and MEMS devices, and improve substrate utilization.

[0069] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A semiconductor substrate structure, characterized in that: The semiconductor substrate structure comprises: A substrate, the substrate comprising a first surface and an opposite second surface; A conductive column, wherein the conductive column extends from the first surface of the substrate to the second surface of the substrate; A lateral insulating layer, the lateral insulating layer is located in the substrate, and is arranged at intervals or continuously along the lateral direction of the substrate, and the component structures located on the upper and lower surfaces of the substrate are isolated by the lateral insulating layer, and the distance from the lateral insulating layer to the upper and lower surfaces of the substrate can be defined; A vertical insulating layer is located in the substrate, arranged at intervals along the vertical direction of the substrate, runs from the first surface of the substrate to the second surface of the substrate and is located at the periphery of the conductive column, and there is a spacing between the vertical insulating layer and the horizontal insulating layer.

2. The semiconductor substrate structure according to claim 1, wherein: The material of the conductive column includes one or a combination of single crystal silicon, polycrystalline silicon, silicon dioxide, and silicon nitride; the resistivity of the conductive column is less than 5×10 -3 Ω•cm.

3. The semiconductor substrate structure according to claim 1, wherein: The material of the substrate includes one or a combination of single crystal silicon, polycrystalline silicon, silicon carbide, diamond and III-V group semiconductors; the thickness of the substrate includes 100μm~800μm.

4. The semiconductor substrate structure according to claim 1, wherein: The included angle between the transverse insulating layer and the vertical insulating layer is 30° to 150°.

5. The semiconductor substrate structure according to claim 1, wherein: The cross-sectional shape of the conductive column includes one or a combination of a circle, an ellipse and a polygon; the cross-sectional shape of the lateral insulating layer includes one or a combination of a circle, an ellipse and a polygon; the cross-sectional shape of the vertical insulating layer includes one or a combination of a circle, an ellipse and a polygon.

6. The semiconductor substrate structure according to claim 1, wherein: The material of the lateral insulating layer includes one or a combination of oxides, nitrides, carbides and polymers; the material of the vertical insulating layer includes one or a combination of oxides, nitrides, carbides and polymers; wherein the oxide includes silicon oxide, the nitride includes silicon nitride, and the carbide includes silicon carbide.

7. The semiconductor substrate structure according to claim 1, wherein: The process temperature applicable to the semiconductor substrate structure includes 25°C~1200°C.

8. The semiconductor substrate structure according to any one of claims 1 to 7, characterized in that: The transverse insulating layer is composed of an insulating medium shell and a cavity.

9. A semiconductor device, characterized in that: The semiconductor device comprises the semiconductor substrate structure according to any one of claims 1 to 8.

10. The semiconductor device according to claim 9, wherein: The semiconductor device includes one or a combination of a MEMS device or an integrated circuit device.

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