Semiconductor structure and forming method thereof, and memory

Abstract

The present disclosure discloses a semiconductor structure, a method for forming the same, and a memory device. The semiconductor structure comprises: a substrate; a bitline layer located within the substrate; a wordline stack located on the substrate, the wordline stack including a wordline layer; and a gap located between the bitline layer and the wordline layer. The present disclosure reduces parasitic capacitance between bitlines.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same, and a memory. Background Art

[0002] As the semiconductor industry develops, device critical dimensions continue to shrink. To achieve higher storage density, the line width of the capacitor needs to be reduced. However, reducing the line width also reduces the capacitance, further reducing the storage capacitance relative to the bit line parasitic capacitance, ultimately making the stored data signal indistinguishable. Summary of the Invention

[0003] Embodiments of the present disclosure provide a semiconductor structure, a method for forming the same, and a memory.

[0004] In a first aspect, an embodiment of the present disclosure provides a semiconductor structure, comprising:

[0005] substrate;

[0006] A bit line layer located in the substrate;

[0007] A word line stack layer is located on the substrate, and the word line stack layer includes a word line layer;

[0008] A gap is located between the bit line layer and the word line layer.

[0009] In an optional embodiment, the word line stack layer further includes:

[0010] a first insulating layer, located on the bit line layer;

[0011] a second insulating layer located below the word line layer;

[0012] The gap is located between the first insulating layer and the second insulating layer.

[0013] In an optional embodiment, the invention further comprises:

[0014] A word line isolation trench is located in the word line stack layer, and the word line isolation trench isolates two adjacent word lines;

[0015] The isolation layer is located in the word line isolation groove.

[0016] In an optional embodiment, the isolation layer is located on the wall of the word line isolation trench, and the isolation layer is a hollow structure.

[0017] In an optional embodiment, the semiconductor structure further includes:

[0018] A transistor is provided, wherein the transistor passes through the word line stack layer, the transistor comprises a source, a channel region and a drain sequentially stacked on the bit line, and the source of the transistor is connected to the bit line.

[0019] In a second aspect, an embodiment of the present disclosure provides a method for forming a semiconductor structure, comprising:

[0020] providing a substrate;

[0021] forming a bit line layer in the substrate;

[0022] forming a word line stack layer on the substrate, wherein the word line stack layer includes a word line layer;

[0023] A gap is formed between the bit line layer and the word line layer.

[0024] In an optional embodiment, forming a word line stack layer on the substrate includes:

[0025] forming a stack structure on the substrate, the stack structure comprising a first sacrificial layer, a second sacrificial layer and a dielectric layer, wherein the first sacrificial layer is closer to the bit line than the second sacrificial layer;

[0026] forming a word line isolation trench in the stack structure;

[0027] removing the second sacrificial layer through the word line isolation groove to form a word line trench;

[0028] forming a conductive layer through the word line isolation groove, wherein the conductive layer fills the word line trench and the word line isolation groove;

[0029] The conductive layer outside the word line trench is removed to form the word line layer.

[0030] In an optional embodiment, forming a word line stack layer on the substrate includes:

[0031] forming a stack structure on the substrate, the stack structure comprising a first sacrificial layer, a conductive layer, and a dielectric layer, wherein the first sacrificial layer is closer to the bit line than the conductive layer;

[0032] A word line isolation trench is formed in the stack structure, and the conductive layer separated by the word line isolation trench forms the word line layer.

[0033] In an optional embodiment, forming a gap between the bit line layer and the word line layer includes:

[0034] The first sacrificial layer is removed through the word line isolation trench to form the gap.

[0035] In an optional embodiment, after forming a gap between the bit line layer and the word line layer, the method further includes:

[0036] An isolation layer is formed in the word line isolation trench.

[0037] In an optional embodiment, before the word line isolation trench is formed in the stacked structure, the method further includes:

[0038] forming a transistor forming hole on the stack structure, wherein the bottom of the transistor forming hole exposes the bit line layer;

[0039] A transistor is formed in the transistor forming hole.

[0040] In an optional embodiment, forming a transistor in the transistor forming hole includes:

[0041] A transistor is formed in the transistor-forming hole by selective epitaxial growth.

[0042] In an optional embodiment, when epitaxial growth is performed on portions other than the portion corresponding to the second sacrificial layer, doping growth is performed separately to form doped portions.

[0043] In a third aspect, an embodiment of the present disclosure provides a memory comprising the semiconductor structure described in any of the above embodiments.

[0044] Embodiments of the present disclosure provide a semiconductor structure comprising a substrate having a bitline layer within the substrate, a wordline layer disposed on the substrate, and a gap between the bitline layer and the wordline layer. The gas or vacuum within the gap has a low dielectric constant, thereby eliminating coupling between the bitline layer and the wordline layer, thereby reducing bitline parasitic capacitance while meeting the trend toward smaller sizes.

[0045] The details of one or more embodiments of the present disclosure are set forth in the accompanying drawings and the description below. Other features and advantages of the present disclosure will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0047] Figures 1-6 Schematic diagrams of cross-sectional structures of different embodiments of the semiconductor structure according to the present disclosure are respectively shown;

[0048] Figures 7 to 20 Schematic diagrams of cross-sectional structures at various stages in the formation process of a semiconductor structure according to an embodiment of the present disclosure are shown;

[0049] Figure 21 A schematic flow chart of a method for forming a semiconductor structure according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0050] To help those skilled in the art better understand the present disclosure, the following clearly and completely describes the technical solutions in the embodiments of the present disclosure. Obviously, the described embodiments are only a portion of the embodiments of the present disclosure, not all of them. All other embodiments derived by those skilled in the art based on the embodiments of the present disclosure without creative effort are within the scope of protection of the present disclosure.

[0051] The terms "first," "second," and the like in the specification and claims of this disclosure and the accompanying drawings are used to distinguish between different objects, not to describe a particular order. Furthermore, the terms "including," "having," and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product, or apparatus comprising a series of steps or elements is not limited to the listed steps or elements but may optionally include steps or elements not listed, or may optionally include other steps or elements inherent to the process, method, product, or apparatus.

[0052] References herein to "embodiments" mean that a particular feature, structure, or characteristic described in connection with the embodiments may be included in at least one embodiment of the present disclosure. The appearance of this phrase in various places in the specification does not necessarily refer to the same embodiment, nor does it constitute an independent or alternative embodiment that is mutually exclusive of other embodiments. It is understood, both explicitly and implicitly, by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0053] like Figures 17 to 20 As shown, the embodiment of the present disclosure provides a semiconductor structure, including:

[0054] substrate 100;

[0055] The bit line layer 200 is located in the substrate 100;

[0056] A word line stack layer 300 is located on the substrate 100 , and the word line stack layer 300 includes a word line layer 310 ;

[0057] The gap 400 is located between the bit line layer 200 and the word line layer 310 .

[0058] The semiconductor structure provided by the embodiments of the present disclosure includes a substrate 100, a bitline layer 200 within the substrate 100, a wordline layer 310 on the substrate 100, and a gap 400 between the bitline layer 200 and the wordline layer 310. The semiconductor structure of the embodiments of the present disclosure has a gap 400 between the bitline layer 200 and the wordline layer 310. The gas or vacuum within the gap 400 has a low dielectric constant, which can effectively eliminate the mutual coupling between the bitline and the wordline, thereby reducing the parasitic capacitance of the bitline. This can further reduce the line width of the storage capacitor, meeting the development trend of small size.

[0059] Specifically, the substrate 100 may be, but is not limited to, a silicon substrate 100. For example, the material used for the substrate 100 may be any one or a mixture of silicon crystal, germanium crystal, a silicon-on-insulator structure, an epitaxial layer structure on silicon, a compound semiconductor, or an alloy semiconductor. Compound semiconductors may be any one or a mixture of silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, or indium dysprosium, and alloy semiconductors may be any one or a mixture of SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, or GaInAsP. This embodiment is described using a silicon substrate 100 as an example.

[0060] The substrate 100 also includes an isolation region 110. The isolation region 110 may be a shallow trench isolation structure. Materials for the shallow trench isolation structure may include silicon oxide, silicon nitride, and the like. The cross-sectional shape of the shallow trench isolation structure is not limited. For example, the cross-sectional shape of the shallow trench isolation structure may be trapezoidal. In other embodiments, the bottom of the shallow trench isolation structure is a curved surface, i.e., the bottom line of its cross-sectional shape is a concave arc.

[0061] In the semiconductor structure of the embodiment of the present disclosure, the word line stack layer 300 may further include an insulating layer in addition to the word line layer 310. The material of the insulating layer is not limited, and may be, for example, oxide or nitride.

[0062] In some embodiments, the wordline stack layer 300 further includes an insulating layer positioned between the wordline layer 310 and the bitline layer 200. The insulating layer between the wordline layer 310 and the bitline layer 200 may be one layer or two layers. When the insulating layer is one layer, the insulating layer may be closer to the bitline layer 200 relative to the gap 400, or closer to the wordline layer 310 relative to the gap 400. Providing an insulating layer between the wordline layer 310 and the bitline layer 200 can reduce bitline parasitic capacitance.

[0063] In an exemplary embodiment, the insulating layer includes a first insulating layer 330 and a second insulating layer 320. The first insulating layer 330 is located above the bit line layer 200. The second insulating layer 320 is located below the word line layer 310. A gap 400 is located between the first insulating layer 330 and the second insulating layer 320.

[0064] In some embodiments, see Figure 17 The semiconductor structure further includes a word line isolation trench 307. The word line isolation trench 307 is located in the stacked layer, and the word line isolation trench 307 isolates two adjacent word lines. Figure 19 and Figure 20 The word line isolation trench 307 includes an isolation layer 800. The isolation layer 800 is located in the word line isolation trench 307 to isolate the word line and reduce the parasitic capacitance of the word line.

[0065] The specific shape of the isolation layer 800 located in the word line isolation trench 307 is not limited.

[0066] In some embodiments, see Figure 19 , the isolation layer 800 fills the word line isolation groove 307, and the isolation layer 800 is a solid structure.

[0067] In some embodiments, see Figure 20 The isolation layer 800 is located on the wall of the word line isolation trench 307. The isolation layer 800 is a hollow structure. The hollow portion inside the isolation layer 800 has a lower dielectric constant, which can reduce parasitic capacitance.

[0068] In some embodiments, the semiconductor structure further includes a transistor 600. The transistor 600 penetrates the word line stack layer 300. The bottom of the transistor 600 is connected to the bit line. Figure 18 , the transistor 600 includes a source 630, a channel region 620, and a drain 610 stacked in sequence on the bit line. The source 630 of the transistor 600 is connected to the bit line. The transistor 600 can be formed by selective epitaxial growth and doping. The channel region 620 can be opposite to the word line layer 310, and the source 630 and the drain 610 can be doped with other elements according to specific circumstances. In an exemplary embodiment, the transistor 600 includes three parts from bottom to top, the source 630, the channel region 620, and the drain 610. The channel region 620 is opposite to the word line layer 310, the drain 610 is located above the channel region 620, the source 630 is located below the channel region 620, and the source 630 is in contact with the bit line.

[0069] The present disclosure provides a method for forming a semiconductor structure, which can be used to obtain any of the semiconductor structures described above. The following method embodiments can be used to understand the above semiconductor structures, and the above semiconductor structure embodiments can also be used to understand the following method for forming a semiconductor structure. Figure 21 FIG. 1 is a flow chart showing an embodiment of a method for forming a semiconductor structure disclosed herein. Figure 21 , the forming method comprises:

[0070] S100 provides a substrate 100;

[0071] S200 forms a bit line layer 200 in the substrate 100;

[0072] S300 forms a word line stack layer 300 on the substrate 100 , wherein the word line stack layer 300 includes a word line layer 310 ;

[0073] S400 forms a gap 400 between the bit line layer 200 and the word line layer 310 .

[0074] In the method for forming a semiconductor structure provided by the embodiments of the present disclosure, a bitline layer 200 is formed within a substrate 100, a wordline layer 310 is formed on the substrate 100, and a gap 400 is formed between the bitline layer 200 and the wordline layer 310. The semiconductor structure of the embodiments of the present disclosure forms a gap 400 between the bitline layer 200 and the wordline layer 310. The gas or vacuum within the gap 400 has a low dielectric constant, which removes the coupling between the bitline layer 200 and the wordline layer 310, effectively removing the mutual coupling between the bitline and wordline layers, and reducing the parasitic capacitance of the bitline. This can further reduce the line width of the storage capacitor, meeting the development trend of small size.

[0075] In the embodiments of the present disclosure, the provided substrate 100 may be, but is not limited to, a silicon substrate 100. For example, the material used for the substrate 100 may be any one or a mixture of silicon crystal, germanium crystal, silicon-on-insulator structure, epitaxial layer structure on silicon, compound semiconductor, or alloy semiconductor. Compound semiconductors may be any one or a mixture of silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, or indium dysprosium. Alloy semiconductors may be any one or a mixture of SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, or GaInAsP.

[0076] The method for forming a semiconductor structure according to the embodiment of the present disclosure further includes forming an isolation region 110 on the substrate 100. The isolation region 110 may be formed using a shallow trench isolation (STI) process.

[0077] In an exemplary embodiment, forming the isolation region 110 on the substrate 100 includes: forming a trench 104 on the substrate 100 ; and forming an isolation material layer 105 in the trench 104 .

[0078] See also Figure 1 The surface of the substrate 100 has an oxide layer 101 and a first hard mask layer 102 in sequence, and a first photoresist layer 103 is disposed on the first hard mask layer 102 .

[0079] In the specific implementation of forming the groove 104 on the substrate 100, a pattern is defined on the first photoresist layer 103, and the first hard mask layer 102 and the oxide layer 101 are sequentially etched using the patterned first photoresist layer 103 as a mask. Then, the substrate 100 is further etched using the patterned first hard mask layer 102 and the oxide layer 101 as masks to form the groove 104 on the substrate 100, and the first photoresist layer 103 is removed, thereby obtaining the following: Figure 2 The structure shown. The pattern defined by this structure can be defined directly by illumination, or the pattern can be defined by illumination first and then realized by pitch double method. Isolation material is injected into the groove 104 to form isolation material layer 105, and the result is as shown below. Figure 3 The structure shown in FIG. 1 is shown. The isolation material layer 105 and the first hard mask layer 102 outside the trench 104 are removed to form an isolation region 110 in the substrate 100. Figure 4 The structure shown.

[0080] In an exemplary embodiment, the isolation region 110 utilizes a shallow trench isolation structure. Materials for the shallow trench isolation structure may include silicon oxide, silicon nitride, or the like. The cross-sectional shape of the shallow trench isolation structure is not limited. For example, the cross-sectional shape of the shallow trench isolation structure may be trapezoidal. In other specific implementations, the bottom of the shallow trench isolation structure is a curved surface, i.e., the bottom line of its cross-sectional shape is a concave arc.

[0081] In some embodiments, forming the bit line layer 200 in the substrate 100 includes: forming an opening 210 in the substrate 100; and forming a bit line in the opening 210. The bit line layer 200 is composed of a plurality of bit lines.

[0082] In the specific implementation of forming the bit line layer 200 in the substrate 100, see Figure 5 , a second photoresist layer 106 is provided on the substrate 100, a pattern is defined on the second photoresist layer 106, and the oxide layer 101 is etched using the patterned second photoresist layer 106 as a mask, and the pattern of the second photoresist layer 106 is transferred to the oxide layer 101 to form an opening 210 exposing the substrate 100. The pattern defined by this structure can be directly defined by light irradiation, or the pattern can be defined by light irradiation first and then realized by a pitch double method. Ion implantation (IMP) is performed on the substrate 100 through the opening 210 to obtain the following: Figure 6 The structure shown is shown. A bit line is formed in the substrate 100, and the second photoresist layer 106 and the oxide layer 101 are removed to make the top surface of the substrate 100 flush with the top surface of the bit line layer 200, and the structure shown is shown. Figure 7 In the embodiment of the present disclosure, a plurality of bit lines constitute the bit line layer 200 .

[0083] In some embodiments, the semiconductor structure formation process includes forming a stacked structure on substrate 100. Based on the stacked structure, transistor 600, storage nodes, wordline structures, and the like can be further formed. In an exemplary embodiment, the stacked structure includes a first sacrificial layer 301, a second sacrificial layer 302, and a dielectric layer 340. The first sacrificial layer 301 is closer to the bit line than the second sacrificial layer 302. For example, the stacked structure can be an oxide layer-silicon nitride layer-oxide layer structure. The top oxide layer can form dielectric layer 340.

[0084] In a specific implementation of forming a stacked structure on a substrate 100, a first insulating layer 330, a first sacrificial layer 301, a second insulating layer 320, a second sacrificial layer 302 and a dielectric layer 340 are sequentially formed on the substrate 100 to obtain Figure 8 The structure shown.

[0085] In other exemplary embodiments, the second sacrificial layer in the stacked structure of the above-described embodiment may be replaced with a conductive layer 309. By forming wordline isolation trenches, the conductive layer can be separated into multiple wordlines, thereby forming a wordline layer. For example, the stacked structure formed on the substrate 100 may include a first sacrificial layer 301, a conductive layer 309, and a dielectric layer 340. The first sacrificial layer 301 is closer to the bitline than the conductive layer 309. In a specific implementation, the stacked structure formed on the substrate 100 may sequentially form a first insulating layer 330, a first sacrificial layer 301, a second insulating layer 320, a conductive layer 309, and a dielectric layer 340. Wordline isolation trenches are formed in the stacked structure, and the conductive layer 309 separated by the wordline isolation trenches forms a wordline layer. The wordline isolation trenches separate the conductive layer into multiple wordlines, forming a wordline layer.

[0086] In some embodiments, the semiconductor structure formation process includes forming a transistor 600. The transistor 600 is formed in the stacked structure. In an exemplary embodiment, the transistor 600 is formed before forming the wordline layer 310. Specifically, the transistor 600 may be formed before forming the wordline isolation trench 307 in the stacked structure.

[0087] In some embodiments, forming the transistor 600 includes: forming a transistor-forming hole 304 on the stacked structure, wherein the bottom of the transistor-forming hole 304 exposes the bit line layer 200. Forming the transistor 600 in the transistor-forming hole 304. The transistor 600 is connected to the bit line.

[0088] In forming a specific implementation of transistor 600, see Figure 9 A third photoresist layer 303 is provided on the stack structure, a pattern is defined on the third photoresist layer 303, and the stack structure is etched using the patterned third photoresist layer 303 as a mask to form a transistor forming hole 304 in the stack structure. The bottom of the transistor forming hole 304 exposes the bit line layer 200, and the third photoresist layer 303 is removed to obtain the following. Figure 10 The structure shown. The graphics defined by this structure can be defined directly by lighting, or the graphics can be defined by lighting first and then realized by the pitch double method.

[0089] In an exemplary embodiment, the transistor 600 is formed in the transistor forming hole 304 by selective epitaxial growth (SEG), and the transistor 600 is obtained as shown in FIG. Figure 11 The structure shown.

[0090] In some embodiments, transistor 600 includes a source 630, a channel region 620, and a drain 610 stacked sequentially on a bit line. Source 630 and drain 610 are formed by doping a semiconductor pillar formed by selective epitaxial growth within transistor-forming hole 304. In an exemplary embodiment, during epitaxial growth, corresponding portions of source 630 and drain 610 are doped and grown to form source 630 and drain 610, respectively. In an exemplary embodiment, the portion between bit line layer 200 and second sacrificial layer 302 is doped and grown to form source 630 of transistor 600, the portion above second sacrificial layer 302 is doped and grown to form drain 610 of transistor 600, and the portion opposite second sacrificial layer 302 forms channel region 620 of transistor 600. Drain 610 and source 630 can be doped with different elements as needed.

[0091] In some embodiments, forming a wordline stack layer 300 on a substrate 100 includes: forming a stack structure on the substrate 100; details of the stack structure may refer to the sections of other embodiments; forming a wordline isolation trench 307 in the stack structure; removing the second sacrificial layer 302 through the wordline isolation trench 307 to form a wordline trench 308; forming a conductive layer 309 through the wordline isolation trench 307, the conductive layer 309 filling the wordline trench 308 and the wordline isolation trench 307; and removing the conductive layer 309 outside the wordline trench 308 to form a wordline layer 310.

[0092] In the specific implementation of forming the word line stack layer 300 on the substrate 100, see Figure 12 , in order to clearly express the changes in semiconductor structure during the manufacturing process, Figure 12 The cross section and Figures 1-11 The cross section is perpendicular. A second hard mask layer 306 and a fourth photoresist layer 305 are sequentially arranged on the stack structure, a pattern is defined on the fourth photoresist layer 305, and the second hard mask layer 306 is further etched. The second hard mask layer 306 is etched using the patterned second hard mask layer 306 as a mask to form a word line isolation groove 307 in the stack structure. The word line isolation groove 307 exposes the stack structure and the substrate 100, and the following is obtained: Figure 13The structure shown. The pattern defined by this structure can be directly defined by light, or the pattern can be defined by light first and then realized by pitch double method. The second sacrificial layer 302 is removed through the word line isolation groove 307 to form the word line groove 308, and the fourth photoresist layer 305 and the second hard mask layer 306 are removed to obtain the following Figure 14 The conductive layer 309 is formed through the word line isolation groove 307, and the conductive layer 309 fills the word line trench 308 and the word line isolation groove 307 to obtain the structure shown in FIG. Figure 15 The conductive layer 309 outside the word line trench 308 is removed, including removing the conductive layer 309 in the word line isolation trench 307 and removing the conductive layer 309 on the top of the stacked structure to form a word line layer 310, and the structure shown is shown. Figure 16 The structure shown.

[0093] In other exemplary embodiments, for example, when the second sacrificial layer 302 in the stacked structure of the above embodiment is replaced with a conductive layer 309, the stacked structure formed on the substrate 100 may include a first sacrificial layer 301, a conductive layer 309, and a dielectric layer 340. The first sacrificial layer 301 is closer to the bit line than the conductive layer 309. In a specific implementation, the stacked structure formed on the substrate 100 may sequentially form a first insulating layer 330, a first sacrificial layer 301, a second insulating layer 320, a conductive layer 309, and a dielectric layer 340. Wordline isolation trenches are formed in the stacked structure, and the conductive layers separated by the wordline isolation trenches form wordline layers. The wordline isolation trenches separate the conductive layers into multiple wordlines, forming a wordline layer.

[0094] In some embodiments, the gap 400 is formed between the bit line layer 200 and the word line layer 310 by removing the first sacrificial layer 301 through the word line isolation trench 307 after removing the conductive layer 309 to form the gap 400. Figure 17 and Figure 18 The structure shown. Figure 17 and Figure 18 Schematic diagram of two corresponding structures with vertical cross sections.

[0095] In some embodiments, after forming the gap 400 between the bit line layer 200 and the word line layer 310, the method further includes forming an isolation layer 800 in the word line isolation trench 307. The isolation layer 800 is formed by depositing a dielectric material in the word line isolation trench 307. The isolation layer 800 seals the edge where the gap 400 meets the isolation layer 800.

[0096] In an exemplary embodiment, the isolation layer 800 fills the entire word line isolation trench 307, resulting in Figure 19 The structure shown.

[0097] In another exemplary embodiment, the isolation layer 800 is formed on the wall of the word line isolation trench 307. The isolation layer 800 is a hollow structure. Figure 20 The hollow portion inside the isolation layer 800 has a lower dielectric constant, which can reduce parasitic capacitance.

[0098] In the embodiments of the present disclosure, there is no limitation on the material of the sacrificial layer (including the first sacrificial layer 301 and the second sacrificial layer 302). For example, the sacrificial layer may be an oxide layer, a nitride layer, a carbon layer, etc. There is no limitation on the material of the hard mask layer (including the first hard mask layer 102 and the second hard mask layer 306). For example, the mask layer may be a silicon nitride layer.

[0099] In a third aspect, an embodiment of the present disclosure provides a memory comprising the semiconductor structure of any of the above embodiments.

[0100] The above are merely exemplary embodiments of the present disclosure and are not intended to limit the scope of the present disclosure. That is, any equivalent changes and modifications made in accordance with the teachings of the present disclosure are still within the scope of the present disclosure. Those skilled in the art will easily come up with other embodiments of the present disclosure after considering the specification and practicing the disclosure herein. The present disclosure is intended to cover any variations, uses or adaptations of the present disclosure, which follow the general principles of the present disclosure and include common knowledge or customary technical means in the art that are not recorded in the present disclosure. The description and examples are to be regarded as exemplary only, and the scope and spirit of the present disclosure are defined by the claims.

Claims

1. A semiconductor structure comprising: substrate; A bit line layer located in the substrate; A word line stack layer is located on the substrate, and the word line stack layer includes a word line layer; a first insulating layer, located on the bit line layer; a second insulating layer located below the word line layer; a dielectric layer, located on the word line layer; A transistor, the transistor comprising a source, a channel region, and a drain stacked sequentially on the bit line, the source penetrating the first insulating layer and the second insulating layer, the channel region penetrating the word line layer, the drain penetrating the dielectric layer, and the source connected to the bit line; and a gap located between the first insulating layer and the second insulating layer.

2. The semiconductor structure according to claim 1, wherein: Also includes: A word line isolation trench is located in the word line stack layer, and the word line isolation trench isolates two adjacent word lines; The isolation layer is located in the word line isolation groove.

3. The semiconductor structure according to claim 2, wherein: The isolation layer is located on the groove wall of the word line isolation groove, and the isolation layer is a hollow structure.

4. A method for forming a semiconductor structure, comprising: providing a substrate; forming a bit line layer in the substrate; forming a word line stack layer on the substrate, the word line stack layer including a word line layer, comprising: forming a stack structure on the substrate, the stack structure including a first sacrificial layer, a second sacrificial layer, and a dielectric layer, wherein the first sacrificial layer is closer to the bit line than the second sacrificial layer; forming a word line isolation trench in the stack structure; removing the second sacrificial layer through the word line isolation trench to form a word line trench; forming a conductive layer through the word line isolation trench, the conductive layer filling the word line trench and the word line isolation trench; and removing the conductive layer outside the word line trench to form the word line layer; Before forming the word line isolation trench in the stacked structure, the method further includes: forming a transistor, the transistor including a source, a channel region, and a drain sequentially stacked on the bit line; Forming a gap between the bit line layer and the word line layer includes: removing the first sacrificial layer through the word line isolation groove to form the gap, wherein the gap is in direct contact with the source and surrounds the source.

5. The method according to claim 4, characterized in that After forming a gap between the bit line layer and the word line layer, the method further includes: An isolation layer is formed in the word line isolation trench.

6. The method according to claim 5, characterized in that forming an isolation layer in the word line isolation trench, comprising: An isolation layer is formed on the groove wall of the word line isolation groove, and the isolation layer is a hollow structure.

7. The method according to claim 4, characterized in that Forming a transistor, including: forming a transistor forming hole on the stack structure, wherein the bottom of the transistor forming hole exposes the bit line layer; The transistor is formed in the transistor forming hole.

8. The method according to claim 7, characterized in that forming the transistor in the transistor forming hole, comprising: A transistor is formed in the transistor-forming hole by selective epitaxial growth.

9. The method according to claim 8, characterized in that The source and drain are formed by doping a semiconductor column formed by selective epitaxial growth.

10. A memory, characterized in that: It comprises the semiconductor structure according to any one of claims 1 to 3.

Images