A shielded gate trench MOSFET

Abstract

The present invention provides a shielded gate trench MOSFET, comprising, from bottom to top, an N-type heavily doped substrate, an N-type lightly doped epitaxial drift layer, a P-type diffusion region, and an N-type heavily doped diffusion region, a deep trench and a shallow trench being constructed vertically, a shield gate polysilicon and a control gate polysilicon being constructed in the deep trench and isolated from the trench edge by an isolation field oxide and gate oxide, respectively; a control gate polysilicon being constructed in the shallow trench and isolated from the trench edge by a gate oxide; a metal electrode is constructed in the device with isolation oxide, a trapezoidal metal electrode is constructed through the isolation oxide, the N-type lightly doped diffusion region, and the P-type diffusion region; a P-type heavily doped region is formed between the metal electrode and the P-type diffusion region; a source is formed at the top of the device, and a drain is formed at the bottom of the device. The present invention fully utilizes the principle that shallow trenches have greater anti-warping capabilities than deep trenches, and arranges the shallow trench for controlling device switching perpendicularly to the deep trench for charge balance. This arrangement improves the overall anti-warping capabilities of the device compared to the deep trench, which is arranged perpendicularly to the deep trench.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor power devices, and in particular relates to a shielded gate trench MOSFET. Background Art

[0002] Power semiconductor devices are widely used in DC-AC converters, DC-DC converters, intelligent power modules and other fields. Compared with traditional VDMOS, trench MOSFET has the characteristics of lower on-resistance, better voltage resistance and high channel density, making it the main product of discrete power devices on the market. However, trench MOSFET is similar to VDMOS and is also limited by the silicon limit. The emergence of superjunction VDMOS has broken the silicon limit, but its production process is complex and costly, so it is mostly used in high-voltage devices and has failed to replace the trench MOSFET market in the field of medium and low voltage devices. As an alternative structure to superjunction, shielded gate trench MOSFET has the characteristics of simple production process, low cost and good frequency characteristics compared to superjunction MOSFET. It has become the mainstream of high-end power devices in the low-voltage field and has even replaced conventional trench MOSFET in many fields.

[0003] The shielded-gate trench MOSFET is characterized by its two polysilicon gates: a control gate that controls the device's on / off state, and a shield gate that provides charge balancing. When the device is in the off state, under reverse bias, the shield gate acts as a field plate, providing a lateral electric field. This assists the longitudinal electric field formed by the reverse bias, completely depleting the drift region. The electric field distribution within the depletion region approximates a uniform electric field, resulting in a breakdown voltage that largely depends on the thickness of the drift region. However, the drift region concentration can be very high, effectively reducing device resistance.

[0004] The current capability of the shielded gate trench MOSFET depends on its channel density. Its predecessor, the trench MOSFET, can use a grid-like trench distribution to nearly double the channel density. However, because the trenches of the shielded gate trench MOSFET are wider and deeper than those of conventional trench MOSFETs, there is a probability that the device will experience wafer warpage during the production process. Wafer warpage can cause deviations in the center and edge processing dimensions during wafer processing, causing greater fluctuations in the device's electrical properties and reducing product yield. In severe cases, the wafer cannot continue subsequent processing or even damage the equipment. Therefore, if the shielded gate trench MOSFET's anti-warpage capability is improved, then a grid-like trench can be used to increase the current capability of the shielded gate trench MOSFET. Summary of the Invention

[0005] The problem to be solved by the present invention is that the shielded gate trench MOSFET is a vertical trench device. A main way to reduce the on-resistance of the device and improve the current capability is to increase the channel density through a grid-type trench. However, during the factory production process, the stress generated by the deep groove can cause the wafer to warp. The use of a grid-type trench will cause obvious warping in both directions of the wafer, significantly increasing the production risk and reducing the uneven distribution of device performance on the same wafer. It is also a major cause of the low yield rate of peripheral devices on the wafer. Therefore, under the premise of using a grid-type trench design, how to alleviate wafer warping becomes the main factor determining whether mass production can be achieved.

[0006] To achieve the above object, the technical solution of the present invention is as follows:

[0007] A shielded gate trench MOSFET comprises: an N-type heavily doped substrate 1, a drift layer 2 located on the N-type heavily doped substrate 1, a P-type diffusion region 3 on the drift layer 2, and an N-type heavily doped diffusion region 4 located on top of the P-type diffusion region 3; a metal electrode isolation oxygen 11 located on top of the N-type heavily doped diffusion region 4, a wedge-shaped metal electrode 12 extending through the metal electrode isolation oxygen 11 and the N-type heavily doped diffusion region 4 and the P-type diffusion region 3; a P-type heavily doped region 13 located between the N-type heavily doped diffusion region 4 and the P-type diffusion region 3; a source electrode 14 located at the top of the device and in contact with the wedge-shaped metal electrode 12; and a drain electrode 15 located at the bottom of the device and in contact with the N-type heavily doped substrate 1.

[0008] Take the line connecting any two adjacent mesas as section line AA'. Along the AA' cross-section, a deep trench 5 is provided inside the drift layer 2. The bottom of the deep trench 5 is close to the junction between the drift layer 2 and the N-type heavily doped substrate 1. An isolation field oxide 7 is provided at the bottom and sidewalls of the deep trench 5. The interior of the isolation field oxide 7 is provided with a shielding gate polysilicon 8. Above the shielding gate polysilicon 8 on both sides of the deep trench 5 is a control gate polysilicon 10. The sidewalls of the control gate polysilicon 10 are gate oxide layers 9.

[0009] The angle α between the BB' section and the AA' section is any value between 0 and 180 degrees. Along the cross-sectional direction of BB', a shallow trench 6 is provided inside the drift layer 2. The depth of the shallow trench 6 is deeper than the junction between the P-type diffusion region 3 and the drift layer 2. A control gate polysilicon 10 is provided in the shallow trench 6. Gate oxide layers 9 are provided on the sidewalls of the shallow trench on both sides of the control gate polysilicon 10.

[0010] As a preferred embodiment, the BB' section is perpendicular to the AA' section.

[0011] As a preferred embodiment, the width of the shallow groove 6 in the BB′ section is smaller than the width of the deep groove 5 in the AA′ section, and the number of the shallow grooves 6 is greater than the number of the deep grooves 5 .

[0012] As a preferred embodiment, the width of the control gate polysilicon 10 in the shallow trench 6 at the BB′ cross section is the same as the width of the control gate polysilicon 10 in the deep trench 5 at the AA′ cross section.

[0013] As a preferred embodiment, a plurality of shallow grooves 6 are added between the deep grooves 5 along the direction perpendicular to the AA′ cross section.

[0014] As a preferred method, three shallow grooves with different angles are set between adjacent deep grooves, forming angles of 60 degrees, 90 degrees, and 120 degrees with the deep grooves respectively, and the shallow grooves are spliced ​​together to form a hexagonal grid structure.

[0015] As a preferred embodiment, each doping type in the device structure is changed to opposite doping, that is, P-type doping is changed to N-type doping, and N-type doping is changed to P-type doping at the same time.

[0016] The beneficial effects of the present invention are as follows: the present invention reduces the trench stress of the device at the same channel density by dividing the channel of the grid-type shielded gate trench MOSFET into a deep trench for charge balance and a shallow trench for controlling the device, thereby reducing the wafer warping caused by the trench stress during the production of high-channel-density shielded gate trench MOSFET, improving the production stability and the uniformity of device performance on the same wafer, and being able to effectively stabilize the product yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a schematic diagram of the three-dimensional structure of the present invention.

[0018] Figure 2 for Figure 1 Schematic diagram of the cross section along the AA' direction;

[0019] Figure 3 for Figure 1 Schematic diagram of the cross section in the BB' direction;

[0020] Figure 4 A top view showing the channel structure of Example 1;

[0021] Figure 5 A top view showing the channel structure of Example 2;

[0022] Figure 6 A top view showing the channel structure of Example 3;

[0023] Figure 7 A top view showing the channel structure of Example 4;

[0024] Figure 8 A top view showing the channel structure of Example 5;

[0025] 1 is the N-type heavily doped substrate, 2 is the drift layer, 3 is the P-type diffusion region, 4 is the N-type heavily doped diffusion region, 5 is the deep trench, 6 is the shallow trench, 7 is the isolation field oxygen, 8 is the shielding gate polysilicon, 9 is the gate oxide layer, 10 is the control gate polysilicon, 11 is the metal electrode isolation oxygen, 12 is the wedge-shaped metal electrode, 13 is the P-type heavily doped region, 14 is the source electrode, and 15 is the drain electrode. DETAILED DESCRIPTION

[0026] The following describes the embodiments of the present invention through specific examples. Those skilled in the art will readily understand the other advantages and benefits of the present invention from the disclosure herein. The present invention may also be implemented or applied through various other specific embodiments, and the details in this specification may be modified or altered based on different viewpoints and applications without departing from the spirit of the present invention.

[0027] The present invention divides the trenches of the network-type trench SGT MOS into deep trenches that provide charge coupling capability and shallow trenches that provide conductive channels. This improves the device channel density while reducing the stress generated by the trenches during the device production process, thereby reducing wafer warpage, lowering the production breakage rate, and improving the finished product yield.

[0028] Example 1

[0029] like Figure 1 As shown, this embodiment provides a shielded gate trench MOSFET, comprising: an N-type heavily doped substrate 1, a drift layer 2 located on the N-type heavily doped substrate 1, a P-type diffusion region 3 on the drift layer 2, and an N-type heavily doped diffusion region 4 located on top of the P-type diffusion region 3; a metal electrode isolation oxygen 11 located on top of the N-type heavily doped diffusion region 4, a wedge-shaped metal electrode 12 penetrating the metal electrode isolation oxygen 11 and the N-type heavily doped diffusion region 4 and the P-type diffusion region 3, a P-type heavily doped region 13 located between the N-type heavily doped diffusion region 4 and the P-type diffusion region 3, a source electrode 14 located at the top of the device and in contact with the wedge-shaped metal electrode 12, and a drain electrode 15 located at the bottom of the device and in contact with the N-type heavily doped substrate 1;

[0030] like Figure 2 , take the line connecting two adjacent mesas as the section line AA', and along the AA' cross-sectional direction, a deep trench 5 is provided inside the drift layer 2, the bottom of the deep trench 5 is close to the junction of the drift layer 2 and the N-type heavily doped substrate 1, the bottom and sidewalls of the deep trench 5 are provided with an isolation field oxide 7, the interior of the isolation field oxide 7 is provided with a shielding gate polysilicon 8, and above both sides of the shielding gate polysilicon 8 in the upper part of the deep trench 5 are control gate polysilicon 10, and the sidewalls on both sides of the control gate polysilicon 10 are gate oxide layers 9;

[0031] like Figure 3As shown, the angle α between cross-section BB' and cross-section AA' is α, which can be any value between 0 and 180 degrees. In this embodiment, cross-section BB' is perpendicular to cross-section AA'. Along the cross-section BB', a shallow trench 6 is defined within drift layer 2. The depth of shallow trench 6 is deeper than the boundary between P-type diffusion region 3 and drift layer 2. Control gate polysilicon 10 is located within shallow trench 6, and gate oxide layer 9 is provided on the sidewalls of the shallow trench on both sides of control gate polysilicon 10.

[0032] Preferably, the doping types in the device structure are changed to opposite doping types, that is, P-type doping is changed to N-type doping, and N-type doping is changed to P-type doping at the same time.

[0033] This example works as follows:

[0034] During the production of shielded-gate trench MOSFETs, stress across the wafer can be roughly decomposed into two directions: along the trench and perpendicular to the trench. Assuming the trench is parallel to the Y-direction, stress in the X-direction is affected by the trench structure, resulting in differences in wafer thickness and morphology at the trench bottom, trench corners, and mesa tops. The trench corners, in particular, generate greater stress when contacting dissimilar materials in the crystal lattice and are more susceptible to deformation under stress, resulting in a greater impact on stress in the X-direction. Regarding stress in the Y-direction, due to the relatively uniform device structure along the trench, the stress across the wafer is similar to that of the wafer substrate. Furthermore, due to the trapezoidal mesa structure created by the trenches, the stress in the Y-direction is less significant. In summary, the stress impact on unidirectional trench SGTs during production primarily comes from the trench corners perpendicular to the trench, resulting in significant overall wafer deformation in the direction perpendicular to the trench.

[0035] During the production process of the grid-type groove SGT, the intersection of the grooves will produce multiple stress weak points around the mesa columns, causing the entire wafer to undergo large warping deformation in all directions. For the shielded gate trench MOSFET, the bottom depth of the control gate only needs to exceed the depth of the P-type diffusion region, and does not need to be as close to the bottom of the epitaxial layer as the shielding gate. At the same time, only a shielding gate array in one direction is needed to achieve the charge balance required by the device. Therefore, the present invention improves the wafer's anti-warping ability in the direction perpendicular to it by replacing the deep grooves in a certain direction of the traditional grid-type groove SGT with shallow grooves. During the production process, devices with such a structure can be produced in different directions on the same wafer, thereby improving the anti-warping ability in all directions and reducing wafer warping.

[0036] Example 2

[0037] like Figure 5As shown, the present invention is basically the same as Example 1, with the difference that the width of the shallow groove 6 in the BB' section is smaller than the width of the deep groove 5 in the AA' section, and the number of the shallow grooves 6 is greater than the number of the deep grooves 5. Since the width of the shallow grooves is reduced, the stress weakness caused by the shallow grooves is further alleviated, and at the same time, the number of shallow grooves enhances the current capacity of the device.

[0038] Example 3

[0039] like Figure 6 As shown, the present invention is substantially the same as Example 1, with the difference being that the width of the control gate polysilicon 10 in the shallow trench 6 at the BB' cross section is the same as the width of the control gate polysilicon 10 in the deep trench 5 at the AA' cross section. This improves the electrical uniformity of the control gates in the deep trench and the shallow trench while achieving the same results as Example 1.

[0040] Example 4

[0041] like Figure 7 As shown, the present invention is basically the same as Example 1, with the difference that multiple shallow trenches 6 are added between the deep trenches 5 along the direction perpendicular to the AA' cross section, thereby significantly improving the device current capacity at the expense of a small amount of anti-warpage capability.

[0042] Example 5

[0043] like Figure 8 As shown, the present invention is essentially the same as Example 1, with the difference being that three shallow trenches with different angles are set between adjacent deep trenches, forming angles of 60, 90, and 120 degrees with the deep trenches, respectively. The shallow trenches are connected to form a hexagonal grid structure. This reduces stress weak points in a single direction, while increasing the channel density and improving the current capability of the device.

[0044] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A shielded gate trench MOSFET, characterized in that include: An N-type heavily doped substrate (1), a drift layer (2) located on the N-type heavily doped substrate (1), a P-type diffusion region (3) on the drift layer (2), an N-type heavily doped diffusion region (4) located on the top of the P-type diffusion region (3); a metal electrode isolation oxygen (11) located on the top of the N-type heavily doped diffusion region (4), a wedge-shaped metal electrode (12) penetrating the metal electrode isolation oxygen (11) and the N-type heavily doped diffusion region (4) and the P-type diffusion region (3), a P-type heavily doped region (13) located between the N-type heavily doped diffusion region (4) and the P-type diffusion region (3), a source electrode (14) located at the top of the device and in contact with the wedge-shaped metal electrode (12), and a drain electrode (15) located at the bottom of the device and in contact with the N-type heavily doped substrate (1); Take the line connecting two adjacent mesas as the section line AA', and along the AA' section direction, a deep trench (5) is provided inside the drift layer (2), the bottom of the deep trench (5) is close to the junction of the drift layer (2) and the N-type heavily doped substrate (1), the bottom and sidewalls of the deep trench (5) are provided with an isolation field oxide (7), the interior of the isolation field oxide (7) is shielding gate polysilicon (8), and above both sides of the shielding gate polysilicon (8) at the top of the deep trench (5) are control gate polysilicon (10), and the sidewalls on both sides of the control gate polysilicon (10) are gate oxide layers (9); The angle between the BB' section and the AA' section is α, and α takes any value between 0 degrees and 180 degrees. Along the cross-sectional direction of BB', a shallow groove (6) is provided inside the drift layer (2). The depth of the shallow groove (6) is deeper than the junction between the P-type diffusion region (3) and the drift layer (2). A control gate polysilicon (10) is provided in the shallow groove (6), and a gate oxide layer (9) is provided on the sidewalls of the shallow groove on both sides of the control gate polysilicon (10).

2. The shielded gate trench MOSFET according to claim 1, wherein: Section BB' is perpendicular to section AA'.

3. The shielded gate trench MOSFET according to claim 1, wherein: The width of the shallow groove (6) in the BB' section is smaller than the width of the deep groove (5) in the AA' section, and the number of the shallow grooves (6) is greater than the number of the deep grooves (5).

4. The shielded gate trench MOSFET according to claim 1, wherein: The width of the control gate polysilicon (10) in the shallow trench (6) at the BB' cross section is the same as the width of the control gate polysilicon (10) in the deep trench (5) at the AA' cross section.

5. The shielded gate trench MOSFET according to claim 1, wherein: A plurality of shallow grooves (6) are added between the deep grooves (5) along the direction perpendicular to the AA' cross section.

6. The shielded gate trench MOSFET according to claim 1, wherein: Three shallow grooves with different angles are set up between adjacent deep grooves, forming angles of 60 degrees, 90 degrees, and 120 degrees with the deep grooves respectively. The shallow grooves are spliced ​​together to form a hexagonal grid structure.

7. The shielded gate trench MOSFET according to any one of claims 1 to 6, characterized in that: The doping types in the device structure are changed to opposite doping types, that is, P-type doping is changed to N-type doping, and N-type doping is changed to P-type doping at the same time.

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