A Real-time Ethernet System-on-Card Architecture

Abstract

The present invention belongs to the field of internal communication of a ship energy consumption management system, and specifically discloses a system-on-chip architecture of a real-time Ethernet card. A system-on-chip of an ARM+FPGA architecture is used as a main control chip, the ARM side completes the scheduling of a protocol stack, and uses a DDR controller to read and write data to a DDR storage chip to realize data caching, thereby completing data transmission with a host computer; a PRP redundant control module, a 1588 synchronization module and a PCIE‑DMA module are designed on the FPGA side to realize dual Ethernet redundant processing, high-precision clock synchronization and communication with a host computer between other nodes in the system, and the advantage of parallel processing of the FPGA side is utilized to greatly reduce the computing requirements of the ARM side, so that the ARM side can accelerate the calculation required for communication scheduling, thereby improving the efficiency and throughput of network communication; the present invention greatly improves the real-time performance, reliability and throughput of network communication of node equipment in the ship energy consumption management system.

Description

Technical Field

[0001] The present invention belongs to the field of internal communication of ship energy consumption management systems, and is a system-on-chip design architecture of a real-time Ethernet card developed to improve communication efficiency, communication reliability and data real-time performance between nodes of a ship energy system. Background Art

[0002] At present, most of the nodes in the ship energy consumption management system use industrial Ethernet for communication, and the nodes in the system will use dual-network redundant communication to improve the reliability of communication. However, as the number of device nodes in the system increases, the data traffic on the network is increasing. In order to avoid data congestion in the network and improve the real-time performance of data in the network, a real-time scheduling strategy needs to be added to the network. A typical strategy is to synchronize all nodes with the same clock reference. Each node sends data in different time slices within a communication macrocycle. In a communication macrocycle, each node only sends data once. Therefore, when the number of nodes in the system is determined, the length of the time slice determines the length of the communication macrocycle, thereby determining the efficiency and throughput of network communication. The length of the time slice depends on the time taken by the real-time Ethernet protocol stack to complete the network data sending and receiving tasks. In addition to completing the network data sending and receiving tasks, the real-time Ethernet card protocol stack also needs to complete tasks such as clock synchronization, dual network port redundant processing, and synchronization with the host computer. The completion of these tasks will generate a lot of software overhead and resource consumption, increase the time for the protocol stack to complete the sending and receiving tasks, and ultimately reduce the efficiency of communication in the network and affect the real-time performance of network data. Summary of the invention

[0003] In view of the above problems, the purpose of the present invention is to design an architecture based on ARM+FPGA heterogeneous system on chip, take advantage of the parallel high-speed computing of the on-chip FPGA side, and cooperate with the ARM side of the system on chip to improve the working efficiency of the real-time Ethernet protocol stack running on the system on chip, thereby improving the real-time, reliability and network throughput of the communication function between nodes of the ship energy consumption management system.

[0004] The present invention uses the ARM+FPGA heterogeneous system-on-chip as the main control chip for development and design, and uses the advantage of FPGA's parallel high-speed processing to complete the PCIE bridging function, dual-network redundant processing and IEEE1588 high-precision synchronization function, thereby reducing the computing requirements of the ARM side of the system-on-chip, so that the ARM side can shorten the time used for communication scheduling processing, thereby reducing the time slice time required for communication of each node, improving the efficiency and throughput of communication on the network, improving the real-time performance of data in the network, and using the dual network port redundancy mechanism to improve the reliability of communication.

[0005] In order to achieve the above object, the technical solution adopted by the present invention is: a real-time Ethernet card system architecture, including:

[0006] The FPGA side is used to complete the address mapping between the host computer and the network card DDR memory chip, so that the host computer can address the network card DDR memory chip and read and write data; process the data of the dual network ports to achieve the switching of the dual network port data; complete the clock synchronization of the network card according to the time difference and frequency difference between the local node clock and the master clock sent by the ARM side;

[0007] The ARM side is used to write the data required by the host computer received from Ethernet into the DDR storage chip, and according to the host computer instructions, take out the data that the host computer needs to send from the DDR and compose it into an Ethernet message, and send it within the time slice corresponding to this node; according to the timestamp recorded by the FPGA side, calculate the time difference and frequency difference between the clock of this node and the master clock, and send it to the FPGA side.

[0008] The FPGA end includes:

[0009] The PCIE-DMA module is used to receive and parse the PCIE data packet sent by the host computer to the mapped DDR memory chip address through the PCIE bus, write the parsed data to the DDR memory chip address mapped by the PCIE protocol through the DDR controller on the ARM side in DMA mode, and inform the network data transceiver scheduling module on the ARM side that new data is written through the PCIE interrupt; obtain the instruction of the network data transceiver scheduling module on the ARM side through the AXI bus, and trigger the host computer PCIE interrupt to inform the host computer that the DDR memory chip has new data to read; after receiving the instruction of the host computer to send a read data packet through the PCIE bus, parse the instruction, take the data of the corresponding address from the DDR memory chip through the DDR controller on the ARM side in DMA mode, and assemble it into a PCIE data packet and send it to the host computer;

[0010] The PRP redundancy processing module is used to receive the Ethernet message assembled by the Ethernet MAC controller on the ARM side when sending the Ethernet message, and copy the message to be sent into two copies, and according to the PRP redundancy algorithm, add message sequence numbers and different redundancy identifiers after the two Ethernet messages respectively, and then send them out in two ways; when receiving the Ethernet message, identify the message sequence numbers and redundancy identifiers of the two received Ethernet messages, determine the order of arrival of the messages with the same sequence number on the two Ethernets, keep the message that arrives first, remove the redundant tail, and then pass it to the Ethernet MAC controller on the ARM side;

[0011] The 1588 clock synchronization module is used to receive the message after the redundant tail is removed by the PRP redundancy processing module during the process of receiving Ethernet messages, identify the received PTP message, and record the corresponding timestamp according to the type of the PTP message, waiting for the synchronization calculation module on the ARM side to read it; in the process of sending Ethernet messages, receive the Ethernet message assembled by the Ethernet MAC controller, identify the PTP message to be sent, and record the corresponding timestamp according to the type of the PTP message, waiting for the synchronization calculation module on the ARM side to read it; adjust the time and frequency of the local clock according to the time difference and frequency difference calculated by the synchronization calculation module on the ARM side to maintain synchronization with the master clock.

[0012] The process of recording the timestamp by the 1588 clock synchronization module is between the Ethernet physical layer and the MAC layer.

[0013] The ARM side includes:

[0014] The network data transceiver scheduling module is used to determine whether the data is required by the host computer according to the node number information in the Ethernet message when the Ethernet message is received from the PRP redundant processing module on the FPGA side through the Ethernet MAC controller, and write the required data into the DDR storage chip through the DDR controller for the host computer to read; when there is data to be sent, the data to be sent is taken out from the specified position in the DDR, and its own node number information is added to form an Ethernet message, and the corresponding periodic sending time of the node is waited for to arrive, and the Ethernet message is sent out through the Ethernet MAC controller and the PRP redundant processing module in the corresponding time slice; the message required for PTPv2 protocol clock synchronization is sent in the corresponding non-periodic time period of the node;

[0015] The synchronization calculation module is used to identify the PTPv2 protocol message when receiving the Ethernet message through the Ethernet MAC controller, and read the corresponding timestamp from the 1588 clock synchronization module on the FPGA side through the AXI bus, compare it with the local time and calculate the time difference and frequency difference, and send it to the 1588 clock synchronization module on the FPGA side through the AXI bus.

[0016] A method for implementing a system architecture on a real-time Ethernet card comprises the following steps:

[0017] The FPGA end completes the address mapping between the host computer and the network card DDR memory chip, enabling the host computer to address the network card DDR memory chip and read and write data; processes the data of the dual network ports to achieve the switching of the dual network port data; completes the clock synchronization of the network card according to the time difference and frequency difference between the local node clock and the master clock sent by the ARM end;

[0018] The ARM side writes the data required by the host computer received from Ethernet into the DDR storage chip, and according to the host computer instructions, takes out the data that the host computer needs to send from the DDR and composes it into an Ethernet message, which is sent within the time slice corresponding to this node; according to the timestamp recorded by the FPGA side, the time difference and frequency difference between the clock of this node and the master clock are calculated and sent to the FPGA side.

[0019] The FPGA side performs the following steps:

[0020] The PCIE-DMA module receives and parses the PCIE data packet sent by the host computer to the mapped DDR memory chip address through the PCIE bus, writes the parsed data to the DDR memory chip address mapped by the PCIE protocol through the DDR controller on the ARM side in DMA mode, and informs the network data transceiver scheduling module on the ARM side that new data is written through the PCIE interrupt; obtains the instruction of the network data transceiver scheduling module on the ARM side through the AXI bus, and triggers the host computer PCIE interrupt to inform the host computer that the DDR memory chip has new data to read; after receiving the instruction to read the data packet sent by the host computer through the PCIE bus, parses the instruction, takes the data of the corresponding address from the DDR memory chip through the DDR controller on the ARM side in DMA mode, and assembles it into a PCIE data packet and sends it to the host computer;

[0021] When sending Ethernet messages, the PRP redundancy processing module receives Ethernet messages assembled by the Ethernet MAC controller on the ARM side, and copies the messages to be sent into two copies. According to the PRP redundancy algorithm, the message sequence numbers and different redundancy identifiers are added to the two Ethernet messages respectively, and then the messages are sent out in two ways. When receiving Ethernet messages, the message sequence numbers and redundancy identifiers of the two received Ethernet messages are identified, and the order of arrival of the messages with the same sequence numbers on the two Ethernet channels is determined. The message that arrives first is kept, and the redundant tail is removed before being passed to the Ethernet MAC controller on the ARM side.

[0022] When the 1588 clock synchronization module receives Ethernet messages, it receives the messages after the redundant tails are removed by the PRP redundancy processing module, identifies the received PTP messages, and records the corresponding timestamps according to the types of the PTP messages, waiting for the synchronization calculation module on the ARM side to read them; when sending Ethernet messages, it receives the Ethernet messages assembled by the Ethernet MAC controller, identifies the PTP messages to be sent, and records the corresponding timestamps according to the types of the PTP messages, waiting for the synchronization calculation module on the ARM side to read them; adjusts the time and frequency of the local clock according to the time difference and frequency difference calculated by the synchronization calculation module on the ARM side to maintain synchronization with the master clock.

[0023] The ARM side performs the following steps:

[0024] When the network data transceiver scheduling module receives the Ethernet message from the PRP redundant processing module on the FPGA side through the Ethernet MAC controller, it determines whether it is the data required by the host computer according to the node number information in the Ethernet message, and writes the required data into the DDR storage chip through the DDR controller for the host computer to read; when there is data to be sent, the data to be sent is taken out from the specified position in the DDR, and its own node number information is added to form an Ethernet message, and the corresponding periodic sending time of this node is waited for to arrive. In the corresponding time slice, the Ethernet message is sent out in sequence through the Ethernet MAC controller and the PRP redundant processing module; the message required for PTPv2 protocol clock synchronization is sent in the corresponding non-periodic time period of this node;

[0025] When the synchronization calculation module receives an Ethernet message through the Ethernet MAC controller, it identifies the PTPv2 protocol message and reads the corresponding timestamp from the 1588 clock synchronization module on the FPGA side through the AXI bus, compares it with the local time and calculates the time difference and frequency difference, and sends it to the 1588 clock synchronization module on the FPGA side through the AXI bus.

[0026] The advantages of the present invention are as follows:

[0027] 1) The ARM+FPGA heterogeneous system-on-chip is used as the main control chip, giving full play to the advantages of high-speed synchronous computing on the FPGA side, reducing the computing requirements on the ARM side, so that the ARM side can shorten the communication scheduling processing time, thereby reducing the time slice time required for communication at each node and improving the efficiency and throughput of communication on the network.

[0028] 2) Using the ARM+FPGA heterogeneous system-on-chip as the main control chip, compared with using two independent ARM chips and FPGA chips, the AXI bus inside the system-on-chip makes data communication between the ARM side and the FPGA side more convenient and efficient;

[0029] 3) Designing a PCIE-DMA module on the FPGA side of the system on chip can realize the direct mapping of the DDR memory chip address to the host processor storage space, making it easier for the host computer to directly read and write the DDR memory chip;

[0030] 4) Design a PCIE-DMA module on the FPGA side of the system on chip to complete data reading and writing with the DDR memory chip of the network card through DMA. The data transmission process does not require the participation of the ARM side software, saving the software overhead of the ARM side of the system on chip;

[0031] 5) Design a PRP redundant processing module on the FPGA side of the system on chip to implement dual-network redundant processing, which reduces the processing requirements on the ARM side while providing reliability of network communication;

[0032] 6) A 1588 synchronization module is designed on the FPGA side of the system on chip to obtain timestamps between the Ethernet MAC layer and the PHY layer, avoiding the impact of the software protocol stack's delay uncertainty on the accuracy of the PTPv2 synchronization calculation and improving the accuracy of clock synchronization. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 It is the internal composition of the node equipment of the ship energy consumption management system;

[0034] Figure 2 It is the hardware architecture and system-on-chip design diagram of the present invention. DETAILED DESCRIPTION

[0035] The present invention will be further described below in conjunction with the accompanying drawings.

[0036] The present invention belongs to the field of internal communication of ship energy consumption management system, and specifically discloses a system-on-chip architecture of a real-time Ethernet card. A system-on-chip of an ARM+FPGA architecture is used as a main control chip, the ARM end completes the scheduling of the protocol stack, and uses a DDR controller to read and write data to a DDR storage chip to realize data caching, so as to achieve data transmission with a host computer; the FPGA end designs a PRP redundant control module, a 1588 synchronization module and a PCIE-DMA module to realize dual Ethernet redundant processing, high-precision clock synchronization and communication with a host computer between other nodes in the system, and the advantage of parallel processing of the FPGA end is used to greatly reduce the computing requirements of the ARM end, so that the ARM end can accelerate the calculation required for communication scheduling, thereby improving the efficiency and throughput of network communication; the internal bus of the system-on-chip is used to make the communication between ARM and FPGA more efficient and convenient; the realization of the dual-network redundant processing function improves the reliability of network communication. The present invention greatly improves the real-time, reliability and throughput of network communication of node equipment in the ship energy consumption management system.

[0037] Real-time Ethernet cards are used in various node devices of ship energy consumption management systems, such as Figure 1As shown, the network card is used to realize the real-time Ethernet communication between the node device and other node devices in the system, and to communicate data with the host computer and other boards through the PCIE bus. The present invention selects ARM+FPGA heterogeneous system on chip (SOC) as the main control chip of the real-time Ethernet card, and uses the FPGA end of the system on chip to complete the address mapping between the network card DDR storage chip and the host computer based on the PCIE protocol, dual network redundancy processing and IEEE1588 high-precision synchronization function, and completes the scheduling calculation and clock synchronization calculation of the network communication on the ARM end of the system on chip. Such a system on chip design of the real-time Ethernet card utilizes the advantages of parallel and high-speed processing of the FPGA end of the system on chip, saves the software overhead of the ARM end of the system on chip, so that the ARM end has more software resources to complete the scheduling of the real-time Ethernet protocol stack, shortens the time that each node of the real-time Ethernet occupies the time slice in the communication macrocycle, improves the efficiency and throughput of communication in the internal network of the ship energy system, and improves the real-time nature of data in the network; the internal bus of the system on chip is used to complete the communication between the ARM end and the FPGA end, so that the communication between the two is more efficient and reliable. The present invention focuses on the design and development of the two parts of FPGA and ARM based on the system on chip. The overall architecture of the system on chip is as follows Figure 2 shown.

[0038] The FPGA side is used to realize redundant processing of dual network ports, clock synchronization, and data transmission with the host computer. Three modules are designed: PCIE-DMA module, PRP redundant processing module, and 1588 clock synchronization module.

[0039] The PCIE-DMA module, as a bridge module of the PCIE protocol, is used to complete the mapping of the NIC DDR memory chip to the host computer storage space, so as to realize the host computer's direct addressing access and data reading and writing to the NIC's DDR memory chip. The specific implementation process is as follows: when the host computer needs the NIC to send data to the network, the host computer sends a data packet to the mapped DDR memory chip address through the PCIE bus, the PCIE-DMA module parses the received PCIE data packet, writes the parsed data to the DDR memory chip address mapped by the PCIE protocol in DMA mode, and informs the ARM end of the system on chip through the PCIE interrupt that new data has been written; when the NIC receives new data from the network and needs to upload it to the host computer, the ARM end of the system on chip triggers the PCIE interrupt of the host computer through the PCIE-DMA module, notifying the host computer that the DDR memory chip has new data to read, and the host computer sends a command to read the data packet through the PCIE bus, the PCIE-DMA module parses the command, takes the data of the corresponding address from the DDR memory chip in DMA mode, and assembles it into a PCIE data packet and sends it to the host computer. During the entire process of data transmission with the host computer, the PCIE-DMA module reads and writes the DDR memory chip through DMA. The ARM-side network data transceiver scheduling module does not need to perform any intervention except sending PCIE interrupt instructions at the appropriate time, thus saving ARM-side software resource overhead.

[0040] The PRP redundancy processing module implements the dual Ethernet port redundancy processing function of the network card. When sending Ethernet messages, the data to be sent is assembled into Ethernet messages by the Ethernet MAC controller on the ARM side of the system on chip and then enters the PRP redundancy processing module. The PRP redundancy processing module copies the message to be sent into two copies, and according to the PRP redundancy algorithm, adds message sequence numbers and different redundancy identifiers after the two Ethernet messages and then sends them out in two ways; when receiving Ethernet messages, the message sequence numbers and redundancy identifiers of the two received Ethernet messages are identified, and the order of arrival of the messages with the same sequence number on the two Ethernet channels is determined. The message that arrives first is retained, and the redundant tail is removed and then passed to the Ethernet MAC controller on the ARM side of the system on chip. This redundancy processing method is transparent to the ARM side of the system on chip. Whether the ARM side is sending or receiving Ethernet messages, it does not need to consider the redundant processing of the message at all, saving the software computing overhead.

[0041] The 1588 clock synchronization module uses the high-precision crystal oscillator on the network card as the clock source to design a local clock timer, which serves as the time reference for the entire on-chip system. During the network reception process, after the message is processed by the PRP redundancy processing module, it bypasses and enters the 1588 clock synchronization module. The 1588 clock synchronization module can identify the received PTP message and record the corresponding timestamp according to the type of the PTP message; during the network transmission process, the message after the Ethernet MAC controller is framed bypasses and enters the 1588 clock synchronization module. The 1588 clock synchronization module can identify the PTP message to be sent and record the corresponding timestamp according to the type of the PTP message. The process of recording the timestamp by the 1588 clock synchronization module is between the Ethernet physical layer and the MAC layer, which can avoid the problem of poor timestamp accuracy caused by uncertain protocol stack delays. The module can adjust the time and frequency of the local clock according to the time difference and frequency difference calculated by the ARM end of the on-chip system to maintain synchronization with the master clock.

[0042] The ARM side of the system on chip is used to implement the scheduling of network data transmission and reception, as well as to calculate the time difference and frequency difference between the main clock and the clock. Two modules are designed: the network data transmission and reception scheduling module and the synchronization calculation module.

[0043] When receiving an Ethernet data frame, the network data transceiver scheduling module determines whether the data is required by the host computer based on the node number information in the Ethernet frame, and writes the required data into the DDR storage chip through the DDR controller for the host computer to read; when there is data to be sent, the network data transceiver scheduling module takes the data to be sent from the specified position in the DDR, adds its own node number information, forms an Ethernet frame, waits for the corresponding periodic sending time of this node to arrive, and sends the data frame through the Ethernet interface within the corresponding time slice; in addition, the message required for PTPv2 protocol clock synchronization is sent within the corresponding non-periodic time period of this node.

[0044] When receiving the Ethernet data frame, the synchronization calculation module identifies the PTPv2 protocol message, reads the corresponding timestamp from the 1588 clock synchronization module on the FPGA side, compares and calculates it with the local time, obtains the time difference and frequency difference, and then sends the calculation result to the 1588 clock synchronization module on the FPGA side through the AXI bus inside the on-chip system.

Claims

1. A real-time Ethernet card system architecture, characterized in that: include: The FPGA side is used to complete the address mapping between the host computer and the NIC DDR memory chip, so that the host computer can address the NIC DDR memory chip and read and write data; Process the data of dual network ports to realize the switching of dual network port data; The clock synchronization of the network card is completed according to the time difference and frequency difference between the local node clock and the master clock sent by the ARM end; The ARM side is used to write the data required by the host computer received from Ethernet into the DDR storage chip, and according to the host computer instructions, take out the data that the host computer needs to send from the DDR and compose it into an Ethernet message, and send it within the time slice corresponding to this node; According to the timestamp recorded by the FPGA end, the time difference and frequency difference between the local node clock and the master clock are calculated and sent to the FPGA end; The FPGA end includes: The PCIE-DMA module is used to receive and parse the PCIE data packet sent by the host computer to the mapped DDR memory chip address through the PCIE bus, write the parsed data to the DDR memory chip address mapped by the PCIE protocol through the DDR controller on the ARM side in DMA mode, and inform the network data transceiver scheduling module on the ARM side that new data is written through the PCIE interrupt; obtain the instruction of the network data transceiver scheduling module on the ARM side through the AXI bus, and trigger the host computer PCIE interrupt to inform the host computer that the DDR memory chip has new data to read; after receiving the instruction of the host computer to send a read data packet through the PCIE bus, parse the instruction, take the data of the corresponding address from the DDR memory chip through the DDR controller on the ARM side in DMA mode, and assemble it into a PCIE data packet and send it to the host computer; The PRP redundancy processing module is used to receive the Ethernet message assembled by the Ethernet MAC controller on the ARM side when sending the Ethernet message, and copy the message to be sent into two copies, and according to the PRP redundancy algorithm, add message sequence numbers and different redundancy identifiers after the two Ethernet messages respectively, and then send them out in two ways; when receiving the Ethernet message, identify the message sequence numbers and redundancy identifiers of the two received Ethernet messages, determine the order of arrival of the messages with the same sequence number on the two Ethernets, keep the message that arrives first, remove the redundant tail, and then pass it to the Ethernet MAC controller on the ARM side; The 1588 clock synchronization module is used to receive the message after the redundant tail is removed by the PRP redundancy processing module during the process of receiving Ethernet messages, identify the received PTP message, and record the corresponding timestamp according to the type of the PTP message, waiting for the synchronization calculation module on the ARM side to read it; in the process of sending Ethernet messages, receive the Ethernet message assembled by the Ethernet MAC controller, identify the PTP message to be sent, and record the corresponding timestamp according to the type of the PTP message, waiting for the synchronization calculation module on the ARM side to read it; adjust the time and frequency of the local clock according to the time difference and frequency difference calculated by the synchronization calculation module on the ARM side to maintain synchronization with the master clock.

2. A real-time Ethernet card system architecture according to claim 1, characterized in that: The process of recording the timestamp by the 1588 clock synchronization module is between the Ethernet physical layer and the MAC layer.

3. A real-time Ethernet card system architecture according to claim 1, characterized in that: The ARM side includes: The network data transceiver scheduling module is used to determine whether the data is required by the host computer according to the node number information in the Ethernet message when the Ethernet message is received from the PRP redundant processing module on the FPGA side through the Ethernet MAC controller, and write the required data into the DDR storage chip through the DDR controller for the host computer to read; when there is data to be sent, the data to be sent is taken out from the specified position in the DDR, and its own node number information is added to form an Ethernet message, and the corresponding periodic sending time of the node is waited for to arrive, and the Ethernet message is sent out through the Ethernet MAC controller and the PRP redundant processing module in the corresponding time slice; the message required for PTPv2 protocol clock synchronization is sent in the corresponding non-periodic time period of the node; The synchronization calculation module is used to identify the PTPv2 protocol message when receiving the Ethernet message through the Ethernet MAC controller, and read the corresponding timestamp from the 1588 clock synchronization module on the FPGA side through the AXI bus, compare it with the local time and calculate the time difference and frequency difference, and send it to the 1588 clock synchronization module on the FPGA side through the AXI bus.

4. A method for implementing a system architecture on a real-time Ethernet card, characterized in that: The following steps are involved: The FPGA completes the address mapping between the host computer and the NIC DDR memory chip, enabling the host computer to address the NIC DDR memory chip and read and write data; it processes the data of the dual network ports and implements the switching of the dual network port data; The clock synchronization of the network card is completed according to the time difference and frequency difference between the local node clock and the master clock sent by the ARM end; The ARM end writes the data required by the host computer received from Ethernet into the DDR storage chip, and according to the host computer instructions, takes out the data that the host computer needs to send from the DDR and composes it into an Ethernet message, which is sent within the time slice corresponding to this node; according to the timestamp recorded by the FPGA end, calculates the time difference and frequency difference between the clock of this node and the master clock, and sends it to the FPGA end; The FPGA side performs the following steps: The PCIE-DMA module receives and parses the PCIE data packet sent by the host computer to the mapped DDR memory chip address through the PCIE bus, writes the parsed data to the DDR memory chip address mapped by the PCIE protocol through the DDR controller on the ARM side in DMA mode, and informs the network data transceiver scheduling module on the ARM side that new data is written through the PCIE interrupt; obtains the instruction of the network data transceiver scheduling module on the ARM side through the AXI bus, and triggers the host computer PCIE interrupt to inform the host computer that the DDR memory chip has new data to read; after receiving the instruction to read the data packet sent by the host computer through the PCIE bus, parses the instruction, takes the data of the corresponding address from the DDR memory chip through the DDR controller on the ARM side in DMA mode, and assembles it into a PCIE data packet and sends it to the host computer; When sending Ethernet messages, the PRP redundancy processing module receives Ethernet messages assembled by the Ethernet MAC controller on the ARM side, and copies the messages to be sent into two copies. According to the PRP redundancy algorithm, the message sequence numbers and different redundancy identifiers are added to the two Ethernet messages respectively, and then the messages are sent out in two ways. When receiving Ethernet messages, the message sequence numbers and redundancy identifiers of the two received Ethernet messages are identified, and the order of arrival of the messages with the same sequence numbers on the two Ethernet channels is determined. The message that arrives first is kept, and the redundant tail is removed before being passed to the Ethernet MAC controller on the ARM side. When the 1588 clock synchronization module receives Ethernet messages, it receives the messages after the redundant tails are removed by the PRP redundancy processing module, identifies the received PTP messages, and records the corresponding timestamps according to the types of the PTP messages, waiting for the synchronization calculation module on the ARM side to read them; when sending Ethernet messages, it receives the Ethernet messages assembled by the Ethernet MAC controller, identifies the PTP messages to be sent, and records the corresponding timestamps according to the types of the PTP messages, waiting for the synchronization calculation module on the ARM side to read them; adjusts the time and frequency of the local clock according to the time difference and frequency difference calculated by the synchronization calculation module on the ARM side to maintain synchronization with the master clock.

5. A method for implementing a system architecture on a real-time Ethernet card according to claim 4, characterized in that: The ARM side performs the following steps: When the network data transceiver scheduling module receives the Ethernet message from the PRP redundant processing module on the FPGA side through the Ethernet MAC controller, it determines whether it is the data required by the host computer according to the node number information in the Ethernet message, and writes the required data into the DDR storage chip through the DDR controller for the host computer to read; when there is data to be sent, the data to be sent is taken out from the specified position in the DDR, and its own node number information is added to form an Ethernet message, and the corresponding periodic sending time of this node is waited for to arrive. In the corresponding time slice, the Ethernet message is sent out in sequence through the Ethernet MAC controller and the PRP redundant processing module; the message required for PTPv2 protocol clock synchronization is sent in the corresponding non-periodic time period of this node; When the synchronization calculation module receives an Ethernet message through the Ethernet MAC controller, it identifies the PTPv2 protocol message and reads the corresponding timestamp from the 1588 clock synchronization module on the FPGA side through the AXI bus, compares it with the local time and calculates the time difference and frequency difference, and sends it to the 1588 clock synchronization module on the FPGA side through the AXI bus.

Images