Apparatus and method for operating a source synchronous device

Abstract

The present invention describes circuits and methods for operating the circuits using a gated DQS signal to gate DQ signals. Some aspects are directed to a gating scheme to selectively pass a received strobe signal, such as a DQS strobe signal, based on the state of a driver enable (DE) signal in a driver circuit in an ATE, thereby preventing edges generated by the driver circuit from erroneously gating a received data signal, such as a DQ signal.

Description

Background Art

[0001] Electronic components such as semiconductor devices, circuits, and printed circuit board (PCB) assemblies are frequently tested during and after their manufacture using test systems such as automated test equipment (ATE). To perform these tests, the ATE may include instruments that generate or measure test signals, allowing a range of operating conditions to be tested on a particular device under test (DUT). For example, the instrument may generate a pattern of digital signals to drive the digital logic within the semiconductor device. The instrument may also receive digital signals from the semiconductor device to check whether the signal emitted by the DUT is correct. For many types of DUTs, checking the signal requires confirming that the signal has the expected value and that it occurs at the expected time.

[0002] Some devices that may be tested are designed to operate as part of a system in which one or more signals act as a clock. When operating correctly, these devices transmit or sense signals at known times relative to changes in the clock signal. These devices can be tested using ATE that generates a clock and uses this clock in conjunction with generating and measuring signals sent to and from the DUT. In this way, the ATE can generate and measure signals with appropriate timing relative to the clock.

[0003] Some devices that may be tested transmit data signals at times relative to a strobe signal that the device sending the data may generate. This gating scheme can be used, for example, in semiconductor memory or other high-data-rate applications where differences in the propagation times of the data signal and the clock signal can cause the clock signal to arrive at a device well before or after the data signal, potentially leading to errors in sensing the data signal. For devices that transmit strobes, known as source-synchronous devices, the data and strobe signals are transmitted in parallel with each other, so the difference in the time required for the data and strobe signals to reach another device can be minimal, reducing the chance that a device sensing data at a certain time based on the strobe signal will sense an incorrect data value.

[0004] For many source synchronous devices, the data strobe line is bidirectional, where the device uses the signal on the strobe line to sense data from another semiconductor device to determine when to sense the value on the data line. Conversely, the device can generate a signal on the strobe line to indicate when it is transmitting data on the data line, so that the other device has an indication of when to sense the value on the data line.

[0005] To test source synchronous devices, the ATE can couple a strobe line to the control input of a channel equipped with a receiver to control the timing of the receiver. When strobed, the receiver can record a signal on a data line coupled to the data input of the receiver. The ATE can also couple a channel equipped with a driver circuit to the strobe line. Whenever another driver in the ATE is driving a data signal on the data line, the driver can be controlled to transmit a signal that operates as a strobe signal. The ATE can be programmed to discard any data value sensed on the data line in response to the strobe signal transmitted from the ATE, so that the ATE processes the signal from the DUT and ignores the signal transmitted by the ATE on the data line. Summary of the Invention

[0006] Aspects of the present disclosure relate to apparatus and methods of operating the apparatus for selectively passing a received strobe signal, such as a DQS strobe signal, based on a state of a driver enable (DE) signal in a driver circuit in an ATE.

[0007] According to some embodiments, a device for synchronizing data received from a semiconductor device with a strobe signal is provided. The device includes: a first connection point configured to connect to a strobe signal pin of the semiconductor device; a second connection point configured to connect to a data pin of the semiconductor device; and a driver circuit having an output coupled to the first connection point and a drive enable input. The driver circuit is configured to drive the output during a drive enable cycle based on the state of a signal at the drive enable input. The device also includes a receiver circuit having a data input and a strobe input. The data input is coupled to the second connection point, and the receiver circuit is configured to receive data at the data input based on the state of the signal at the strobe input. The device also includes a gating circuit having an input coupled to the first connection point, an output coupled to the strobe input of the receiver circuit, and a control input coupled to the drive enable input. The gating circuit is configured to selectively pass a signal from its input to its output based on the state of a signal at its control input.

[0008] According to some embodiments, a method for source synchronization with a semiconductor device is provided. The method includes: enabling a driver to drive a gate line of the semiconductor device during a drive enable period of a drive enable signal; receiving a gate signal from the semiconductor device on the gate line; generating a gated gate signal from the received gate signal on the gate line based on the drive enable signal; and gating a receiver based on the gated gate signal to record a received data signal on a data line of the semiconductor device.

[0009] According to some embodiments, a method for operating automated test equipment (ATE) to test semiconductor devices is provided. The ATE includes a driver circuit having an output coupled to a gate line of the semiconductor device, a receiver circuit, and a gating circuit having an input coupled to the gate line. The method includes: enabling the driver circuit to drive the gate line during a drive enable period of a drive enable signal; receiving a gating signal from the semiconductor device at an input of the gating circuit; generating a gated gating signal using the gating circuit based on the received gating signal and the drive enable signal; and gating the receiver circuit based on the gated gating signal to record a data signal on the data line of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Various aspects and embodiments will be described with reference to the following figures. It should be understood that the figures are not necessarily drawn to scale. In the figures, each identical or nearly identical component shown in different figures is represented by the same reference numeral. For clarity, not every component is labeled in every figure.

[0011] Figure 1 is a schematic diagram of an embodiment of an automated test system in which strobe signals are processed according to aspects of the present application for testing source synchronous semiconductor devices;

[0012] Figure 2 is a schematic diagram illustrating an apparatus for testing a DUT according to some embodiments;

[0013] Figure 3 It shows that Figure 2 Schematic diagram of an exemplary implementation of an apparatus for testing a DUT is shown;

[0014] Figure 4 Shown Figure 3 Schematic timing diagram of several signals in the illustrated embodiment. DETAILED DESCRIPTION

[0015] Described herein are circuits and methods for accurately testing source synchronous devices under test (DUTs) in ATE, including those operating at high speeds.

[0016] When testing a semiconductor device under test (DUT), the ATE may alternate between driving data and receiving data at the data pins. For a source synchronous device under test, the ATE provides a strobe signal to the semiconductor device when the ATE is driving the data line connected to the DUT. Conversely, the DUT should provide a signal on the strobe line when the ATE is receiving data on the data line data from the DUT. The inventors have recognized and understood that in conventional test systems, when the ATE is configured to receive data from the DUT, the signal on the strobe line may undesirably include an edge generated by the ATE when driving data on the data line. Affecting the signal on the strobe line in this way may interfere with the accuracy of the test of the DUT because the ATE may sense data at a time when the data from the DUT is not on the data line. By sensing the signal on the data line at an incorrect time, the ATE may incorrectly determine that the DUT is not operating correctly.

[0017] Various aspects of the present disclosure relate to gating a signal on a gate line of a device under test (DUT) based on the state of a drive enable (DE) signal in a driver circuit in an ATE device that drives the gate line. The gated gate signal can be provided as a gate input to a receiver connected to a data line. The gate selectively passes the received gate signal so that the receiver is not inadvertently triggered to sense a signal on the data line that is not driven by the DUT. The rising and / or falling edges of the drive enable signal can be delayed before it is used to gate the signal on the gate line. Such techniques can be used to test certain semiconductor memories to selectively gate a signal on a DQS line to a gate input of a receiver connected to a DQ line.

[0018] In some embodiments, the ATE includes a driver circuit, a receiver circuit, and a gating circuit. The ATE can be configured so that the driver circuit is connected to a gate line of the DUT. The receiver circuit can be connected to a data line of the DUT. When the ATE is driving data (to the DUT) on the data line, the driver circuit can be controlled to generate a gate signal on the gate line to signal the DUT when to sense the data on the data line. Conversely, when the DUT is generating data to be received by the ATE, the DUT, if operating correctly, can generate a gate signal on the gate line.

[0019] A receiver connected to a data line can be gated by a gated select signal generated in a gating circuit. The gating circuit can receive a signal on a gate line of the DUT and generate the gated select signal by selectively passing the received select signal to a driver circuit based on the state of a drive enable (DE) signal. At other times, at least during a gated duration, the gating circuit can block the received select signal so that it is not coupled to the gate input of the receiver. When the received select signal is blocked during the gated duration, the gating circuit can set the gated select signal to a value that does not cause the receiver to sense the data line, such as a logic low value or a tri-state, during the gated duration.

[0020] In some embodiments, the gate duration can be set to include at least the beginning of the receive interval to block the strobe signal from the driver circuit when the driver circuit is switching from the enabled state to the disabled state. The gate duration can be set to end at a time determined by delaying the first edge of the DE signal indicating the enable to disable transition. Similarly, the gate duration can be set to include at least the ending of the receive interval to block the strobe signal from the driver circuit when the driver circuit is switching from the disabled state to the enabled state. The gate duration can be set to start at a time determined by delaying the second edge of the DE signal indicating the disable to enable transition.

[0021] The above aspects and embodiments, as well as additional aspects and embodiments, are further described below. These aspects and / or embodiments may be used alone, together, or in any combination of two or more, as this patent application is not limited in this regard.

[0022] Figure 1 is a schematic diagram of an example embodiment of an automated test system that can be configured to control the reception of source-synchronous data using the techniques described herein. Figure 1 A test setup 10 is shown that includes a test computer 12 that controls a tester 16 to perform tests on a device under test (DUT) 20 according to the methods disclosed herein. In some cases, the tester 16 can be automated test equipment (ATE) that includes driver circuits and receiver circuits configured as known in the art. A driver can drive a signal at its output while a signal connected to its drive enable input is asserted. A receiver can sense the value of a signal at its input in response to a signal connected to its strobe input being asserted. The function of each driver and receiver can be controlled by a test program loaded into the tester 16. The test program can be written to apply test signals to the DUT 20 and record the responses. The recorded responses can be processed to determine whether the DUT 20 is operating according to its specified design.

[0023] DUT 20 can be any suitable device for testing. DUT 20 can be a semiconductor device, and in some embodiments can be a memory device. DUT 20 can be a random access memory (RAM), dynamic RAM (DRAM), static RAM (SRAM), synchronous dynamic RAM (SDRAM), double data rate (DDR) SDRAM, non-volatile memory such as erasable programmable read-only memory (EPROM), NAND flash memory, NOR flash memory, or any other type of memory device. It should be understood that DUT 20 does not have to be a single-purpose semiconductor device, and in some embodiments can be a package of more than one semiconductor component, such as a system on a chip (SOC) that includes a memory device as part of the package. In the embodiments described herein, DUT 20 can be a source synchronous device and can have data lines and associated strobe lines. One or more drivers and / or receivers of ATE can be connected to each line of the DUT for generating and measuring signals on the lines of the DUT 20 during testing.

[0024] exist Figure 1 In the embodiment of the present invention, ATE 16 may include circuitry for generating and / or measuring multiple test signals 14 for DUT 20. ATE 16 may include multiple instruments configured to generate or measure different types of analog or digital signals. ATE 16 may include one or more timing generators configured to synchronize the generation of multiple test signals within different channels. In some embodiments, ATE 16 may include a programmable delay line for delaying a signal for each of a plurality of timing signals that controls each of the plurality of test signals, as described in more detail below.

[0025] It should be understood that Figure 1 is a greatly simplified representation of an automated test system. For example, although not shown, test system 10 may include control circuitry to control the operation of instruments within ATE 16. Additionally, test system 10 may include processing circuitry to process measurement results and determine whether DUT 20 is operating correctly. Furthermore, although Figure 1 A scenario is shown in which a single DUT 20 is being tested, but the test system 10 can be configured to test multiple devices. Regardless of the number of instruments or other components that generate or measure test signals and the number of devices under test, the test system 10 can include signal delivery components that route signals between the DUT 20 and the instruments within the ATE 16.

[0026] In addition, it should be understood that the other components shown in the figure are exemplary and not limiting. For example, although the test computer 12 is Figure 11 is shown as a personal computer (PC), but it should be understood that any suitable computing device can be used to implement the test computer, such as a mobile device or a computer workstation. The test computer 12 can be connected to a network and can access resources through the network and / or communicate with one or more other computers connected to the network.

[0027] Figure 2 is a schematic diagram illustrating an apparatus 100 for testing a DUT 20 according to some embodiments. In this example, the apparatus 100 may be a circuit within the ATE 16. For example, the apparatus 100 may be part of a test instrument within the ATE and may be implemented in the form of pin electronics (PE) and / or a timing generator. The PE may include separate components or may be implemented as one or more integrated circuits (ICs) including a large number of transistors.

[0028] The DUT 20 may be a semiconductor device and has a data pin 22 and a strobe signal pin 24. In this example, the pins 22 and 24 are shown as being located on the periphery of the DUT 20. However, the pins 22 and 24 may represent any location that can be connected to the circuitry of the DUT 20. In the case where the DUT 20 is a packaged part, the pins 22 and 24 may be leads extending from the semiconductor device package DUT 20. In embodiments where the DUT 20 is tested while a portion of a wafer is being tested, the pins 22 and 24 may represent pads or test points within the DUT 20 that can be connected to a data line and a strobe line, respectively.

[0029] Figure 2 Device 100 is shown as including a driver circuit 110, a gating circuit 120, and a receiver circuit 140. Device 100 has a first connection point 102 that can be connected to a data pin 22 to receive a data signal 23 from a DUT 20. Device 100 has a second connection point 104 that can be connected to a strobe signal pin 24 to send / receive a strobe signal 25 to / from the DUT 20. For simplicity, other circuitry is not shown but will be understood to be present based on the description herein. For example, although not shown, device 100 may also include another driver that can drive data to data pin 22. This data can be timed relative to the strobe signal driven by driver circuit 110 to strobe signal pin 24.

[0030] The driver circuit 110 has an output 114 coupled to the first connection point 104. The driver circuit 110 has a drive enable input 112 that can receive a drive enable (DE) signal 113, such as that provided by a pattern generator executing a test program. The test pattern can specify the operation and timing during the test of the DUT 20, such as driving certain data on the data lines to the DUT or sensing data on certain data lines. In some embodiments, the DE signal 113 can have an enabled state and a disabled state, and when the DE signal is in the enabled state, the driver circuit 110 can drive the strobe signal pin 24 of the DUT 20 with the strobe signal 25 during the drive interval of the test process.

[0031] The receiver circuit 140 has a data input 144 coupled to the second connection point 102 to receive the data signal 23. The receiver circuit 140 also has a strobe input 142. The signal at the strobe input 142 controls when the receiver circuit senses data.

[0032] Gating circuit 120 has an input 124 coupled to first connection point 104 and an output 126 coupled to a strobe input 142 of receiver circuit 140. Gating circuit 120 also has a control input 122 coupled to drive enable input 112 of driver circuit 110.

[0033] Still refer to Figure 2 During a receive interval during an exemplary test process, the receiver circuit 140 uses a gated strobe signal 128 received at a strobe input 142 to gate a data signal 23 received from a data line in the DUT 20. The gated strobe signal 128 is generated by the gating circuit 120 based on a strobe signal 25 received from a strobe line of the DUT 20 and based on the DE signal 113 at the control input 122. In some embodiments, the gating circuit 120 selectively passes the received strobe signal 25 from its input 124 to its output 126 based on the state of the DE signal 113. For example, the gating circuit 120 may alternately set the gated strobe signal 128 to a logic low during a gated duration or pass the received strobe signal 25 as the gated strobe signal 128 outside of the gated duration. The gated duration may be set based on both the rising and falling edges of the DE signal 113. In some embodiments, the gate duration can start and end based on the delayed rising and falling edges of the DE signal 113. The delays applied to the rising and falling edges can be the same or different. In some embodiments, the delays for each of the rising and falling edges can be determined using a calibration process.

[0034] In some embodiments, the gated strobe signal may optionally and additionally be delayed in the gating circuitry for an amount of time before being provided to the receiver circuitry to adjust timing synchronization. Regardless of where it is applied, the total delay may be selected so that the received strobe signal is applied to the receiver 140 beginning at a time relative to the de-assertion of the DE signal that is comparable to the time required for the signal from the ATE (indicating that the ATE is not driving data) to propagate to the DUT and for the DUT to respond by transmitting data and for that data to arrive at the receiver 140. The delay also ensures that the signal on the strobe line is not used to gate the receiver 140 later than some time after the assertion of the DE signal (at which point the driver 110 may generate a signal that will then propagate to the receiver 140).

[0035] Figure 3 FIG2 is a schematic diagram illustrating an apparatus 200 for testing a DUT 30 according to some embodiments. The DUT 30 is similar in many respects to the Figure 2 The DUT 20 in FIG. 2 and the apparatus 200 may be as follows Figure 2 An exemplary implementation of the apparatus 100 is shown in FIG.

[0036] exist Figure 3 2 , device 200 includes a driver circuit 210, a gating circuit 220, and a receiving circuit 240. During a drive interval, driver circuit 210 drives DUT pin 34 using a drive DQS signal generated at output 214 of driver circuit 210. The drive DQS signal at output 214 can be enabled or disabled based on the state of a DE signal 213 coupled to a drive enable input 212. During a receive interval, a DQS signal is received from a source channel in DUT 30 at the same DUT pin 34. DE signal 213 is generated by DE generator 216, which can be, for example, part of a timing generator that executes a test pattern that specifies when an ATE including device 200 drives data line 244.

[0037] Figure 3 1 shows a circuit that can process a received strobe signal, which can be a single-ended signal or a differential signal. In this embodiment, comparator 206 has one input coupled to DUT pin 34 and a second input 208. If DUT 30 drives DQS in single-ended mode, second input 208 of comparator 206 can be set to a fixed voltage level. If DUT 30 drives DQS in differential mode, the DUT pin can be coupled to one of the differential DQS signals within DUT 30, while second input 208 of comparator 206 can be coupled to the complementary differential DQS signal. In either case, comparator 206 can provide DQS signal 35 at its output terminal, which represents the DQS signal driven from DUT 30.

[0038] The timing relationship between the DE signal 213 and the signal at the DUT pin 34 in various operating states of the device 200 is Figure 4 As shown in the figure, the Figure 3 Schematic timing diagram of several signals in the embodiment shown in FIG. As shown, time is divided into a driving interval and a receiving interval. During the driving interval, the device 200 can drive data on the data line 244 and can provide a strobe signal on the strobe line connected to the DUT pin 34. During the receiving interval, the device 200 can sense the data on the data line 244 at a time determined by the strobe signal on the strobe line. Figure 4 In the example shown, the gated DQS signal has a transition that reflects the strobe signal driven from the DUT during the receive interval, but is otherwise in a non-intrusive state.

[0039] like Figure 4 , when there is a logic high in the DE signal 213, the driver circuit 210 outputs a sequence of drive DQS signals 416 at the output 214 during the drive interval 402. The drive DQS signal 416 is thus driven from the driver circuit and is reflected in the waveform at the DUT pin 34. Following the falling edge 408 in the DE signal 213, the drive DQS signal is disabled at the output 214 and the waveform at the DUT pin 34 shows the DQS signal 420 driven from the DUT 30 as received during the receive interval 404. Following the rising edge 410 in the DE signal 213, a new drive interval 406 begins and the drive DQS signal 418 is applied at the DUT pin 34. It should be understood that although Figure 4 The specific combination of falling / rising edges in the DE signal 213 is shown as corresponding to drive-to-receive / receive-to-drive interval transitions, respectively, but this example is for illustrative purposes only and similar combinations may also be used. Figure 4 Those edges of opposite polarity shown in the DE signal 213 in.

[0040] Still refer to Figure 4 , the timing of the edges in the DE signal 213 determines the timing of when the driver circuit alternates between the drive interval and the receive interval. In some embodiments, the timing of the edges in the DE signal 213 (e.g., the falling edge 408) can be set before the drive DQS signal 416 generated from the driver circuit 210 changes to the level 424 to ensure that the DE edge 408 determines the driver timing and avoids glitches. When the drive interval 402 ends, the level 422 at the DUT pin 34 can be set by the output 214 of the driver circuit 212 to a state that is not interpreted by the receiver as a select signal. In various embodiments, this state can be a logic low, a logic high, or a third level (a tri-state level), such as Figure 4In some embodiments, level 422 can be set to tri-state for receiving a single-ended DQS signal, and in some other embodiments, level 416 can be set to logic low or logic high when the received DQS signal 420 is in a differential configuration.

[0041] The inventors have understood and appreciated that if the signal received at the DUT pin 34 during the receive interval 404 is used as a DQS strobe signal to strobe received data, the edge from the driven DQS signal 416 near the beginning of the receive interval 404 and the edge from the driven DQS signal 418 near the end of the receive interval 404 may cause errors in strobing the received data because there is no received data from the DUT that corresponds to the DQS signal generated in the driver circuit. Aspects of the present disclosure relate to generating a gated DQS signal such as Figure 4 As shown as signal 228, the gated DQS signal can block the drive DQS signal during at least the beginning and end portions of the receive interval.

[0042] like Figure 4 As shown, the gated DQS signal 228 is generated by passing the received DQS signal 420 during a pass period 422 within the receive interval 404. The pass period 422 is defined by the first edge 412 and the second edge 414 of the delayed DQS signal 227. Therefore, the duration from the second edge 414 to the next occurrence of the first edge 412 can be a gating duration, in which the gated DQS signal 228 is set to a logic low value to avoid gating any received data signals.

[0043] Still refer to Figure 4. The transfer period 422, and likewise the gating duration, is set based on the edges 408 and 410 in the DE signal 213. Specifically, the first edge 412 is set by delaying the edge 410 by a first amount d1, while the second edge 414 is set by delaying the edge 408 by a second amount d2. The delay amounts d1 and d2 can be set so that the driven DQS signal can be prevented from appearing in the gated DQS signal while not missing the DQS edge from the DUT. The programmable delays d1 and d2 can be provided independently and separately to delay the rising edge 410 and the falling edge 408 in the DE signal 213 because the delay required to disable DQS may have different timing than enabling DQS. For example, the round-trip signal travel time in the path between the driver circuit and the DUT may result in a longer delay 424 between the end of the driven DQS signal and the start of the DQS signal received at the DUT pin 34. Therefore, when gating is turned off, there may be relaxed requirements on the exact timing of the edge 412. On the other hand, when the gate is turned on at edge 414, there are stricter requirements for setting the timing because there is no round-trip delay between the driver circuit and the comparator 206. The delay time d2 received before the drive interval edge is enabled can theoretically be the negative amount of the gate duration starting just before the driven DQS signal 418 is enabled, but in practice both d1 and d2 incorporate a positive amount of delay time to account for the DQ signal travel time from the DUT to the receiver. In some embodiments, d2 can be less than d1, and the gate duration can be longer than the drive enable period of the DE signal.

[0044] Return to Figure 3 , which shows the method used to generate Figure 4 An exemplary implementation of the gating circuit 220 for gating the DQS signal 228 is shown. Figure 3As shown, the drive enable input 212 is coupled to the control input 222 of the gate circuit 220 via a pair of delay lines 221 and 223 and an SR flip-flop 224. Examples of delay lines 221 and 223 are described in U.S. Patent No. 10,276,229, the entire contents of which are incorporated herein by reference. Delay lines 221 and 223 and SR flip-flop 224 form a delay circuit that independently applies delay times to the falling and rising edges of the DE signal 213. Delay line 221 is programmable to apply a delay amount d1 to the falling edge 408 of the DE signal 213, while delay line 223 is programmable to apply a delay amount d2 to the rising edge 410 of the DE signal 213. Each of the delay lines 221 and 223 can be a coarse delay line that can be adjusted with an accuracy of less than 50 ps, ​​such as between 10 ps and 20 ps. In some embodiments, the DQS delays d1 and d2 can be in a range between 1 ns and 5 ns, such as between 1 ns and 2 ns. The output of delay line 221 is coupled to the R input of SR flip-flop 224. The output of delay line 223 is coupled to the S input of SR flip-flop 224. The output of SR flip-flop 224 is coupled to the control input 222 of gating circuit 220.

[0045] Delays 221 and 223 can be adjusted as part of a calibration process. For example, a calibration process can be performed by adjusting the delay times in falling delay line 221 and rising delay line 223 until D flip-flop 236 changes state due to the timing of delayed DE signal 227 and DQS signal 35. The calibrated delay times can determine the timing of the delayed DE signal relative to the DQS signal. In some embodiments, each delay time in delay lines 221 and 223 can be adjusted individually to provide margin relative to the calibrated delay times. For example, the rising delay time in delay line 223 can be adjusted to turn off gated DQS signal 228 before the driving edge. Similarly, the falling delay time in delay line 221 can be adjusted to turn on gated DQS signal 228 after the last driving edge in the pulse train completes.

[0046] exist Figure 3 , after the delayed falling and rising edges of the DE signal 213 are combined in the SR flip-flop 224, the control input 222 carries the delayed DE signal 227. Optionally and additionally, a multiplexer 226 can be coupled to the control input 222 so that when it is not desired that the DQS gating be controlled by the delayed DE signal, the delayed DE signal 227 can be replaced by a static DQS gating control signal.

[0047] Still refer to Figure 3, the multiplexer 230 has a first select input '0' coupled to the received DQS signal 35, and a second select input '1' coupled to a logic value 231 which may be a logic low. The multiplexer control input 234 receives the delayed DE signal 227 and controls the multiplexer 230 to pass through the received DQS signal 35 to become a gated DQS signal 228 at the multiplexer output when the delayed DE signal 227 is at a logic low, and to set the gated DQS signal 228 to a logic level 231 when the delayed DE signal 227 is at a logic high. Figure 4 The timing relationship between various waveforms is shown in Figure 2.

[0048] Optionally and additionally, a delay can be applied to the gated DQS signal 228, such as by a DQS delay unit 232, before the delayed gated DQS signal is used to gate the DQ signal 244 received in the receiver circuit 240. In some embodiments, a D flip-flop 236 is optionally coupled to the delayed DE signal 227 and the '0' input of the multiplexer 234. The D flip-flop 236 can be used for calibration purposes within the gating circuit 220. For example, a gate alignment signal at the Q output terminal of the D flip-flop 236 can provide observability of the state of the delayed DE signal 227 relative to the rising edge of the DQS signal 35.

[0049] While the above describes various aspects of at least one embodiment of the present invention, it should be understood that various changes, modifications, and improvements may be readily made by those skilled in the art. Figure 2 and Figure 3 Only a single source channel is shown in FIG, but it should be understood that aspects of the present disclosure can be extended to provide a gated DQS signal in multiple source channels to gate multiple DQ channels based on a drive enable signal.

[0050] Furthermore, to simplify the description, one gate line is shown as being associated with one data line. In some cases, a gate line may be associated with multiple data lines, such as multiple data lines forming a bus. In this case, components driving or receiving signals on the data lines may be duplicated and controlled based on the same gating signal.

[0051] Also for simplicity of explanation, the operation of a properly functioning DUT is described.The test system can be programmed to recognize that the DUT does not respond to signals in the same manner as a properly functioning device and can responsively provide an output indicating that the DUT has failed.

[0052] As an example of further variation, ATE and DUT are used as examples of two devices that can use source synchronous communication to transfer data. Circuits and techniques as described herein can be used in other devices that use source synchronous communication to transfer data, such as a processor that can communicate with a memory chip.

[0053] Such changes, modifications, and improvements are intended to be part of this disclosure and are considered to fall within the spirit and scope of the invention. Furthermore, while advantages of the invention are indicated, it should be understood that not every embodiment of the technology described herein will include every described advantage. Some embodiments may not implement any of the features advantageously described herein, and in some cases, one or more of the features may be implemented to implement additional embodiments. Therefore, the foregoing description and drawings are intended to be by way of example only.

[0054] The various aspects of the present invention may be used individually, in combination, or in various configurations not specifically discussed in the above embodiments, and therefore their application is not limited to the details and configurations of the components described in the above description or shown in the drawings. For example, aspects described in one embodiment may be combined in any manner with aspects described in other embodiments.

[0055] Additionally, the present invention may be implemented as a method, and examples thereof have been provided. The operations performed as part of the method may be ordered in any suitable manner. Thus, embodiments may be constructed that perform operations in an order different from that shown, which may include performing certain operations simultaneously, even though these operations are shown as sequential operations in the exemplary embodiments.

[0056] Such changes, modifications and improvements are intended to be part of this disclosure and are considered to fall within the spirit and scope of the invention. In addition, although the advantages of the present invention are indicated, it should be understood that not every embodiment of the present invention will include every described advantage. Some embodiments may not implement any of the features described herein and in some cases, which are advantageous. Therefore, the above description and drawings are intended to be by way of example only.

[0057] The use of ordinal terms such as "first," "second," "third," etc. in the claims to modify claim elements does not in itself imply any priority, precedence, or order of one claim element over another, or the temporal order of performing method operations, but serves merely as a label to distinguish one claim element having a certain name from another element having the same name (except for the ordinal terms used) to identify the claim elements.

[0058] In addition, the phrases and terms used herein are for illustrative purposes and should not be considered as limiting. As used herein, "include," "comprising," or "having," "containing," "involving," and variations thereof are meant to encompass the items listed thereafter and their equivalents as well as additional items.

Claims

1. An apparatus (100) for synchronizing data received from a semiconductor device (20) with a strobe signal, the apparatus comprising: a first connection point (104) configured to connect to a strobe signal pin (24) of the semiconductor device; a second connection point (102) configured to connect to a data pin (22) of the semiconductor device; a driver circuit (110) having an output (114) coupled to the first connection point and a drive enable input (112), wherein the driver circuit is configured to drive the output during a drive enable period based on a state of a signal (113) at the drive enable input; a receiver circuit having a data input (144) and a strobe input (142), wherein the data input is coupled to the second connection point and the receiver circuit is configured to receive data (23) at the data input (144) based on a state of a signal at the strobe input; and a gating circuit (120) having an input (124) coupled to the first connection point and an output (126) coupled to the strobe input of the receiver circuit and a control input (122) coupled to the drive enable input, wherein the gating circuit is configured to selectively pass a signal from the input of the gating circuit to the output of the gating circuit based on a state of a signal at the control input of the gating circuit.

2. The apparatus of claim 1 , wherein the drive enable input is coupled to the control input via a delay circuit comprising a first delay component and a second delay component, wherein The first delay component is configured to delay a rising edge of a signal at the drive enable input by a first amount, and the second delay component is configured to delay a falling edge of the signal at the drive enable input by a second amount.

3. The apparatus according to claim 2, wherein the delay circuit further comprises: An SR flip-flop includes an output coupled to the control input of the gating circuit, an S input coupled to the first delay component, and an R input coupled to the second delay component.

4. The apparatus of claim 3, wherein the first delay element and the second delay element are independently programmable.

5. The apparatus of claim 3 , wherein the gating circuit comprises: A multiplexer comprising an output and at least a first select input and a second select input and a multiplexer control input; wherein: the multiplexer being configured to selectively couple a signal from either the first select input or the second select input to the output based on a state of a signal at the multiplexer control input; the first select input is coupled to the first connection point; and The multiplexer control input is coupled to the output of the SR flip-flop.

6. The apparatus of claim 1 , wherein the gating circuit is configured to selectively pass the signal from the input of the gating circuit to the output of the gating circuit when the signal at the control input of the gating circuit is in a first state, and to pass a logic low value when the signal at the control input of the gating circuit is in a second state different from the first state.

7. The apparatus of claim 1 , wherein the apparatus comprises automatic test equipment (ATE) comprising a plurality of channels configured to generate and / or measure signals of a device under test (DUT), and The first connection point is located in a first channel of the plurality of channels, and the second connection point is located in a second channel of the plurality of channels.

8. The apparatus of claim 1, further comprising a second delay circuit, and wherein the output of the gating circuit is coupled to the strobe input of the receiver circuit through the second delay circuit.

9. A method for performing source synchronization with a semiconductor device, the method comprising: enabling a driver to drive a gate line of the semiconductor device during a drive enable period of a drive enable signal; receiving a strobe signal from the semiconductor device on the strobe line; generating a gated strobe signal from the received strobe signal on the strobe line based on the drive enable signal; as well as A receiver is gated based on the gated gate signal to record the received data signal on a data line of the semiconductor device.

10. The method of claim 9, wherein generating the gated strobe signal from the signal on the strobe line comprises alternately passing a received strobe signal as the gated strobe signal or setting the gated strobe signal to a logic low value based on the drive enable signal.

11. The method of claim 9 , wherein generating the gated strobe signal from the signal on the strobe line comprises passing a received strobe signal as the gated strobe signal or blocking the received strobe signal during a gating duration, wherein the drive enable period is defined by a first edge and a second edge in the drive enable signal, and wherein: Generating the gated selection signal further includes: starting the gating duration at a delayed first edge based on the timing of the first edge in the drive enable signal; and The gating duration is terminated at a delayed second edge based on the timing of the second edge in the drive enable signal. The method of claim 11 , wherein the gating duration is longer than the drive enable period.

13. The method according to claim 11, further comprising: using a first delay component to delay the first edge of the drive enable signal by a first delay amount to become the delayed first edge; as well as The second edge of the drive enable signal is delayed by a second delay amount different from the first delay amount to become the delayed second edge using a second delay component.

14. The method of claim 9, wherein the strobe signal is a DQS signal, and wherein the received data signal is a DQ signal.

15. The method of claim 9, wherein gating the receiver comprises: applying a delay to the gated strobe signal to generate a delayed gated strobe signal; as well as The receiver is gated based on the delayed gated enable signal.

16. A method for operating automated test equipment (ATE) to test a semiconductor device, the ATE comprising a driver circuit having an output coupled to a gate line of the semiconductor device, a receiver circuit, and a gating circuit having an input coupled to the gate line, the method comprising: enabling the driver circuit to drive the gate line during a drive enable period of a drive enable signal; receiving a gating signal from the semiconductor device at the input of the gating circuit; generating a gated gate signal using the gate control circuit based on the received gate signal and the drive enable signal; as well as The receiver circuit is enabled based on the gated enable signal to record a data signal on a data line of the semiconductor device. 17 . The method of claim 16 , wherein generating the gated strobe signal comprises alternately passing a received strobe signal as the gated strobe signal or setting the gated strobe signal to a logic low value based on the drive enable signal.

18. The method of claim 16 , wherein generating the gated strobe signal from the signal on the strobe line comprises passing a received strobe signal as the gated strobe signal or blocking the received strobe signal during a gating duration, wherein the drive enable period is defined by a first edge and a second edge in the drive enable signal, and wherein: Generating the gated strobe signal also includes: starting the gating duration at a delayed first edge based on the timing of the first edge in the drive enable signal; and The gating duration is terminated at a delayed second edge based on the timing of the second edge in the drive enable signal. The method of claim 18 , wherein the gating duration is longer than the drive enable period.

20. The method of claim 18, wherein the gating circuit comprises a first delay line and a second delay line, and the method further comprises: delaying the first edge of the drive enable signal by a first delay amount to become the delayed first edge using the first delay line; as well as The second edge of the drive enable signal is delayed by a second delay amount different from the first delay amount to become the delayed second edge using the second delay line.

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