Electronic system testing method

Abstract

A method for testing an electronic system is disclosed. The method comprises: (a) inputting a main test waveform to a main signal path of the electronic system and simultaneously inputting a plurality of sub test waveforms to a plurality of sub signal paths of the electronic system according to a test waveform combination comprising the main test waveform and the plurality of sub test waveforms; (b) obtaining a result waveform corresponding to the step (a); (c) changing the main test waveform or the plurality of sub test waveforms, and repeating the steps (a) and (b) until all the test waveforms of the test waveform combination are tested to obtain a plurality of result waveforms; and (d) determining a combination level of the test waveform combination according to the plurality of result waveforms.

Description

Technical Field

[0001] The present invention relates to an electronic system testing method, and more particularly to an electronic system testing method capable of obtaining required test results with a relatively simple test waveform (test pattern) and testing multiple signal paths. Background Art

[0002] In electronic system testing, eye diagrams are often used to determine the overall system performance. However, this testing method typically requires a test pattern of sufficient length to generate the required eye diagram. For example, a pseudo-random binary sequence (PRBS) is used, with the commonly used PRBS-7 signal being at least 127 bits long. Furthermore, conventional electronic system testing typically only tests a single signal path and fails to consider crosstalk caused by other nearby signal paths. Summary of the Invention

[0003] An object of the present invention is to provide an electronic system testing method using a test waveform with fewer bits.

[0004] Another object of the present invention is to provide a test device that uses a test waveform with fewer bits.

[0005] One embodiment of the present invention provides an electronic system testing method for testing a target electronic system, comprising: (a) inputting a main test waveform into a main signal path of the target electronic system and simultaneously inputting a secondary test waveform into at least one secondary signal path of the target electronic system based on a test waveform combination comprising multiple test waveforms; (b) obtaining a result waveform corresponding to step (a); and (c) changing the main test waveform or the secondary test waveform and repeating steps (a) and (b) multiple times until all test waveforms of the test waveform combination are tested and multiple result waveforms are obtained, and then determining a combination level of the test waveform combination based on the result waveforms. The main test waveform is an X-bit waveform and the secondary test waveform is a Y-bit waveform, where X and Y are positive integers greater than or equal to 3. This electronic system testing method can be implemented using a test device.

[0006] According to the aforementioned embodiment, the number of bits in the test waveform can be reduced to reduce the amount of data and the required test time during the test process. In addition to testing the potential problems caused by signal changes in a single signal path, the potential impact of other signal paths on this signal path is also considered. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1FIG. 4 is a block diagram illustrating a method of testing a target electronic system using a testing device according to an embodiment of the present invention.

[0008] Figure 2 A flow chart of an electronic device testing method according to an embodiment of the present invention is shown.

[0009] Figure 3 A more detailed flow chart of an electronic device testing method according to an embodiment of the present invention is shown.

[0010] Figure 4 A testing device according to an embodiment of the present invention is shown.

[0011] Explanation of symbols:

[0012] 101 Target Electronic Systems

[0013] 103 Eye diagram generator

[0014] 105 Test Device

[0015] 401 Processing Circuit

[0016] 403 Storage

[0017] AS1, AS2 secondary signal paths

[0018] MS Main Signal Path DETAILED DESCRIPTION

[0019] The present invention will be described below using multiple embodiments. Please note that the components in each embodiment may be implemented via hardware (e.g., a device or circuit) or firmware (e.g., at least one program written into a microprocessor). Furthermore, the terms "first," "second," and similar terms in the following description are used solely to define different components, parameters, data, signals, or steps. They are not intended to limit the order in which they are presented.

[0020] Figure 1 FIG. 1 is a block diagram showing a method for testing a target electronic system using a test device according to an embodiment of the present invention. Figure 1As shown, the target electronic system 101 may include at least one electronic device and include a main signal path MS and multiple auxiliary signal paths (two auxiliary signal paths AS1 and AS2 in the following embodiment, but this is not limiting). In one embodiment, the main signal path MS and the auxiliary signal paths AS1 and AS2 are both signal transmission lines of the target electronic system 101. During testing, a main test waveform MP is input to the main signal path MS of the target electronic system 101 based on a test waveform combination comprising multiple test waveforms. Simultaneously, auxiliary test waveforms AP1 and AP2 are input to the auxiliary signal paths AS1 and AS2 of the target electronic system 101, respectively. The main test waveform MP or the auxiliary test waveforms AP1 and AP2 may be generated by the test device 105 or by a device external to the test device 105. The main test waveform is an X-bit waveform, and the auxiliary test waveform is a Y-bit waveform, where X and Y are positive integers greater than or equal to 3, and X and Y may be the same positive integer or different positive integers. By simultaneously inputting test waveforms to the main signal path MS and multiple subsidiary signal paths AS1 and AS2, not only the impact of the test waveform on the main signal path MS can be observed, but also the impact of the test waveform on the subsidiary signal paths AS1 and AS2 on the main signal path MS can be observed.

[0021] The target electronic system 101 generates a result waveform RW corresponding to a test waveform comprising different main test waveforms MP and auxiliary test waveforms AP1 and AP2. The eye pattern generating device 103 receives the result waveform RW and generates an eye diagram ED corresponding to the result waveform RW. In one embodiment, the eye pattern generating device 103 generates an eye diagram based on the result waveforms RW corresponding to all test waveforms in the test waveform combination. The detailed steps will be described in detail in the following examples.

[0022] The test device 105 will determine the combination level of the test waveform combination based on the eye diagram ED. Please also note that in one embodiment, the judgment of whether the eye diagram ED is good or bad can also be made by the tester visually, rather than by the test device 105. The aforementioned values ​​of X and Y can be determined by the required test data and the required test time. The larger the values ​​of X and Y, the more test data can be used to generate the eye diagram, and the more accurate the judgment of the eye diagram, but a longer test time is required. On the contrary, the smaller the values ​​of X and Y, the less test data there is, but the required test time will be correspondingly shorter. However, please note that in Figure 1 In the embodiment, the combination level is determined based on the eye diagram of the result waveform RW. However, the combination level may also be determined based on other parameters of the result waveform RW.

[0023] As previously described, after obtaining the result waveform RW corresponding to a set of main and sub-test waveforms, the main or sub-test waveform is changed, and the aforementioned steps are repeated to generate multiple result waveforms RW until all test waveforms in the test waveform combination have been tested. For example, the input waveforms for the main and sub-test waveforms are (MP, AP1, AP2), and the result waveform RW1 is obtained. In the next test round, the main and sub-test waveforms are changed to (MP, AP1, AP3), and the result waveform RW2 is obtained. Then, in the next test round, the main and sub-test waveforms are changed to (MPa, AP1, AP2), and the result waveform RW3 is obtained. Therefore, after performing three tests with different main and sub-test waveforms, three result waveforms RW1, RW2, and RW3 are obtained. The result waveforms RW1, RW2, and RW3 are then used to generate an eye diagram. The better the eye diagram condition is, for example, the clearer the eye diagram is, the better the response of the target electronic system 101 to the test waveform combination is.

[0024] Table 1 below shows an example of a test waveform combination. However, please note that these combinations are for example purposes only, and the test waveforms can be set to meet different requirements.

[0025]

[0026] Table 1

[0027] The test waveform combination shown in Table 1 includes 8 test waveforms, each of which includes a main test waveform MP and two sub-test waveforms AP1 and AP2. The first test waveform input to the main signal path MS and the sub-signal paths AS1 and AS2 is test waveform 1. After obtaining the result waveform of test waveform 1, the test waveform input to the main signal path MS and the sub-signal paths AS1 and AS2 will be switched to test waveform 2. That is, the sub-test waveform input to the sub-signal paths AS1 and AS2 will switch from 010 to 101, while the main test waveform input to the main signal path MS will remain 010, and the corresponding result waveform will be obtained. The remaining test waveforms follow the same rules until all 8 test waveforms are input.

[0028] The multiple test waveforms in Table 1 follow at least one of the following rules, but are not limited to them. In the embodiment of Table 1, the same sub-test waveform is input to different sub-signal paths. In one embodiment, the main test waveform and the sub-test waveform are the same, such as test waveform 1 and test waveform 4. According to Table 1, the main test waveform and the sub-test waveform respectively include one of the following values: 010, 101, 000 and 111. In detail, the main test waveform may include one of the following values: 010, 101, 000 and 111, and the sub-test waveform may include one of the following values: 010 and 101. And according to Table 1, in one embodiment, the main test waveform and the sub-test waveform do not include values ​​other than 010, 101, 000 and 111.

[0029] As previously mentioned, the combination level can be determined based on the eye diagram. Therefore, in one embodiment, the main test waveforms and auxiliary test waveforms included in the test waveforms are determined by the portion of the eye diagram to be observed. Taking Table 1 as an example, if the entire eye diagram is to be observed, all test waveforms from test waveforms 1 to 8 are used to test the target electronic system 101. If only the inner boundary of the eye diagram is to be observed, test waveforms 1-4 are used to test the target electronic system 101. If the outer boundary of the eye diagram is to be observed, test waveforms 6-8 are used to test the target electronic system 101.

[0030] Please also note that in the aforementioned examples, multiple tests were performed by changing only the main test waveform or the auxiliary test waveform, without changing the configuration of the main signal path MS and the auxiliary signal paths AS1 and AS2. However, in another embodiment, the configuration of the main signal path MS and the auxiliary signal paths AS1 and AS2 can also be changed to perform multiple tests. For example, one of the auxiliary signal paths AS1 and AS2 can be selected as the main signal path, while the original main signal path MS serves as the auxiliary signal path. Furthermore, there can be more than one main signal path, and the number of auxiliary signal paths is not limited to two.

[0031] In one embodiment, after testing the target electronic system 101 with multiple test waveform combinations and obtaining multiple combination levels, a determination is made as to whether the signal quality corresponding to the lowest combination level meets a predetermined standard (e.g., the minimum signal quality required by a circuit or device standard) to determine whether the target electronic system 101 can be used or whether adjustments are required. However, the multiple combination levels are not limited to this application. For example, in one embodiment, several preferred combination levels are selected from the multiple combination levels, and the input signals to the target electronic system 101 are limited to the test waveform combinations corresponding to the preferred combination levels. Such variations and application variations are intended to be within the scope of the present invention.

[0032] According to the aforementioned embodiments, an electronic device testing method can be obtained, which is used to test the signal quality of at least one output signal of a target electronic system (eg, 101 ). Figure 2 A flow chart of an electronic device testing method according to an embodiment of the present invention is shown, which includes the following steps:

[0033] Step 201

[0034] According to a test waveform combination including a plurality of test waveforms, a main test waveform (e.g., MP) is input to a main signal path (e.g., MS) of the target electronic system, and simultaneously, a pair of test waveforms (e.g., AP1, AP2) are respectively input to at least one pair of signal paths (e.g., AS1, AS2) of the target electronic system.

[0035] The main test waveform is an X-bit waveform and the auxiliary test waveform is a Y-bit waveform, where X and Y are positive integers greater than or equal to 3.

[0036] Step 203

[0037] A result waveform corresponding to step 201 is obtained.

[0038] Step 205

[0039] The main test waveform or the auxiliary test waveform is changed, and step 201 and step 203 are repeated multiple times until all the test waveforms of the test waveform combination are tested, and a combination level of the test waveform combination is determined according to the result waveforms.

[0040] For example, as shown in Table 1, the test waveform combination includes 8 test waveforms. After testing these 8 test waveforms in sequence, 8 result waveforms can be obtained. Then, an eye diagram is generated based on these 8 result waveforms to obtain the combination level.

[0041] Figure 3 A more detailed flow chart of an electronic device testing method according to an embodiment of the present invention is shown. Figure 2 An example of a more detailed flow chart of a method for testing an electronic device is shown. Figure 3 The electronic device testing method shown includes a first stage and a second stage. The first stage includes steps 301-309, and the second stage includes step 311. Steps 301-311 include the following steps:

[0042] Step 301

[0043] Establishing the test system architecture involves defining the test system to test the target electronic system. This step may include, but is not limited to, selecting the path to be tested, setting the system channels, and configuring the load components. System channels are the signal transmission paths in the system, such as netlists, S-parameters, and W-elements. Load components can be IBIS or RLC components.

[0044] Step 303

[0045] Select and input the main test waveform into the main signal path.

[0046] Step 305

[0047] Select and input the secondary test waveform into the secondary signal path.

[0048] Step 307

[0049] An eye diagram is generated from the multiple resulting waveforms.

[0050] Steps 303 to 307 can be run in parallel to reduce test time. Taking Table 1 as an example, the eight test waveforms can be run simultaneously and the results can then be combined.

[0051] Step 309

[0052] After steps 303 to 307 are repeated multiple times, the test waveform combination with the lowest combination rank is found.

[0053] Step 311

[0054] Observe the system status of the target electronic system when using the test waveform combination with the lowest combination level to determine whether the target electronic system needs to be adjusted.

[0055] Figure 1 The test device 105 shown in FIG. 1 may include a variety of structures. Figure 4 FIG. 1 shows a test device according to an embodiment of the present invention. Figure 4 As shown, the test device 105 includes a processing circuit 401 and a storage device 403. The storage device 403 includes at least one program. The processing circuit 401 is used to execute the stored program to perform the above embodiments. Specifically, the processing circuit 401 can be used to calculate Figure 1 The test waveform generator 403 generates the desired test waveforms in response to commands from the tester or automatically generates instructions. The test waveform generator 403 may be included in the test device 105 or located outside the test device 105. Furthermore, the storage device 403 may also be located outside the test device 105.

[0056] According to the aforementioned embodiment, the number of bits in the test waveform can be reduced to reduce the amount of data and the required test time during the test process. In addition to testing the potential problems caused by signal changes in a single signal path, the potential impact of other signal paths on this signal path is also considered.

[0057] The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made according to the claims of the present invention should fall within the scope of the present invention.

Claims

1. An electronic system testing method for testing a target electronic system, characterized in that: Include: (a) inputting a main test waveform to a main signal path of the target electronic system and simultaneously inputting a secondary test waveform to at least one secondary signal path of the target electronic system according to a test waveform combination comprising a plurality of test waveforms; (b) obtaining a result waveform corresponding to step (a); (c) changing the main test waveform or the auxiliary test waveform and repeating steps (a) and (b) multiple times until all the test waveforms of the test waveform combination are tested to obtain a plurality of result waveforms, and determining a combination level of the test waveform combination based on the result waveforms; The main test waveform is an X-bit waveform and the auxiliary test waveform is a Y-bit waveform, where X and Y are positive integers greater than or equal to 3.

2. The electronic system testing method according to claim 1, wherein: The step (a) inputs the same secondary test waveform to different secondary signal paths.

3. The electronic system testing method according to claim 2, wherein: The main test waveform and the auxiliary test waveform are the same.

4. The electronic system testing method according to claim 1, wherein: X and Y are both 3, and the number of the secondary signal paths is 2.

5. The electronic system testing method according to claim 4, wherein: The main test waveform contains one of the following values: 010, 101, 000, and 111.

6. The electronic system testing method according to claim 5, wherein: The main test waveform and the subsidiary test waveform do not include values ​​other than 010, 101, 000, and 111.

7. The electronic system testing method according to claim 4, wherein: The main test waveform includes one of the following values: 010, 101, 000, and 111, and the sub-test waveform includes one of the following values: 010 and 101.

8. The electronic system testing method according to claim 7, wherein: The main test waveform and the subsidiary test waveform do not include values ​​other than 010, 101, 000, and 111.

9. The electronic system testing method according to claim 1, wherein: The step (c) generates an eye diagram according to the result waveforms, and determines the combination level according to the eye diagram.

10. The electronic system testing method according to claim 1, wherein: Also includes: generating a plurality of combination levels according to a plurality of test waveform combinations; Whether the target electronic system can be used or needs to be adjusted is determined based on the plurality of result waveforms of the test waveform combination corresponding to the lowest combination level.

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