A method, apparatus, device and storage medium for generating a layout of a wafer substrate

Abstract

This specification discloses a method, apparatus, device, and storage medium for generating a layout of a wafer substrate. The various layers of the wafer substrate can be divided into two different modules, and when generating the layouts corresponding to the first adaptation module and the structure module, they can be generated based on different lithography processes respectively. The first adaptation module is used to adapt between the structure module and the heterogeneous heterogeneous die, the structure module is used to achieve the corresponding structural function connection, and the second adaptation module is used to adapt between the structure module and the auxiliary power supply board. Furthermore, a layout of the wafer substrate that can be adapted to various heterogeneous heterogeneous dies can be generated.

Description

Technical Field

[0001] This specification relates to the field of integrated circuit technology, and particularly to a method, apparatus, device, and storage medium for generating a layout of a wafer substrate. Background Art

[0002] Currently, due to the characteristics of high interconnect density, excellent energy consumption ratio, and high integration density of the system-on-chip itself, the system-on-chip technology has gradually replaced the traditional Printed Circuit Board (PCB) technology and received extensive attention.

[0003] In the prior art, when generating the layout of the wafer substrate required to form the system-on-chip, the layout of the wafer is often generated based on the characteristics of the step-and-repeat lithography technology for manufacturing the wafer substrate. However, when using the step-and-repeat lithography technology to fabricate the wafer substrate, a pre-set photomask is often used to continuously draw on the wafer substrate, so that the lithographic pattern structures of each area of the drawn wafer substrate are the same.

[0004] In actual application scenarios, due to the different numbers and distributions of pins with different functions on the heterogeneous and heterogeneous dielets to be mounted on the wafer substrate, it is required that the lithographic pattern structures corresponding to different areas of the wafer substrate are also different. Therefore, the existing methods for generating the layout of the wafer substrate cannot be adapted to the wafer substrate that needs to mount a variety of different heterogeneous and heterogeneous dielets. Summary of the Invention

[0005] This specification provides a method, apparatus, device, and storage medium for generating a layout of a wafer substrate to partially solve the above problems existing in the prior art.

[0006] This specification adopts the following technical solutions:

[0007] This specification provides a method for generating a layout of a wafer substrate. The method is applied to generate the layout of the wafer substrate. The wafer substrate includes: a first adaptation module, a second adaptation module, and each structure module. Wherein, the layout corresponding to each structure module is the same, each structure module corresponds to each dielet one by one, the structure module is composed of a micro-bump array layer, a through-silicon via layer, at least one redistribution layer, and at least one via layer. One side of the first adaptation module is used to bond with the pins of dielets with different functions, and the other side of the first adaptation module is used to bond with the micro-bump array layer of each structure module. One side of the second adaptation module is used to bond with the through-silicon via layer of each structure module, and the other side of the second adaptation module is used to bond with an auxiliary power supply board. The method includes:

[0008] Obtain the pin information of the chiplets to be connected, where the pin information includes: the position information of each pin of the chiplet and the function information of each pin of the chiplet;

[0009] Determine the connection relationship between the pins of the chiplet according to the pin information;

[0010] Generate the layout corresponding to the micro - pad array layer of the structural module, the layout corresponding to the through - silicon via layer of the structural module, and generate the layout corresponding to each layer of the redistribution layer and via layer of the first adaptation module. The layout is used to represent the quantity and position distribution information of each basic unit required for each layer of the structure constituting the wafer substrate, and the basic unit includes at least one of metal wires, vias, and through - silicon vias;

[0011] Generate the layout corresponding to each layer of the redistribution layer and each layer of the via layer of the structural module according to the layout corresponding to the micro - pad array layer of the structural module and the layout corresponding to the through - silicon via layer of the structural module, and generate the layout corresponding to the second adaptation module;

[0012] Determine the layout corresponding to the wafer substrate according to the layout corresponding to each layer of the structure required for the first adaptation module, the structural module, and the second adaptation module.

[0013] Optionally, determining the connection relationship between the pins of the chiplet according to the pin information specifically includes:

[0014] For each chiplet, determine the connection relationship between the pins of the chiplet according to the pin information of each pin of the chiplet.

[0015] Optionally, determining the connection relationship between the pins of the chiplet according to the pin information specifically includes:

[0016] For each chiplet, determine the connection relationship between the pins of the chiplet and the pins of other chiplets according to the pin information of each pin of each chiplet.

[0017] Optionally, generating the layout corresponding to each layer of the redistribution layer and via layer of the first adaptation module according to the connection relationship specifically includes:

[0018] Generate the initial layout corresponding to each layer of the redistribution layer and via layer of the first adaptation module according to the connection relationship;

[0019] Judge whether there is an abnormality when preparing the wafer substrate according to the quantity and position distribution information of each basic unit included in the initial layout corresponding to each layer of the redistribution layer and via layer of the first adaptation module;

[0020] If so, regenerate the initial layout corresponding to each layer of the rewiring layer and the via layer of the first adaptation module;

[0021] If not, use the initial layout corresponding to each layer of the rewiring layer and the via layer of the first adaptation module as the layout corresponding to each layer of the rewiring layer and the via layer of the first adaptation module.

[0022] Optionally, determine whether there is an abnormality when preparing the wafer substrate according to the initial layout corresponding to each layer of the rewiring layer and the via layer of the first adaptation module based on the quantity and position distribution information of each basic unit included in the initial layout, specifically including:

[0023] Determine whether there is an abnormality when preparing the wafer substrate according to the initial layout corresponding to each layer of the rewiring layer and the via layer of the first adaptation module based on the quantity and position distribution information of each basic unit included in at least part of the initial layout of the initial layout corresponding to each layer of the rewiring layer and the via layer of the first adaptation module.

[0024] Optionally, generate the layout corresponding to the second adaptation module, specifically including:

[0025] For each structural module, generate the layout corresponding to the area of the second adaptation module corresponding to this structural module according to the pin information of the die corresponding to this structural module and the layout corresponding to the through-silicon via layer of this structural module.

[0026] Optionally, for each structural module, generate the layout corresponding to the area of the second adaptation module corresponding to this structural module according to the pin information of the die corresponding to this structural module and the layout corresponding to the through-silicon via layer of this structural module, specifically including:

[0027] Determine whether there is an abnormality when preparing this structural module according to the layout corresponding to each layer of the structure of any one structural module based on the quantity and position distribution information of each basic unit included in the layout corresponding to each layer of the structure of any one structural module;

[0028] If not, for each structural module, generate the layout corresponding to the area of the second adaptation module corresponding to this structural module according to the pin information of the die corresponding to this structural module and the layout corresponding to the through-silicon via layer of this structural module.

[0029] This specification provides a wafer substrate layout generation device, including:

[0030] An acquisition module, configured to acquire the pin information of the die to be connected, where the pin information includes: the position information of each pin of the die, and the function information of each pin of the die;

[0031] A first determination module, configured to determine the connection relationship between the pins of the chiplet according to the pin information.

[0032] A first generation module, configured to generate a layout corresponding to the micro-pad array layer of the structural module, a layout corresponding to the through-silicon via layer of the structural module, and generate a layout corresponding to each layer of the redistribution layer and the via layer of the first adaptation module according to the connection relationship. The layout is used to represent the quantity and position distribution information of each basic unit required for each layer of the structure constituting the wafer substrate. The basic unit includes at least one of a metal wire, a via, and a through-silicon via.

[0033] A second generation module, configured to generate a layout corresponding to each layer of the redistribution layer and each layer of the via layer of the structural module, and generate a layout corresponding to the second adaptation module according to the layout corresponding to the micro-pad array layer of the structural module and the layout corresponding to the through-silicon via layer of the structural module.

[0034] A second determination module, configured to determine the layout corresponding to the wafer substrate according to the layout corresponding to each layer of the structure required for the first adaptation module, the structural module, and the second adaptation module.

[0035] Optionally, the first determination module is specifically configured to, for each chiplet, determine the connection relationship between the pins of the chiplet according to the pin information of each pin of the chiplet.

[0036] Optionally, the first determination module is specifically configured to, for each chiplet, determine the connection relationship between the pins of the chiplet and the pins of other chiplets according to the pin information of each pin of each chiplet.

[0037] Optionally, the first generation module is specifically configured to generate an initial layout corresponding to each layer of the redistribution layer and the via layer of the first adaptation module according to the connection relationship; determine whether there is an abnormality when preparing the wafer substrate according to the quantity and position distribution information of each basic unit included in the initial layout corresponding to each layer of the redistribution layer and the via layer of the first adaptation module; if so, regenerate the initial layout corresponding to each layer of the redistribution layer and the via layer of the first adaptation module; if not, use the initial layout corresponding to each layer of the redistribution layer and the via layer of the first adaptation module as the layout corresponding to each layer of the redistribution layer and the via layer of the first adaptation module.

[0038] Optionally, the first generation module is specifically configured to determine whether there is an abnormality when preparing the wafer substrate according to the number and position distribution information of each basic unit included in at least part of the initial layout corresponding to each layer of the rewiring layer and the via layer of the first adaptation module.

[0039] Optionally, the second generation module is specifically configured to, for each structural module, generate the layout corresponding to the area corresponding to the structural module in the second adaptation module according to the pin information of the chiplet corresponding to the structural module and the layout corresponding to the through-silicon via layer of the structural module.

[0040] Optionally, the second generation module is specifically configured to determine whether there is an abnormality when preparing the structural module according to the number and position distribution information of each basic unit included in the layout corresponding to each layer structure of any one structural module; if not, then for each structural module, generate the layout corresponding to the area corresponding to the structural module in the second adaptation module according to the pin information of the chiplet corresponding to the structural module and the layout corresponding to the through-silicon via layer of the structural module.

[0041] This specification provides a computer-readable storage medium storing a computer program, and when the computer program is executed by a processor, the above-mentioned wafer substrate layout generation method is implemented.

[0042] This specification provides an electronic device, including a memory, a processor, and a computer program stored on the memory and executable on the processor. When the processor executes the program, the above-mentioned wafer substrate layout generation method is implemented.

[0043] At least one of the above technical solutions adopted in this specification can achieve the following beneficial effects:

[0044] In the method for generating a wafer substrate layout provided in this specification, first, the pin information of the dies to be connected is obtained. The pin information includes: the position information of each pin of the die and the function information of each pin of the die. According to the pin information, the connection relationship between the pins of the die is determined. According to the connection relationship, the layout corresponding to the micro-pad array layer of the structural module, the layout corresponding to the through-silicon via layer of the structural module, and the layout corresponding to each layer of the redistribution layer and via layer of the first adaptation module are generated. The layout is used to represent the quantity and position distribution of each basic unit required for each layer structure constituting the wafer substrate. The basic unit includes at least one of a metal wire, a via, and a through-silicon via. According to the layout corresponding to the micro-pad array layer of the structural module and the layout corresponding to the through-silicon via layer of the structural module, the layout corresponding to each layer of the redistribution layer and each layer of the via layer of the structural module is generated, and the layout corresponding to the second adaptation module is generated. According to the layout corresponding to each layer structure required for the first adaptation module, the structural module, and the second adaptation module, the layout corresponding to the wafer substrate is determined.

[0045] As can be seen from the above method, the various layer structures constituting the wafer substrate can be divided into two different modules, and when generating the layouts corresponding to the first adaptation module and the structural module, they can be generated respectively based on different lithography processes. The first adaptation module adapts between the structural module and the heterogeneous die, the structural module realizes the corresponding structural function connection, and the second adaptation module adapts between the structural module and the auxiliary power supply board, so that a wafer substrate layout capable of adapting to various heterogeneous dies can be generated. Description of the Drawings

[0046] The drawings described herein are used to provide a further understanding of this specification and constitute a part of this specification. The schematic embodiments of this specification and their descriptions are used to explain this specification and do not constitute an improper limitation to this specification. In the drawings:

[0047] Figure 1 It is a schematic flowchart of a method for generating a wafer substrate layout provided in this specification;

[0048] Figure 2 It is a schematic diagram of the pins of a heterogeneous die provided in this specification;

[0049] Figure 3 It is a schematic diagram of the pins of another heterogeneous die provided in this specification;

[0050] Figure 4 It is a schematic vertical cross-sectional view of a system-on-chip provided in this specification;

[0051] Figure 5 It is a schematic diagram of the micro-pad array layer of a single structural module provided in this specification;

[0052] Figure 6 Schematic diagram of the redistribution layer in the second adaptation module provided in this specification;

[0053] Figure 7 Schematic diagram of a wafer substrate layout generation device provided in this specification;

[0054] Figure 8 Provided in this specification corresponding to Figure 1 Schematic diagram of an electronic device. Detailed implementation manners

[0055] To make the objectives, technical solutions, and advantages of this specification clearer, the technical solutions of this specification will be clearly and completely described below in conjunction with the specific embodiments of this specification and the corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this specification, rather than all the embodiments. Based on the embodiments in this specification, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the scope of protection of this specification.

[0056] The following will detail the technical solutions provided in each embodiment of this specification with reference to the drawings.

[0057] Figure 1 Flow schematic diagram of a wafer substrate layout generation method provided in this specification, including the following steps:

[0058] S101: Obtain the pin information of the dies to be connected, where the pin information includes: the position information of each pin of the die and the function information of each pin of the die.

[0059] Currently, due to the increasing development of the system-on-chip technology, the structure of the system-on-chip has gradually become highly integrated and complex. This requires mounting various heterogeneous dies for implementing different functions on the wafer substrate to form a highly integrated system-on-chip. However, due to the different specifications of various heterogeneous dies, it is difficult to design the layout of the wafer substrate.

[0060] For example: There are heterogeneous die A and heterogeneous die B. Among them, heterogeneous die A is rectangular, including 4 high-speed signal pins, 4 low-speed signal pins, 2 configuration signal pins, 2 clock signal pins, and 8 power signal pins, specifically as Figure 2 shown, Figure 2 where different graphics represent different signal pins.

[0061] Heterogeneous die B is square, including 16 low-speed signal pins, 4 configuration signal pins, 4 clock signal pins, and 20 power signal pins, specifically asFigure 3 as shown

[0062] When designing the layout of the wafer substrate, it is necessary to consider the differences in the functions and quantities of the pins of the heterogeneous die A and the heterogeneous die B, which makes it difficult to design the layout of the wafer substrate.

[0063] Based on this, in this specification, the service platform can generate a wafer substrate layout for mounting heterogeneous dies according to the pin information of each pin of the heterogeneous dies to be mounted, and then can prepare a wafer substrate according to the generated wafer substrate layout, and mount the heterogeneous dies on the prepared wafer substrate to obtain an on-chip system. Among them, the above-mentioned pin information includes at least one of the position information of each pin of the heterogeneous die and the function information of each pin of the heterogeneous die.

[0064] To further elaborate on the above content, this specification also provides a schematic vertical cross-section diagram of an on-chip system prepared by the above-mentioned wafer substrate layout generation method, specifically as Figure 4 shown

[0065] Figure 4 This is a schematic vertical cross-section diagram of an on-chip system provided in this specification.

[0066] In Figure 4 , the on-chip system is composed of two heterogeneous dies A to be mounted, one heterogeneous die B, and a wafer substrate. The wafer substrate is composed of a first adaptation module and each structural module. Among them, one side of the first adaptation module is used to bond with the pins of each die with different functions, and the other side of the first adaptation module is used to bond with the micro-bump array layer of each structural module. The layout corresponding to each structural module is the same (that is, each layer structure included in each structural module is the same). Each structural module corresponds to each die one by one. The structural module is composed of a micro-bump array layer, a through-silicon via layer, at least one redistribution layer, and at least one via layer. The first adaptation module is composed of a redistribution layer and a via layer.

[0067] It should be noted that in Figure 4 , the number of layers of each layer structure of the first adaptation module is less than the number of layers of each layer structure of each structural module, which is due to the different functions of the first adaptation module and each structural module and the different lithography technologies used.

[0068] Among them, the first adaptation module is used to connect each pin of each heterogeneous die to the corresponding micro-pad in the micro-pad array of the corresponding structure module for each heterogeneous die (for example: the pins for transmitting clock signals correspond to the micro-pads for transmitting clock signals). Among them, for some pins with the same function in the heterogeneous die (for example: the four pins for power supply can be merged), they can also be merged through the re-wiring layer in the first adaptation module, so that the heterogeneous die can be connected to the corresponding structure module.

[0069] The structure module is used to interconnect the pins that need to be connected to each other between heterogeneous dies. For example: through the metal lines in the re-wiring layer and the vias in the via layer, connect the pins for transmitting low-speed signals in heterogeneous die A to the pins for transmitting low-speed signals in heterogeneous die B to achieve signal transmission between heterogeneous dies.

[0070] In addition, the structure module is also used to connect the pins with the same function of heterogeneous dies to form a network and connect it to the through-silicon via layer at the bottom. The networks here include: power supply network, ground network, configuration network, clock network, signal transmission network, etc.

[0071] For example: through the metal lines in the re-wiring layer and the vias in the via layer, connect the pins for power supply in heterogeneous die A together to form a power supply network.

[0072] For another example: through the metal lines in the re-wiring layer and the vias in the via layer, connect the pins for grounding in heterogeneous die A together to form a ground network.

[0073] It can be seen from the above content that the types of pins of different heterogeneous dies may be different. For example: heterogeneous die A contains high-speed signal pins, while heterogeneous die B does not contain high-speed signal pins. For another example: heterogeneous die B contains clock signal pins, while heterogeneous die A does not contain clock signal pins.

[0074] The first adaptation module is only used to control the connection of each pin of the heterogeneous die to the corresponding micro-pad in the micro-pad array of the corresponding structure module, and to merge some pins with the same function in the heterogeneous die to adapt to the differences in the size, number, and position of pins of different heterogeneous dies, but it cannot adapt to the differences in the types of pins of different heterogeneous dies.

[0075] Therefore, when designing the structural modules, each structural module needs to be compatible with each die to be mounted. This makes the types of pins corresponding to the micro - pad array on the structural module be the union of the types of pins included in each heterogeneous die to be mounted. Specifically, as shown in Figure 5 shown.

[0076] Figure 5 This is a schematic diagram of the micro - pad array layer of a single structural module provided in this specification.

[0077] From Figure 5 it can be seen that if the heterogeneous die A includes 4 high - speed signal pins, 4 low - speed signal pins, 2 configuration signal pins, 2 clock signal pins, and 8 power signal pins, and the heterogeneous die B includes 16 low - speed signal pins, 4 configuration signal pins, 4 clock signal pins, and 20 power signal pins.

[0078] In actual application scenarios, the micro - pads corresponding to the configuration signal pins of different heterogeneous dies are often different. Therefore, in Figure 4 , each structural module needs to have 2 micro - pads corresponding to the configuration signal pins of the heterogeneous die A (i.e., the two pentagons marked with A in Figure 4 ), and 4 micro - pads corresponding to the configuration signal pins of the heterogeneous die B (i.e., the four pentagons marked with B in Figure 4 ).

[0079] The low - speed signal pins of different heterogeneous dies can often be shared. Therefore, in Figure 4 , each structural module only needs to have 16 micro - pads corresponding to the low - speed signal pins (i.e., the squares in Figure 4 ). Among them, when the structural module is connected to the heterogeneous die A through the first adaptation module, only 4 of the 16 micro - pads corresponding to the low - speed signal pins are needed.

[0080] It can be seen from the above that the layout of the structural module can be determined according to the categories and quantities of different pins of the heterogeneous dies to be mounted, and whether the corresponding micro - pads can be shared, so that there are redundant micro - pads in the micro - pad array included in each structural module, that is, the micro - pads required by other heterogeneous dies but not required by the currently connected heterogeneous die.

[0081] Furthermore, the lithography technologies based on which the above - mentioned first adaptation module, second adaptation module, and each structural module are generated are different. Among them, the lithography technologies based on which the first adaptation module and the second adaptation module are generated can be global exposure lithography, and the lithography technology based on which each structural module is generated can be step - and - repeat lithography.

[0082] It should be noted that in global exposure lithography, the copper Cu and silicon dioxide SiO2 used for the metal wires to construct each layer structure are prepared into each layer structure by means of ramp growth. As a result, when the number of layers of the structures of the first adaptation module combined is relatively large, the surface of each subsequently grown layer structure will be uneven, which will reduce the accuracy of lithography. Therefore, the number of layers of the first adaptation module and the second adaptation module prepared by global exposure lithography cannot exceed a preset value.

[0083] In an actual application scenario, the other side of the structure module also needs to be connected to the auxiliary power supply board. Therefore, a second adaptation module can also be provided between each structure module and the auxiliary power supply board. One side of the second adaptation module is used for bonding with the through-silicon via layer of each structure module, and the other side of the second adaptation module is used for bonding with the auxiliary power supply board. Here, the second adaptation module can include a redistribution layer.

[0084] From Figure 4 it can be seen that the second adaptation module is composed of a redistribution layer. The second adaptation module can form micro-vias corresponding to the pins of each heterogeneous die to be mounted through the redistribution layer, and then can be connected to the auxiliary power supply board through the above-mentioned micro-vias.

[0085] It should be noted that since the types of pins of each heterogeneous die are different, the structure modules corresponding to each heterogeneous die are in different regions in the second adaptation module, and each region contains micro-vias for connecting the pins of different heterogeneous dies to the auxiliary power supply board.

[0086] To further elaborate on the above-mentioned second adaptation module, the present specification also provides a schematic diagram of the redistribution layer in the second adaptation module, specifically as Figure 6 shown.

[0087] From Figure 6 it can be seen that since the second adaptation module needs to be adapted to different heterogeneous dies to be mounted, the redistribution layer of the second adaptation module contains micro-vias corresponding to the pins of each heterogeneous die that need to be connected to the auxiliary power supply board. In Figure 6 , the figure marked with A is the micro-via corresponding to the pin of heterogeneous die A, the figure marked with B is the micro-via corresponding to the pin of heterogeneous die B, and the other figures are micro-vias corresponding to the pins of both heterogeneous die A and heterogeneous die B. In other words, they are the micro-vias shared by some pins of heterogeneous die A and some pins of heterogeneous die B.

[0088] In this specification, the execution entity for implementing the method for generating the layout of a wafer substrate may refer to a specified device such as a server set up on a service platform, or may refer to a specified device such as a desktop computer or a laptop computer. For the sake of convenience in description, hereinafter, only the case where the server is the execution entity will be taken as an example to illustrate the method for generating the layout of a wafer substrate provided in this specification.

[0089] S102: Determine the connection relationship between the pins of the chiplet according to the pin information.

[0090] S103: Generate the layout corresponding to the micro-bump array layer of the structural module, the layout corresponding to the through-silicon via layer of the structural module, and generate the layout corresponding to each layer of the redistribution layer and via layer of the first adaptation module. The layout is used to represent the quantity and position distribution information of each basic unit required for each layer of the structure constituting the wafer substrate. The basic units include at least one of metal wires, vias, and through-silicon vias.

[0091] Furthermore, the server can determine the connection relationship between the pins according to the pin information of each pin of each heterogeneous chiplet to be connected as needed, and generate the layout corresponding to the micro-bump array layer of the structural module and the layout corresponding to each layer of the redistribution layer and via layer of the first adaptation module according to the determined connection relationship. Here, the layout is used to represent the quantity and position distribution information of each basic unit required for each layer of the structure constituting the wafer substrate. The basic units include at least one of metal wires, vias, and through-silicon vias.

[0092] The above connection relationship can include two types, namely, the connection relationship between the pins of a heterogeneous chiplet, and the connection relationship between the pins of a heterogeneous chiplet and the pins of other heterogeneous chiplets.

[0093] Specifically, the server can determine the connection relationship between the pins of each chiplet according to the pin information of each pin of the chiplet for each chiplet. And, for each chiplet, the server can determine the connection relationship between the pins of the chiplet and the pins of other chiplets according to the pin information of each pin of each chiplet.

[0094] Furthermore, after the server generates the layout corresponding to the micro-bump array layer of the structural module and the layout corresponding to each layer of the redistribution layer and via layer of the first adaptation module, it can also perform anomaly detection on the generated layout to avoid problems such as unreasonable layout of each basic unit in the generated layout.

[0095] Specifically, the server may use the layout corresponding to the micro-pad array layer of the generated structural module and the layout corresponding to each layer of the rewiring layer and via layer of the generated first adaptation module as the initial layout corresponding to the micro-pad array layer of the structural module and the initial layout corresponding to each layer of the rewiring layer and via layer of the first adaptation module.

[0096] Furthermore, the server may determine whether there is an abnormality when preparing the wafer substrate according to the initial layout corresponding to the micro-pad array layer of the structural module based on the quantity and position distribution information of each basic unit included in the initial layout, and the quantity and position distribution information of each basic unit included in the initial layout corresponding to each layer of the rewiring layer and via layer of the first adaptation module.

[0097] If so, regenerate the initial layout corresponding to the micro-pad array layer of the structural module and the initial layout corresponding to each layer of the rewiring layer and via layer of the first adaptation module. If not, use the initial layout corresponding to the micro-pad array layer of the structural module and the initial layout corresponding to each layer of the rewiring layer and via layer of the first adaptation module as the final layout corresponding to the micro-pad array layer of the structural module and the final layout corresponding to each layer of the rewiring layer and via layer of the first adaptation module.

[0098] The method for determining whether there is an abnormality in the above layout may be to perform power integrity analysis and signal integrity analysis based on the quantity and position distribution information of each basic unit included in the layout. Here, the power integrity analysis includes: the voltage drop range of each voltage domain and the current density. Here, the signal integrity analysis includes: the insertion loss, return loss, eye diagram, and bit error rate of the signal.

[0099] It should be noted that when the server performs abnormality detection on the initial layout corresponding to the micro-pad array layer of the structural module, it does not need to detect each structural module, but only needs to detect any one of them. Specifically, the server may determine whether there is an abnormality when preparing the wafer substrate according to the quantity and position distribution information of each basic unit included in the initial layout corresponding to any one of the structural modules.

[0100] Similarly, when the server performs abnormality detection on the first adaptation module, it only needs to determine whether there is an abnormality when preparing the wafer substrate according to the quantity and position distribution information of each basic unit included in at least part of the initial layout corresponding to each layer of the rewiring layer and via layer of the first adaptation module.

[0101] Further, after the server generates the layout corresponding to the micro-pad array layer of the final structure module and the layout corresponding to each layer of the redistribution layer and via layer of the first adaptation module, it can also generate the layout corresponding to the through-silicon via layer of the structure module according to the connection relationship between the pins of each heterogeneous die.

[0102] S104: Generate the layout corresponding to each layer of the redistribution layer and each layer of the via layer that make up the structure module, and generate the layout corresponding to the second adaptation module, according to the layout corresponding to the micro-pad array layer of the structure module and the layout corresponding to the through-silicon via layer of the structure module.

[0103] After the server generates the layout corresponding to the micro-pad array layer of the structure module and the layout corresponding to the through-silicon via layer of the structure module, it can generate the layout corresponding to each layer of the redistribution layer and each layer of the via layer that make up the structure module, according to the generated layout corresponding to the micro-pad array layer of the structure module and the layout corresponding to the through-silicon via layer of the structure module.

[0104] Further, for each structure module, the server can also generate the layout corresponding to the area of the second adaptation module corresponding to the structure module, according to the pin information of the die corresponding to the structure module and the layout corresponding to the through-silicon via layer of the structure module.

[0105] In addition, before the server generates the layout corresponding to the area of the second adaptation module corresponding to each structure module, according to the pin information of the die corresponding to the structure module and the layout corresponding to the through-silicon via layer of the structure module, it can also detect each layer of the structure corresponding to the structure module.

[0106] Specifically, the server can also determine whether there is an abnormality when fabricating the structure module according to the layout corresponding to each layer of the structure of any one of the structure modules, based on the number and position distribution information of each basic unit included in the layout corresponding to each layer of the structure of any one of the structure modules. If so, regenerate the layout corresponding to each layer of the structure of any one of the above-mentioned structure modules. If not, for each structure module, generate the layout corresponding to the area of the second adaptation module corresponding to the structure module, according to the pin information of the die corresponding to the structure module and the layout corresponding to the through-silicon via layer of the structure module.

[0107] S105: Determine the layout corresponding to the wafer substrate, according to the layout corresponding to each layer of the structure required to form the first adaptation module, the structure module, and the second adaptation module.

[0108] Further, after obtaining the layout corresponding to each layer structure of the first adaptation module, the layout corresponding to each layer structure of the structure module, and the layout corresponding to each layer structure of the second adaptation module that make up the wafer substrate, the layout corresponding to the wafer substrate is obtained.

[0109] As can be seen from the above content, the server can divide the various layer structures that make up the wafer substrate into two different modules, and when generating the layouts corresponding to the first adaptation module and the structure module, they can be generated respectively based on different lithography processes. The first adaptation module is used to adapt between the structure module and the heterogeneous heterogeneous die, the structure module is used to implement the corresponding structural function connection, and the second adaptation module is used to adapt between the structure module and the auxiliary power supply board. Furthermore, a wafer substrate layout that can be adapted to various heterogeneous heterogeneous dies can be generated.

[0110] The above is the method for generating a wafer substrate layout provided by one or more embodiments of this specification. Based on the same idea, this specification also provides a corresponding wafer substrate layout generation device, as Figure 7 shown.

[0111] Figure 7 The schematic diagram of a wafer substrate layout generation device provided by this specification includes:

[0112] An acquisition module 701, configured to acquire the pin information of the die to be connected, where the pin information includes: the position information of each pin of the die and the function information of each pin of the die;

[0113] A first determination module 702, configured to determine the connection relationship between the pins of the die according to the pin information;

[0114] A first generation module 703, configured to generate the layout corresponding to the micro-bump array layer of the structure module, the layout corresponding to the through-silicon via layer of the structure module, and generate the layout corresponding to each layer of the redistribution layer and via layer of the first adaptation module according to the connection relationship. The layout is used to represent the quantity and position distribution information of each basic unit required for each layer structure that makes up the wafer substrate. The basic unit includes at least one of a metal wire, a via, and a through-silicon via;

[0115] A second generation module 704, configured to generate the layout corresponding to each layer of the redistribution layer and each layer of the via layer that make up the structure module, and generate the layout corresponding to the second adaptation module according to the layout corresponding to the micro-bump array layer of the structure module and the layout corresponding to the through-silicon via layer of the structure module;

[0116] The second determination module 705 is configured to determine the layout corresponding to the wafer substrate according to the layout corresponding to each layer of the structure required for the composition of the first adaptation module, the structure module, and the second adaptation module.

[0117] Optionally, the first determination module 702 is specifically configured to, for each die, determine the connection relationship between the pins of the die according to the pin information of each pin of the die.

[0118] Optionally, the first determination module 702 is specifically configured to, for each die, determine the connection relationship between the pins of the die and the pins of other dies according to the pin information of each pin of each die.

[0119] Optionally, the first generation module 703 is specifically configured to generate an initial layout corresponding to each layer of the redistribution layer and the via layer of the first adaptation module according to the connection relationship; determine whether there is an abnormality when preparing the wafer substrate according to the initial layout corresponding to each layer of the redistribution layer and the via layer of the first adaptation module based on the quantity and position distribution information of each basic unit included in the initial layout corresponding to each layer of the redistribution layer and the via layer of the first adaptation module; if so, regenerate the initial layout corresponding to each layer of the redistribution layer and the via layer of the first adaptation module; if not, use the initial layout corresponding to each layer of the redistribution layer and the via layer of the first adaptation module as the layout corresponding to each layer of the redistribution layer and the via layer of the first adaptation module.

[0120] Optionally, the first generation module 703 is specifically configured to determine whether there is an abnormality when preparing the wafer substrate according to the initial layout corresponding to each layer of the redistribution layer and the via layer of the first adaptation module based on the quantity and position distribution information of each basic unit included in at least part of the initial layout corresponding to each layer of the redistribution layer and the via layer of the first adaptation module.

[0121] Optionally, the second generation module 704 is specifically configured to, for each structure module, generate the layout corresponding to the area corresponding to the structure module in the second adaptation module according to the pin information of the die corresponding to the structure module and the layout corresponding to the through-silicon via layer of the structure module.

[0122] Optionally, the second generation module 704 is specifically configured to determine whether there is an abnormality when preparing the structure module according to the layout corresponding to each layer of the structure of any one of the structure modules based on the quantity and position distribution information of each basic unit included in the layout corresponding to each layer of the structure of the any one of the structure modules; if not, for each structure module, generate the layout corresponding to the area corresponding to the structure module in the second adaptation module according to the pin information of the die corresponding to the structure module and the layout corresponding to the through-silicon via layer of the structure module.

[0123] This specification also provides a computer-readable storage medium storing a computer program that can be used to execute the Figure 1 method provided above.

[0124] This specification also provides Figure 8 a schematic structural diagram of an electronic device corresponding to Figure 1 as shown. As Figure 8 shown, at the hardware level, the electronic device includes a processor, an internal bus, a network interface, a memory, and a non-volatile memory. Of course, it may also include other hardware required for other services. The processor reads the corresponding computer program from the non-volatile memory into the memory and then runs it to implement the Figure 1 method described above.

[0125] Of course, in addition to the software implementation, this specification does not exclude other implementation methods, such as logic devices or a combination of software and hardware, etc. That is to say, the execution subject of the following processing flow is not limited to each logic unit, and can also be hardware or a logic device.

[0126] In the 1990s, improvements to a technology could be clearly distinguished as either hardware improvements (e.g., improvements to circuit structures such as diodes, transistors, switches, etc.) or software improvements (improvements to method flows). However, with the development of technology, many method flow improvements today can be regarded as direct improvements to hardware circuit structures. Designers almost always obtain the corresponding hardware circuit structure by programming the improved method flow into the hardware circuit. Therefore, it cannot be said that an improvement to a method flow cannot be implemented using a hardware entity module. For example, a Programmable Logic Device (PLD) (such as a Field Programmable Gate Array (FPGA)) is an integrated circuit whose logical function is determined by the user programming the device. Designers can program themselves to "integrate" a digital system onto a single PLD, without having to ask a chip manufacturer to design and fabricate a dedicated integrated circuit chip. Moreover, nowadays, instead of manually fabricating integrated circuit chips, this programming is mostly implemented using "logic compiler" software, which is similar to the software compiler used in program development and writing. The original code before compilation also has to be written in a specific programming language, which is called a Hardware Description Language (HDL), and there is not just one type of HDL, but many types, such as ABEL (Advanced Boolean Expression Language), AHDL (Altera Hardware Description Language), Confluence, CUPL (Cornell University Programming Language), HDCal, JHDL (Java Hardware Description Language), Lava, Lola, MyHDL, PALASM, RHDL (Ruby Hardware Description Language), etc. The most commonly used ones currently are VHDL (Very-High-Speed Integrated Circuit Hardware Description Language) and Verilog. Those skilled in the art should also be aware that by simply performing a little logical programming on the method flow using the above-mentioned several hardware description languages and programming it into the integrated circuit, it is easy to obtain the hardware circuit that implements the logical method flow.

[0127] The controller can be implemented in any suitable manner. For example, the controller can take the form of, for example, a microprocessor or a processor and a computer-readable medium storing computer-readable program code (such as software or firmware) executable by the (micro)processor, logic gates, switches, an Application Specific Integrated Circuit (ASIC), a programmable logic controller, and an embedded microcontroller. Examples of the controller include, but are not limited to, the following microcontrollers: ARC 625D, Atmel AT91SAM, Microchip PIC18F26K20, and Silicone Labs C8051F320. The memory controller can also be implemented as part of the control logic of the memory. Those skilled in the art also know that in addition to implementing the controller in the form of pure computer-readable program code, it is entirely possible to logically program the method steps to enable the controller to be implemented in the form of logic gates, switches, ASICs, programmable logic controllers, embedded microcontrollers, etc. to achieve the same functions. Therefore, such a controller can be considered a hardware component, and the devices included therein for implementing various functions can also be regarded as the structures within the hardware component. Or even, the devices for implementing various functions can be regarded as either software modules for implementing the method or the structures within the hardware component.

[0128] The systems, devices, modules, or units illustrated in the above embodiments can be specifically implemented by computer chips or entities, or by products with certain functions. A typical implementation device is a computer. Specifically, the computer can be, for example, a personal computer, a laptop computer, a cellular phone, a camera phone, a smart phone, a personal digital assistant, a media player, a navigation device, an email device, a game console, a tablet computer, a wearable device, or any combination of these devices.

[0129] For the convenience of description, when describing the above devices, they are described separately as various units according to their functions. Of course, when implementing this specification, the functions of each unit can be implemented in the same or multiple software and / or hardware.

[0130] Those skilled in the art should understand that the embodiments of this specification can be provided as a method, a system, or a computer program product. Therefore, this specification can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, this specification can take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk memories, CD-ROMs, optical memories, etc.) containing computer-usable program code.

[0131] This specification is described with reference to the flowcharts and / or block diagrams of methods, apparatuses (systems), and computer program products according to embodiments of the specification. It should be understood that each flow and / or block in the flowchart and / or block diagram, and combinations of flows and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to the processors of general-purpose computers, special-purpose computers, embedded processors, or other programmable data processing devices to produce a machine, such that the instructions executed by the processors of the computer or other programmable data processing devices produce means for implementing the functions specified in one flow Figure 1 one flow or multiple flows and / or blocks Figure 1 or means for implementing the functions specified in one block or multiple blocks.

[0132] These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, such that the instructions stored in the computer-readable memory produce a manufactured article including instruction means that implement the functions specified in one flow Figure 1 one flow or multiple flows and / or blocks Figure 1 or means for implementing the functions specified in one block or multiple blocks.

[0133] These computer program instructions can also be loaded onto a computer or other programmable data processing device, such that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, and thus the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one flow Figure 1 one flow or multiple flows and / or blocks Figure 1 or means for implementing the functions specified in one block or multiple blocks.

[0134] In a typical configuration, a computing device includes one or more processors (CPUs), an input / output interface, a network interface, and memory.

[0135] The memory may include non-permanent memory in the form of computer-readable media, random access memory (RAM), and / or non-volatile memory, such as read-only memory (ROM) or flash memory. The memory is an example of computer-readable media.

[0136] Computer readable media include permanent and non-permanent, removable and non-removable media that can be implemented by any method or technology to store information. Information can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device. As defined herein, computer readable media does not include temporary computer readable media (transitory media), such as modulated data signals and carrier waves.

[0137] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0138] Those skilled in the art will appreciate that the embodiments of this specification may be provided as methods, systems or computer program products. Therefore, this specification may take the form of a complete hardware embodiment, a complete software embodiment or an embodiment combining software and hardware. Moreover, this specification may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0139] This specification may be described in the general context of computer-executable instructions executed by a computer, such as program modules. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform specific tasks or implement specific abstract data types. This specification may also be practiced in distributed computing environments where tasks are performed by remote processing devices connected through a communication network. In a distributed computing environment, program modules may be located in local and remote computer storage media, including storage devices.

[0140] Each embodiment in this specification is described in a progressive manner. For the same or similar parts among the embodiments, reference can be made to each other, and the differences between each embodiment and other embodiments are emphasized. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and for the relevant parts, reference can be made to the description of the method embodiment.

[0141] The above description is only for the embodiments of this specification and is not intended to limit this specification. For those skilled in the art, various modifications and changes can be made to this specification. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of this specification shall be included within the scope of the claims of this specification.

Claims

1. A method for generating a layout of a wafer substrate, characterized in that, The method is applied to generate the layout of a wafer substrate. The wafer substrate includes: a first adaptation module, a second adaptation module, and each structural module. Wherein, the layout corresponding to each structural module is the same, and each structural module corresponds to each die one by one. The structural module is composed of a micro-pad array layer, a through-silicon via layer, at least one redistribution layer, and at least one via layer. One side of the first adaptation module is used to bond with the pins of each die with different functions, and the other side of the first adaptation module is used to bond with the micro-pad array layer of each structural module. One side of the second adaptation module is used to bond with the through-silicon via layer of each structural module, and the other side of the second adaptation module is used to bond with an auxiliary power supply board. The method includes: Obtain the pin information of the dies to be connected. The pin information includes: the position information of each pin of the die and the function information of each pin of the die; Determine the connection relationship between the pins of the die according to the pin information; Generate the layout corresponding to the micro-pad array layer of the structural module, the layout corresponding to the through-silicon via layer of the structural module, and generate the layout corresponding to each redistribution layer and via layer of the first adaptation module according to the connection relationship. The layout is used to represent the quantity and position distribution information of each basic unit required for each layer structure constituting the wafer substrate. The basic unit includes at least one of metal wires, vias, and through-silicon vias; Generate the layout corresponding to each redistribution layer and each via layer of the structural module and generate the layout corresponding to the second adaptation module according to the layout corresponding to the micro-pad array layer of the structural module and the layout corresponding to the through-silicon via layer of the structural module; Determine the layout corresponding to the wafer substrate according to the layout corresponding to each layer structure required for the first adaptation module, the structural module, and the second adaptation module; 2. The method according to claim 1, characterized in that, Determine the connection relationship between the pins of the die according to the pin information, specifically including: For each die, determine the connection relationship between the pins of the die according to the pin information of each pin of the die; 3. The method according to claim 1, characterized in that Determine the connection relationship between the pins of the die according to the pin information, specifically including: For each die, determine the connection relationship between the pins of the die and the pins of other dies according to the pin information of each pin of each die; 4. The method according to claim 1, characterized in that Generate the layout corresponding to each redistribution layer and via layer of the first adaptation module according to the connection relationship, specifically including: Generate the initial layout corresponding to each redistribution layer and via layer of the first adaptation module according to the connection relationship; Judge whether there is an abnormality when preparing the wafer substrate according to the quantity and position distribution information of each basic unit included in the initial layout corresponding to each redistribution layer and via layer of the first adaptation module; If so, regenerate the initial layout corresponding to each redistribution layer and via layer of the first adaptation module; Otherwise, use the initial layout corresponding to each layer of the redistribution layer and via layer of the first adaptation module as the layout corresponding to each layer of the redistribution layer and via layer of the first adaptation module.

5. The method according to claim 4, wherein Based on the quantity and position distribution information of each basic unit included in the initial layout corresponding to each layer of the redistribution layer and via layer of the first adaptation module, determine whether there is an abnormality when preparing the wafer substrate according to the initial layout corresponding to each layer of the redistribution layer and via layer of the first adaptation module. Specifically, it includes: Based on the quantity and position distribution information of each basic unit included in at least part of the initial layout in the initial layout corresponding to each layer of the redistribution layer and via layer of the first adaptation module, determine whether there is an abnormality when preparing the wafer substrate according to the initial layout corresponding to each layer of the redistribution layer and via layer of the first adaptation module.

6. The method according to claim 1, characterized in that, Generate the layout corresponding to the second adaptation module. Specifically, it includes: For each structural module, generate the layout corresponding to the area of the second adaptation module corresponding to this structural module according to the pin information of the die corresponding to this structural module and the layout corresponding to the through-silicon via layer of this structural module.

7. The method according to claim 6, wherein For each structural module, generate the layout corresponding to the area of the second adaptation module corresponding to this structural module according to the pin information of the die corresponding to this structural module and the layout corresponding to the through-silicon via layer of this structural module. Specifically, it includes: Based on the quantity and position distribution information of each basic unit included in the layout corresponding to each layer of the structure of any one structural module, determine whether there is an abnormality when preparing this structural module according to the layout corresponding to each layer of the structure of any one structural module. Otherwise, for each structural module, generate the layout corresponding to the area of the second adaptation module corresponding to this structural module according to the pin information of the die corresponding to this structural module and the layout corresponding to the through-silicon via layer of this structural module.

8. A wafer substrate layout generation device, characterized in that, It includes: An acquisition module, configured to acquire the pin information of the die to be connected, where the pin information includes: the position information of each pin of the die, and the function information of each pin of the die. A first determination module, configured to determine the connection relationship between the pins of the die according to the pin information. A first generation module, configured to generate the layout corresponding to the micro-pad array layer of the structural module, the layout corresponding to the through-silicon via layer of the structural module, and generate the layout corresponding to each layer of the redistribution layer and via layer of the first adaptation module according to the connection relationship. The layout is used to represent the quantity and position distribution information of each basic unit required for each layer of the structure constituting the wafer substrate. The basic unit includes at least one of a metal wire, a via, and a through-silicon via. A second generation module, configured to generate the layout corresponding to each layer of the redistribution layer and each layer of the via layer constituting the structural module, and generate the layout corresponding to the second adaptation module according to the layout corresponding to the micro-pad array layer of the structural module and the layout corresponding to the through-silicon via layer of the structural module. A second determination module, configured to determine the layout corresponding to the wafer substrate according to the layout corresponding to each layer of the structure required for constituting the first adaptation module, the structural module, and the second adaptation module.

9. The device according to claim 8, characterized in that Specifically, the first determination module is configured to determine the connection relationship between the pins of each die according to the pin information of each pin of the die.

10. The device according to claim 8, characterized in that, Specifically, the first determination module is configured to determine the connection relationship between the pins of each die and the pins of other dies according to the pin information of each pin of each die.

11. The device according to claim 8, wherein, Specifically, the first generation module is configured to generate an initial layout corresponding to each rewiring layer and via layer of the first adaptation module according to the connection relationship; determine whether there is an abnormality when preparing the wafer substrate according to the initial layout corresponding to each rewiring layer and via layer of the first adaptation module, based on the number and position distribution information of each basic unit included in the initial layout; If so, regenerate the initial layout corresponding to each rewiring layer and via layer of the first adaptation module; If not, use the initial layout corresponding to each rewiring layer and via layer of the first adaptation module as the layout corresponding to each rewiring layer and via layer of the first adaptation module.

12. The device according to claim 11, wherein, Specifically, the first generation module is configured to determine whether there is an abnormality when preparing the wafer substrate according to the initial layout corresponding to each rewiring layer and via layer of the first adaptation module, based on the number and position distribution information of at least some of the basic units included in the initial layout corresponding to each rewiring layer and via layer of the first adaptation module.

13. The device according to claim 8, characterized in that Specifically, the second generation module is configured to generate a layout corresponding to the area of the second adaptation module corresponding to each structural module according to the pin information of the die corresponding to the structural module and the layout corresponding to the through-silicon via layer of the structural module.

14. The device according to claim 8, wherein Specifically, the second generation module is configured to determine whether there is an abnormality when preparing the structural module according to the layout corresponding to each layer structure of any one structural module, based on the number and position distribution information of each basic unit included in the layout corresponding to each layer structure of the any one structural module; If not, for each structural module, generate a layout corresponding to the area of the second adaptation module corresponding to the structural module according to the pin information of the die corresponding to the structural module and the layout corresponding to the through-silicon via layer of the structural module.

15. A computer-readable storage medium, characterized in that, The storage medium stores a computer program, and when the computer program is executed by a processor, the method described in any one of claims 1 to 7 above is implemented.

16. An electronic device, comprising a memory, a processor, and a computer program stored on the memory and executable on the processor, characterized in that, When the processor executes the program, the method described in any one of claims 1 to 7 above is implemented.

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