Wafer loading platform

Abstract

The present invention provides a wafer carrier to improve the thermal uniformity of the wafer. The wafer carrier (10) comprises: a ceramic substrate (20), a cooling substrate (30), and a metal bonding layer (40). The ceramic substrate (20) has a wafer carrier surface (22a) capable of carrying a wafer on its upper surface and has a built-in wafer adsorption electrode (26). The cooling substrate (30) has a coolant flow path (32). The metal bonding layer (40) bonds the ceramic substrate (20) and the cooling substrate (30). Regarding the distance (d) from the top surface of the coolant flow path (32) to the wafer carrier surface (22a) at the upstreammost portion (32U) and the downstreammost portion (32L) of the coolant flow path (32) in the region overlapping the wafer carrier surface (22a) when viewed from above, the distance (d) of the downstreammost portion (32L) is shorter than the distance (d) of the upstreammost portion (32U).

Description

Technical Field

[0001] The present invention relates to a wafer placing table. Background Art

[0002] In the past, there is a known wafer carrier, which includes: a ceramic substrate having a wafer carrier surface and a built-in electrode; a cooling substrate having a coolant flow path; and a bonding layer that bonds the ceramic substrate and the cooling substrate. For example, Patent Documents 1 and 2 describe that, in the wafer carrier, as a cooling substrate, a component made of a metal-based composite material having a linear thermal expansion coefficient similar to that of the ceramic substrate is used. In addition, it is described that a terminal hole for inserting a power supply terminal for supplying power to the electrode, a gas hole for supplying He gas to the back of the wafer, and a lifting pin hole for inserting a lifting pin for lifting the wafer from the wafer carrier surface are provided on the wafer carrier.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent No. 5666748

[0006] Patent Document 2: Japanese Patent No. 5666749 Summary of the invention

[0007] However, the distance from the top surface of the coolant flow path to the chip is constant from the inlet to the outlet of the coolant flow path. Therefore, the chip tends to cool easily near the inlet of the coolant flow path and difficult to cool near the outlet. As a result, sometimes the thermal uniformity of the chip cannot be fully achieved.

[0008] The present invention has been made to solve the above-mentioned problems, and a main object of the present invention is to improve the thermal uniformity of a wafer.

[0009] The wafer loading platform of the present invention comprises:

[0010] A ceramic substrate having a wafer placement surface on an upper surface thereof on which a wafer can be placed and having electrodes built therein;

[0011] a cooling substrate having a cooling medium flow path; and

[0012] a bonding layer bonding the ceramic substrate and the cooling substrate,

[0013] The wafer stage is characterized in that:

[0014] Regarding the distance from the top surface of the coolant flow path to the chip placement surface at the upstream and downstream parts of the coolant flow path in the region overlapping the chip placement surface when viewed from above, the distance at the downstream part is shorter than that at the upstream part.

[0015] In the wafer carrier, the distance from the top surface of the cold medium flow path to the wafer loading surface at the most upstream part and the most downstream part of the cold medium flow path in the region where the cold medium flow path overlaps with the wafer loading surface when viewed from above is shorter than the distance at the most upstream part. When the wafer carrier is used, the cold medium flows from the most upstream part of the cold medium flow path to the most downstream part while taking away heat from the high-temperature wafer, so the temperature of the cold medium flowing in the cold medium flow path increases compared with the most upstream part. On the other hand, the distance from the top surface of the cold medium flow path to the wafer loading surface is shorter in the most downstream part of the cold medium flow path compared with the most upstream part, so the thermal resistance from the top surface of the cold medium flow path to the wafer loading surface is reduced compared with the most upstream part. Therefore, in general, the temperature difference between the position of the wafer loading surface opposite to the most upstream part of the cold medium flow path and the position opposite to the most downstream part can be reduced. Therefore, the thermal uniformity of the wafer is improved.

[0016] In the wafer placement table of the present invention, the distance from the top surface of the coolant flow path to the wafer placement surface may be gradually shortened from the most upstream portion to the most downstream portion of the coolant flow path. This further improves the thermal uniformity of the wafer.

[0017] In the wafer loading platform of the present invention, the distance from the top surface of the coolant flow path to the wafer loading surface can be adjusted by at least one of the distance from the top surface of the coolant flow path to the upper surface of the cooling substrate, the thickness of the bonding layer, and the thickness of the ceramic substrate. The distance from the top surface of the coolant flow path to the wafer loading surface is preferably adjusted by the distance from the top surface of the coolant flow path to the upper surface of the cooling substrate.

[0018] In the wafer loading platform of the present invention, the distance from the top surface of the coolant flow path at the most downstream portion to the wafer loading surface is preferably 50 to 90% of the distance from the top surface of the coolant flow path at the most upstream portion to the wafer loading surface. If the ratio is 90% or less, the thermal uniformity of the wafer W is sufficiently improved. In addition, if the ratio is 50% or more, it is possible to avoid the generation of cracks above the most downstream portion.

[0019] In the chip carrier of the present invention, the cooling substrate can be made of a metal-based composite material, and the bonding layer can be a metal bonding layer. In the structure in which the cooling substrate is a metal-based composite material and the bonding layer is a metal bonding layer, the thermal resistance from the refrigerant flow path to the chip loading surface is small, and therefore, the chip temperature is easily affected by the temperature gradient of the refrigerant. Therefore, the application of the present invention is of great significance. In addition, the thermal conductivity of the metal bonding layer is high, and therefore, it is suitable for heat dissipation. In addition, the cooling substrate made of the ceramic substrate and the metal-based composite material can reduce the thermal expansion difference, and therefore, even if the stress relaxation of the metal bonding layer is low, it is not easy to cause problems.

[0020] The wafer carrier of the present invention may have a hole that penetrates the cooling substrate in the up-down direction, and the coolant flow path may be configured such that the distance from the top surface of the coolant flow path to the wafer loading surface is shorter in the peripheral area of ​​the hole than in the area that deviates from the peripheral area of ​​the hole. Usually, the area just above the hole in the wafer is prone to become a hot spot, but here, the distance from the top surface of the coolant flow path to the wafer loading surface is shorter in the peripheral area of ​​the hole than in the area that deviates from the peripheral area of ​​the hole. Therefore, heat removal from the peripheral area of ​​the hole is promoted. Therefore, the thermal uniformity of the wafer is further improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a longitudinal cross-sectional view of the wafer stage 10 installed in the chamber 94 .

[0022] Figure 2 This is a cross-sectional view when the cross section of the cooling substrate 30 is cut along a horizontal plane passing through the coolant flow path 32 and viewed from above.

[0023] Figure 3 It is a manufacturing process diagram of the wafer placement table 10.

[0024] Figure 4 This is a cross-sectional view when the cross section of the cooling substrate 30 cut along a horizontal plane passing through the coolant flow path 82 is viewed from above.

[0025] Figure 5 This is a longitudinal cross-sectional view of an example in which a portion 32 x having a shorter distance d is provided in the middle of the refrigerant flow path 32 .

[0026] Figure 6 It is a longitudinal cross-sectional view of an example using a ceramic substrate 20 having no FR placement surface.

[0027] Figure 7 It is a longitudinal cross-sectional view of the wafer placement table 210 .

[0028] Figure 8 It is a longitudinal cross-sectional view of the wafer placement table 310 .

[0029] Explanation of symbols

[0030] 10, 210, 310 ... wafer placement table, 20, 320 ... ceramic substrate, 22, 322 ... central portion, 22a, 322a ... wafer placement surface, 24 ... peripheral portion, 24a ... focusing ring placement surface, 26 ... wafer adsorption electrode, 30, 230 ... cooling substrate, 32, 82, 232 ... cooling medium flow path, 32a, 82a, 232a ... inlet, 32b, 32d, 32f, 32h, 32j, 32l, 32n, 32p, 32r…straight part, 32c, 32e, 32g, 32i, 32k, 32m, 32o, 32q…turning part, 32s, 82s, 232s…exit, 32L, 82L, 232L…downstream part, 32U, 82U, 232U…upstream part, 34, 234…flange part, 36…refrigerant supply path, 38…refrigerant discharge path, 40, 240, 340…metal bonding layer, 42…insulating film, 51…terminal hole, 52…DC power supply for wafer adsorption, 53…low-pass filter, 54…power supply terminal, 55…insulating tube, 62…RF power supply, 63…high-pass filter, 64…power supply terminal, 70…clamping component, 70a…inner peripheral step surface, 72…bolt, 78…focusing ring, 94…chamber, 96…setting plate, 98…shower head, 110…joining body, 120…ceramic sintered body, 130…MMC block, 131, 136…MMC disc component, 132…groove, 133, 134…through hole, 135…metal bonding layer, 151a…upper part of terminal hole, 151b…middle part of terminal hole, 151c…lower part of terminal hole, d…distance, W…wafer. DETAILED DESCRIPTION

[0031] Hereinafter, preferred embodiments of the present invention will be described with reference to the accompanying drawings. Figure 1 1 is a longitudinal cross-sectional view of the wafer stage 10 provided in the chamber 94 (a cross-sectional view when cut along a plane including the central axis of the wafer stage 10). Figure 2 This is a cross-sectional view when the cross section of the cooling substrate 30 is cut along a horizontal plane passing through the coolant flow path 32 and viewed from above. Figure 2 The terminal hole 51, power supply terminal 54 and insulation tube 55 are omitted.

[0032] The wafer stage 10 is a member used when CVD or etching is performed on a wafer W using plasma, and is fixed to a mounting plate 96 provided inside a chamber 94 for semiconductor processes. The wafer stage 10 includes a ceramic substrate 20 , a cooling substrate 30 , and a metal bonding layer 40 .

[0033] The ceramic substrate 20 has an outer peripheral portion 24 having an annular focus ring placement surface 24a on the outer periphery of a central portion 22 having a circular wafer placement surface 22a. Hereinafter, the focus ring is sometimes abbreviated as "FR". A wafer W is placed on the wafer placement surface 22a, and a focus ring 78 is placed on the FR placement surface 24a. The ceramic substrate 20 is formed of a ceramic material represented by aluminum oxide, aluminum nitride, etc. The FR placement surface 24a is lowered by one level relative to the wafer placement surface 22a.

[0034] The central portion 22 of the ceramic substrate 20 has a built-in wafer adsorption electrode 26 on the side close to the wafer placement surface 22a. The wafer adsorption electrode 26 is formed of a material containing, for example, W, Mo, WC, MoC, etc. The wafer adsorption electrode 26 is a disk-shaped or mesh-shaped monopolar electrostatic adsorption electrode. The layer on the upper side of the wafer adsorption electrode 26 in the ceramic substrate 20 functions as a dielectric layer. A wafer adsorption DC power supply 52 is connected to the wafer adsorption electrode 26 via a power supply terminal 54. The power supply terminal 54 is inserted into a terminal hole 51 provided between the lower surface of the wafer adsorption electrode 26 and the lower surface of the cooling substrate 30 in the wafer placement table 10. The power supply terminal 54 is provided so as to pass through an insulating tube 55 arranged in a through hole in the terminal hole 51 that penetrates the cooling substrate 30 and the metal bonding layer 40 in the up-down direction, and reach the wafer adsorption electrode 26 from the lower surface of the ceramic substrate 20. A low-pass filter (LPF) 53 is provided between the wafer adsorption DC power supply 52 and the wafer adsorption electrode 26 .

[0035] The cooling substrate 30 is a disk component made of a metal matrix composite material (also referred to as Metal Matrix Composite (MMC)). The cooling substrate 30 is provided with a refrigerant flow path 32 for refrigerant circulation inside. The refrigerant flow path 32 is connected to a refrigerant supply path 36 and a refrigerant discharge path 38, and the refrigerant discharged from the refrigerant discharge path 38 is temperature-adjusted and then returns to the refrigerant supply path 36 again. As MMC, there can be cited: materials containing Si, SiC and Ti, materials obtained by impregnating Al and / or Si in a SiC porous body, etc. The material containing Si, SiC and Ti is referred to as SiSiCTi, the material obtained by impregnating Al in a SiC porous body is referred to as AlSiC, and the material obtained by impregnating Si in a SiC porous body is referred to as SiSiC. When the ceramic substrate 20 is an alumina substrate, as the MMC for cooling the substrate 30, AlSiC, SiSiCTi, etc., whose thermal expansion coefficient is close to that of alumina, are preferably used. The cooling substrate 30 is connected to the RF power supply 62 by means of a power supply terminal 64. A high pass filter (HPF) 63 is disposed between the cooling substrate 30 and the RF power source 62. The cooling substrate 30 has a flange portion 34 for clamping the wafer stage 10 to the installation plate 96 on the lower surface side.

[0036] like Figure 2 As shown, when observing the cross section of the refrigerant flow path 32 cut in a horizontal plane from above, the refrigerant flow path 32 is formed in a single stroke from the inlet 32a to the outlet 32s in the cooling substrate 30 except the flange portion 34. In the present embodiment, the refrigerant flow path 32 is formed in a Z-shape. Specifically, the refrigerant flow path 32 is formed in a Z-shape by starting from the inlet 32a connected to the refrigerant supply path 36 through the straight portion 32b, the return portion 32c, the straight portion 32d, the return portion 32e, the straight portion 32f, the return portion 32g, the straight portion 32h, the return portion 32i, the straight portion 32j, the return portion 32k, the straight portion 32l, the return portion 32m, the straight portion 32n, the return portion 32o, the straight portion 32p, the return portion 32q and the straight portion 32r to reach the outlet 32s connected to the refrigerant discharge path 38. Here, when the uppermost portion 32U and the lowermost portion 32L are determined in the region of the coolant flow path 32 that overlaps with the wafer placement surface 22a when viewed from above, the uppermost portion 32U and the lowermost portion 32L are Figure 2 Regarding the distance d from the top surface of the cooling medium flow path 32 to the wafer placement surface 22a, as shown in FIG. Figure 1 As shown in FIG. 1 , the distance d of the most downstream portion 32L is shorter than that of the most upstream portion 32U. The distance d gradually becomes shorter from the most upstream portion 32U toward the most downstream portion 32L. In this embodiment, the top surfaces of the inlet 32a, outlet 32s, and straight portions 32d, 32f, 32h, 32j, 32l, 32n, and 32p of the refrigerant flow path 32 are as shown in FIG. Figure 1 As shown, it slopes downward from the outlet 32s side toward the inlet 32a side. The bottom surface of the refrigerant flow path 32 is arranged on the same horizontal plane. It should be noted that the distance d at the most downstream portion 32L is preferably 50 to 90% of the distance d at the most upstream portion 32U.

[0037] When the relationship between the position of the refrigerant flow path 32 and the distance d is represented by a curve graph, the distance d may be shortened continuously or in a step-like manner from the most upstream portion 32U toward the most downstream portion 32L, but it is preferably shortened continuously. As for the case where the distance d is shortened continuously from the most upstream portion 32U toward the most downstream portion 32L, for example, it may be shortened continuously at a certain gradient (slope), or it may be shortened by drawing a downward convex curve, or it may be shortened by drawing an upward convex curve.

[0038] The metal bonding layer 40 bonds the lower surface of the ceramic substrate 20 and the upper surface of the cooling substrate 30. The metal bonding layer 40 may be, for example, a layer formed of solder or metal brazing material. The metal bonding layer 40 is formed using, for example, TCB (Thermal Compression Bonding). TCB refers to a well-known method of sandwiching a metal bonding material between two components to be bonded and bonding the two components under pressure while heating to a temperature below the solidus temperature of the metal bonding material.

[0039] The side surface of the outer peripheral portion 24 of the ceramic substrate 20, the outer periphery of the metal bonding layer 40, and the side surface of the cooling substrate 30 are covered with an insulating film 42. Examples of the insulating film 42 include a thermal sprayed film of aluminum oxide, yttrium trioxide, and the like.

[0040] The wafer stage 10 is provided with a clamping member 70, which is mounted on a setting plate 96 provided inside a chamber 94. The clamping member 70 is an annular member having a substantially inverted L-shaped cross section, and has an inner peripheral step surface 70a. The wafer stage 10 and the setting plate 96 are integrated by the clamping member 70. In a state where the inner peripheral step surface 70a of the clamping member 70 is placed on the flange portion 34 of the cooling substrate 30 of the wafer stage 10, a bolt 72 is inserted from the upper surface of the clamping member 70 and screwed into a screw hole provided on the upper surface of the setting plate 96. The bolt 72 is installed at a plurality of locations (e.g., 8 locations, 12 locations) provided at equal intervals along the circumferential direction of the clamping member 70. The clamping member 70 and the bolt 72 may be made of an insulating material or a conductive material (metal, etc.).

[0041] Next, use Figure 3 , a manufacturing example of the wafer placement table 10 is described. Figure 3 1 is a manufacturing process diagram of the wafer stage 10. First, a ceramic powder compact is hot-pressed and fired to produce a disk-shaped ceramic sintered body 120 ( Figure 3 (A)). The ceramic sintered body 120 has a wafer adsorption electrode 26 built therein. Next, a terminal hole upper portion 151a ( Figure 3 (B)). Then, the power supply terminal 54 is inserted into the upper portion 151a of the terminal hole, and the power supply terminal 54 and the chip adsorption electrode 26 are joined ( Figure 3 (C)).

[0042] At the same time, two MMC disk components 131 and 136 are made ( Figure 3 (D)). Then, holes penetrating in the vertical direction are provided in the two MMC disc components 131 and 136, and a groove 132 which eventually becomes the refrigerant flow path 32 is formed on the lower surface of the upper MMC disc component 131 ( Figure 3(E)). Specifically, the terminal hole middle portion 151b is provided on the upper MMC disc member 131. The groove 132 is formed by machining the upper MMC disc member 131 in the same shape as the refrigerant flow path 32. In addition, the terminal hole lower portion 151c, the through hole 133 for the refrigerant supply path, and the through hole 134 for the refrigerant discharge path are provided on the lower MMC disc member 136. When the ceramic sintered body 120 is made of alumina, the MMC disc members 131 and 136 are preferably made of SiSiC or AlSiC. This is because: the thermal expansion coefficient of alumina is substantially the same as that of SiSiC and AlSiC.

[0043] The SiSiCTi disc component can be made, for example, as follows. First, silicon carbide, metal Si and metal Ti are mixed to make a powder mixture. Next, the obtained powder mixture is formed into a disc-shaped molded body by uniaxial pressure molding, and the molded body is hot-pressed and sintered in an inert atmosphere to obtain the SiSiCTi disc component.

[0044] Next, a metal bonding material is arranged between the lower surface of the upper MMC disc component 131 and the upper surface of the lower MMC disc component 136, and a metal bonding material is arranged on the upper surface of the upper MMC disc component 131. Through holes are pre-set at positions of each metal bonding material that are opposite to each hole. Then, the power supply terminal 54 of the ceramic sintered body 120 is inserted into the middle portion 151b of the terminal hole and the lower portion 151c of the terminal hole, and the ceramic sintered body 120 is placed on the metal bonding material arranged on the upper surface of the upper MMC disc component 131. Thus, a stacked body is obtained in which the lower MMC disc component 136, the metal bonding material, the upper MMC disc component 131, the metal bonding material, and the ceramic sintered body 120 are stacked in sequence starting from the bottom. The stacked body is heated and pressurized (TCB) to obtain a joint body 110 ( Figure 3 (F)). The joint body 110 is obtained by joining the ceramic sintered body 120 to the upper surface of the MMC block 130 which is the basis of the cooling substrate 30 by means of the metal bonding layer 40. The MMC block 130 is obtained by joining the upper MMC disc part 131 and the lower MMC disc part 136 by means of the metal bonding layer 135. The MMC block 130 has a refrigerant flow path 32, a refrigerant supply path 36, a refrigerant discharge path 38 and a terminal hole 51. The terminal hole 51 is a hole obtained by connecting the terminal hole upper part 151a, the terminal hole middle part 151b and the terminal hole lower part 151c.

[0045] TCB is performed, for example, as follows. That is, the stack is pressurized and joined at a temperature below the solidus temperature of the metal bonding material (for example, a temperature above the solidus temperature minus 20°C and below the solidus temperature), and then returned to room temperature. Accordingly, the metal bonding material becomes a metal bonding layer. As the metal bonding material at this time, Al-Mg bonding materials and Al-Si-Mg bonding materials can be used. For example, when TCB is performed using an Al-Si-Mg bonding material, the stack is pressurized in a heated state under a vacuum atmosphere. The metal bonding material preferably uses a metal bonding material with a thickness of about 100 μm.

[0046] Next, the outer periphery of the ceramic sintered body 120 is cut to form a step, thereby manufacturing a ceramic substrate 20 having a central portion 22 and an outer peripheral portion 24. In addition, the outer periphery of the MMC block 130 is cut to form a step, thereby manufacturing a cooling substrate 30 having a flange portion 34. In addition, an insulating tube 55 for inserting a power supply terminal 54 is arranged from the lower surface of the ceramic substrate 20 in the terminal hole 51 to the lower surface of the cooling substrate 30. Furthermore, ceramic powder is sprayed on the side of the outer peripheral portion 24 of the ceramic substrate 20, the periphery of the metal bonding layer 40, and the side of the cooling substrate 30, thereby forming an insulating film 42 ( Figure 3 (G)). Thus, the wafer placement table 10 is obtained.

[0047] It should be explained that Figure 1 The cooling substrate 30 is described as an integral part, but it can be Figure 3 The structure in which two members are joined via a metal joining layer as shown in (G) may be a structure in which three or more members are joined via a metal joining layer.

[0048] Next, use Figure 1 , an example of using the wafer stage 10 is described. As described above, the wafer stage 10 is fixed to the setting plate 96 of the chamber 94 by the clamping member 70. A shower head 98 is arranged on the top surface of the chamber 94 to release the process gas into the chamber 94 from a plurality of gas injection holes.

[0049] A focus ring 78 is placed on the FR placement surface 24a of the wafer placement table 10, and a disc-shaped wafer W is placed on the wafer placement surface 22a. The focus ring 78 has a step along the inner circumference of the upper end so that it does not interfere with the wafer W. In this state, a DC voltage of the wafer adsorption DC power supply 52 is applied to the wafer adsorption electrode 26, so that the wafer W is adsorbed on the wafer placement surface 22a. Then, the interior of the chamber 94 is set to a predetermined vacuum atmosphere (or a reduced pressure atmosphere), and while supplying a process gas from the shower head 98, an RF voltage from the RF power supply 62 is applied to the cooling substrate 30. As a result, plasma is generated between the wafer W and the shower head 98. Then, CVD film formation or etching is performed on the wafer W using this plasma. It should be noted that the focus ring 78 is also consumed along with the plasma processing of the wafer W. However, since the focus ring 78 is thicker than the wafer W, the focus ring 78 is replaced after a plurality of wafers W are processed.

[0050] When the wafer W is processed with high-power plasma, it is necessary to cool the wafer W efficiently. In the wafer carrier 10, as the bonding layer between the ceramic substrate 20 and the cooling substrate 30, a metal bonding layer 40 with high thermal conductivity is used instead of a resin layer with low thermal conductivity. Therefore, the ability to take away heat from the wafer W (heat dissipation ability) is high. In addition, since the thermal expansion difference between the ceramic substrate 20 and the cooling substrate 30 is small, even if the stress relaxation of the metal bonding layer 40 is low, it is not easy to cause problems. In addition, compared with the upstreammost part 32U of the coolant flow path 32, the distance d from the top surface of the coolant flow path 32 of the downstreammost part 32L to the wafer loading surface 22a is shortened. Compared with the upstreammost part 32U, the distance d of the downstreammost part 32L is shortened. When the wafer placement table 10 is in use, the coolant flows from the most upstream portion 32U of the coolant flow path 32 to the most downstream portion 32L while taking away heat from the high-temperature wafer W. Therefore, the temperature of the coolant flowing through the coolant flow path 32 in the most downstream portion 32L is higher than that in the most upstream portion 32U. On the other hand, the distance d from the top surface of the coolant flow path 32 to the wafer placement surface 22a in the most downstream portion 32L is shorter than that in the most upstream portion 32U of the coolant flow path 32. Therefore, the thermal resistance from the top surface of the coolant flow path 32 to the wafer placement surface 22a in the most downstream portion 32L is lower than that in the most upstream portion 32U. Therefore, in general, the temperature difference between the position opposite to the most upstream portion 32U of the coolant flow path 32 and the position opposite to the most downstream portion 32L in the wafer placement surface 22a can be reduced. The flow rate of the refrigerant flowing through the refrigerant flow path 32 is preferably 15 to 50 L / min, more preferably 20 to 40 L / min.

[0051] In the chip placement table 10 of the present embodiment described above, the distance d from the top surface of the coolant flow path 32 to the chip placement surface 22a is shorter in the downstream portion 32L than in the upstream portion 32U of the coolant flow path 32, so that the thermal uniformity of the chip W is improved.

[0052] In addition, the distance d gradually decreases from the most upstream portion 32U toward the most downstream portion 32L of the coolant flow path 32. Therefore, the thermal uniformity of the wafer W is further improved.

[0053] In addition, the distance d is adjusted by the distance from the top surface of the coolant flow path 32 to the upper surface of the cooling substrate 30. Therefore, the distance d can be adjusted relatively easily.

[0054] Furthermore, the coolant flow path 32 is formed in a Z-shape when the cooling substrate 30 is viewed from above. Therefore, it is easy to make the coolant flow path 32 extend over the entire cooling substrate 30 .

[0055] Furthermore, the distance d at the most downstream portion 32L is preferably 50 to 90% of the distance d at the most upstream portion 32U. If the ratio is 90% or less, the thermal uniformity of the wafer W is sufficiently improved. If the ratio is 50% or more, the generation of cracks above the most downstream portion 32L can be avoided.

[0056] In addition, the cooling substrate 30 is made of MMC and is bonded to the ceramic substrate 20 by means of a metal bonding layer 40. In the structure in which the cooling substrate 30 is MMC and the bonding layer is the metal bonding layer 40, the thermal resistance from the coolant flow path 32 to the chip loading surface 22a is small, so the chip temperature is easily affected by the temperature gradient of the coolant. Therefore, the application of the present invention is of great significance. In addition, the thermal conductivity of the metal bonding layer 40 is high, and therefore, it is suitable for heat dissipation. In addition, the cooling substrate 30 made of the ceramic substrate 20 and the MMC can reduce the thermal expansion difference, so even if the stress relaxation of the metal bonding layer 40 is low, it is not easy to cause problems.

[0057] It should be noted that the present invention is not limited to the above-described embodiment and can be implemented in various forms as long as they fall within the technical scope of the present invention.

[0058] In the above implementation, it can be Figure 4 The coolant flow path 82 shown in the figure is a spiral coolant flow path 82 in a top view instead of a Z-shaped coolant flow path 32 in a top view. The coolant flow path 82 is formed in a spiral shape in the entire portion of the cooling substrate 30 except for the flange portion 34 in a one-stroke manner from the inlet 82a provided at the center to the outlet 82b provided at the periphery. In this case, when the uppermost portion 82U and the lowermost portion 82L are determined in the region of the coolant flow path 82 that overlaps with the wafer placement surface 22a in a top view, the uppermost portion 82U and the lowermost portion 82L are Figure 4The distance d from the top surface of the coolant flow path 82 to the wafer placement surface 22a is not shown in the figure, but the distance d is shorter in the most downstream portion 32L than in the most upstream portion 32U. The distance d can be formed so as to gradually shorten from the most upstream portion 82U toward the most downstream portion 82L. It should be noted that the outer peripheral portion of the coolant flow path 82 can be set as the inlet and the central portion can be set as the outlet.

[0059] In the above implementation, if Figure 5 As shown, the coolant flow path 32 can be provided with a portion 32x in the peripheral area of ​​the terminal hole 51, and the distance d from the top surface of the coolant flow path 32 to the chip loading surface 22a of the portion 32x is shortened compared with the area of ​​the peripheral area deviating from the terminal hole 51. It should be noted that the coolant flow path 32 is formed in the same shape as the above-mentioned embodiment except that it has the portion 32x, and the distance d of the most downstream part 32L is shortened compared with the most upstream part 32U. In addition, except for the peripheral area of ​​the terminal hole 51, the distance d gradually shortens from the most upstream part U to the most downstream part L of the coolant flow path 32. Usually, the periphery directly above the terminal hole 51 in the chip loading surface 22a is easy to become a hot spot, but here, the peripheral area of ​​the terminal hole 51 is shorter than the area deviating from the peripheral area. Therefore, the heat removal of the peripheral area of ​​the terminal hole 51 is promoted. Therefore, the thermal uniformity of the chip W is further improved. It should be noted that the distance d at the portion 32x is preferably 50 to 90% of the distance d at the most upstream portion 32U.

[0060] In the above implementation, if Figure 6 As shown, the ceramic substrate 20 may have a wafer placement surface 22a but not a FR placement surface. In this case, when the uppermost portion 32U and the lowermost portion 32L are determined in the region overlapping the wafer placement surface 22a in the coolant flow path 32 when viewed from above, the uppermost portion 32U and the lowermost portion 32L are respectively consistent with the inlet 32a and the outlet 32s.

[0061] In the above embodiment, the distance d from the top surface of the coolant flow path 32 to the wafer placement surface 22a is adjusted by the distance from the top surface of the coolant flow path 32 to the upper surface of the cooling substrate 30, but the present invention is not limited thereto. Figure 7 As shown in the wafer carrier 210, the distance d is adjusted by the thickness of the metal bonding layer 240. The wafer carrier 210 is obtained by bonding the ceramic substrate 20 and the cooling substrate 230 with the metal bonding layer 240. The ceramic substrate 20 is the same as the ceramic substrate used in the above-mentioned embodiment, and the thickness of the central portion 22 is uniform. For the cooling substrate 230, the thickness of the central portion except the flange portion 234 is uniform, the distance between the top surface of the coolant flow path 232 and the upper surface of the cooling substrate 230 is also uniform, and the height of the coolant flow path 232 (the length from the bottom surface to the top surface) is also uniform. The shape of the coolant flow path 232 when viewed from above is the same as Figure 2 The bonding layer 240 is also in a Z-shape. The bonding layer 240 is arranged such that the thickness gradually decreases from the inlet 232a to the outlet 232s of the coolant flow path 232. Even so, the distance d between the top surface of the coolant flow path 232 and the wafer placement surface 22a in the most downstream portion 232L can be shortened compared to the most upstream portion 232U of the coolant flow path 232.

[0062] Or, you can do something like Figure 8 As shown in FIG. 3 , the distance d is adjusted by the thickness of the ceramic substrate 320. The wafer stage 310 is obtained by bonding the ceramic substrate 320 and the cooling substrate 230 with a metal bonding layer 340. Figure 7 The ceramic substrate 320 is configured such that the thickness of the central portion 322 gradually decreases from the inlet 232a of the coolant flow path 232 toward the outlet 232s. The thickness of the metal bonding layer 340 is uniform. Even so, the distance d between the top surface of the coolant flow path 232 and the wafer placement surface 322a of the most downstream portion 232L of the coolant flow path 232 can be shortened compared to the most upstream portion 232U of the coolant flow path 232.

[0063] In the above embodiment, the inlet 32a, the outlet 32s, and the top surfaces of the straight portions 32d, 32f, 32h, 32j, 32l, 32n, and 32p of the coolant flow path 32 are inclined surfaces, but they may be horizontal surfaces.

[0064] In the above embodiment, the distance d between the top surface of the cooling medium flow path 32 and the wafer placement surface 22a is gradually shortened from the most upstream portion 32U to the most downstream portion 32L, but the present invention is not limited thereto. The distance d of the most downstream portion 32L may be shorter than that of the most upstream portion 32U, and the distance between the most upstream portion 32U and the most downstream portion 32L may be formed arbitrarily. For example, there may be a section where the distance d is constant between the most upstream portion 32U and the most downstream portion 32L, there may be a section where the distance d gradually increases from the most upstream portion 32U to the most downstream portion 32L, and there may be a section where the distance d changes irregularly.

[0065] In the above-mentioned embodiment, a sealing ring band may be formed along the outer edge of the wafer placing surface 22a, and a plurality of small protrusions may be formed on the entire surface, so that the top surface of the sealing ring band and the top surfaces of the plurality of small protrusions support the wafer W. In this case, the distance d between the top surface of the coolant flow path 32 and the wafer placing surface 22a is the distance between the top surface of the coolant flow path 32 and the top surface of the small protrusions (the top surface of the sealing ring band).

[0066] In the above-mentioned embodiment, the chip loading platform 10 may have a plurality of holes penetrating the chip loading platform 10 in the up-down direction. As the above-mentioned holes, there are a plurality of gas holes that are open on the chip loading surface 22a, and lift pin holes for inserting lift pins that move the chip W up and down relative to the chip loading surface 22a. When looking down at the chip loading surface 22a, a plurality of gas holes are provided at appropriate positions. A heat-conducting gas such as He gas is supplied to the gas holes. Usually, the gas holes are provided so that the portions of the chip loading surface 22a where the sealing belt and the small protrusions are not provided are open. If the heat-conducting gas is supplied to the gas holes, the space on the back side of the chip W loaded on the chip loading surface 22a is filled with the heat-conducting gas. When looking down at the chip loading surface 22a, a plurality of lift pin holes are provided at equal intervals along the concentric circles of the chip loading surface 22a. When the chip loading surface 22a is provided with gas holes and lift pin holes, it can be like Figure 5 As in the portion 32x of the hole, a portion is provided in the peripheral area of ​​the hole where the distance d from the top surface of the coolant channel 32 to the wafer placement surface 22a is shorter than that of the region away from the peripheral area of ​​the hole. Thus, the thermal uniformity of the wafer W is further improved.

[0067] In the above embodiment, the cooling substrate 30 is made of MMC, but the present invention is not particularly limited thereto. The cooling substrate 30 may be made of metal (eg, aluminum, titanium, molybdenum, tungsten, and alloys thereof).

[0068] In the above embodiment, the ceramic substrate 20 and the cooling substrate 30 are bonded via the metal bonding layer 40 , but the present invention is not particularly limited thereto. For example, a resin bonding layer may be used instead of the metal bonding layer 40 .

[0069] In the above embodiment, the wafer adsorption electrode 26 is built into the central portion 22 of the ceramic substrate 20, but instead, an RF electrode for plasma generation may be built into it, or a heater electrode (resistance heating element) may be built into it, or in addition to the wafer adsorption electrode 26, an RF electrode for plasma generation may be built into it, or a heater electrode (resistance heating element) may be built into it. In addition, a focusing ring (FR) adsorption electrode may be built into the outer peripheral portion 24 of the ceramic substrate 20, or an RF electrode or a heater electrode may be built into it.

[0070] In the above embodiment, Figure 3 The ceramic sintered body 120 of (A) is produced by hot pressing a ceramic powder molded body. However, the molded body in this case may be produced by stacking a plurality of tape-cast molded bodies, by die casting, or by compacting ceramic powder.

Claims

1. A wafer loading platform, comprising: A ceramic substrate having a wafer placement surface on an upper surface thereof on which a wafer can be placed and having electrodes built therein; A cooling substrate having a refrigerant flow path; a bonding layer bonding the ceramic substrate and the cooling substrate, and a hole extending through the cooling substrate in the up-down direction, The wafer stage is characterized in that: Regarding the distance from the top surface of the coolant flow path to the chip loading surface at the upstream and downstream parts of the coolant flow path in the area where the coolant flow path overlaps with the chip loading surface when viewed from above, the distance at the downstream part is shorter than that at the upstream part. The coolant flow path is configured such that a distance from a top surface of the coolant flow path to the wafer placement surface is shorter in a peripheral region of the hole than in a region away from the peripheral region of the hole.

2. The wafer stage according to claim 1, wherein: The distance from the top surface of the coolant flow path to the wafer placement surface gradually shortens from the most upstream portion to the most downstream portion of the coolant flow path.

3. The wafer stage according to claim 1 or 2, characterized in that: The distance from the top surface of the coolant flow path to the wafer placement surface is adjusted by at least one of the distance from the top surface of the coolant flow path to the upper surface of the cooling substrate, the thickness of the bonding layer, and the thickness of the ceramic substrate.

4. The wafer stage according to claim 1 or 2, characterized in that: The distance from the top surface of the coolant flow path at the most downstream portion to the wafer placement surface is 50 to 90% of the distance from the top surface of the coolant flow path at the most upstream portion to the wafer placement surface.

5. The wafer stage according to claim 1 or 2, characterized in that: The cooling substrate is made of a metal-based composite material. The bonding layer is a metal bonding layer.

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