Bonding method for a germanium-on-insulator structure substrate
By using plasma bombardment to form oxygen dangling bonds on the silicon and germanium wafer surfaces and combining it with annealing, the problem of mass production of large-size GOI substrates in the prior art has been solved, realizing an efficient and low-cost bonding method.
Patent Information
- Application Number
- CN202310041030.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-01-11
- Publication Date
- 2026-02-13
- Estimated Expiration
- 2043-01-11
AI Technical Summary
Existing technologies make it difficult to mass-produce large-size GOI substrates, and chemical mechanical polishing equipment is expensive, resulting in low production efficiency and high costs.
Plasma bombardment is used instead of chemical mechanical polishing. Oxygen dangling bonds are formed on the surfaces of silicon and germanium wafers, and bonding is achieved by van der Waals forces. Annealing is used to enhance the bonding strength, and an insulating silicon-on-germanium structure substrate is formed by etching and polishing.
This achieves a high degree of flatness in the bonding interface, improving industrial production efficiency and reducing production costs.
Smart Images
Figure CN116110848B_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the field of semiconductor manufacturing and microelectronic devices, and in particular to a bonding method of a germanium-on-insulator structure substrate. BACKGROUND
[0002] With the improvement of the integration of integrated circuits, the intrinsic characteristics of the substrate material gradually begin to appear to be restrictive to the integrated circuits. Compared with Si material, Ge has higher carrier mobility, which can improve the working frequency of the device. The GOI structure substrate combines the double advantages of Ge material and SOI structure, and has broad application prospects under the development trend of optoelectronic interconnection integrated circuits.
[0003] Similar to the preparation of SOI structure, the SmartCut TM technology is currently used to prepare GOI structure substrate. However, due to the limitation of Ge wafer size, the SmartCut TM technology cannot prepare GOI substrate with a larger size, especially for wafer substrates larger than 12 inches. Or through the way of epitaxial germanium to prepare GOI substrate, but this method needs to perform chemical mechanical polishing (CMP) on the wafer to reduce the surface roughness to 0.5 nm or below. However, the chemical mechanical polishing equipment is expensive, and only one sample can be polished at a time, which reduces the work efficiency. SUMMARY
[0004] Based on this, the present application provides a bonding method of a germanium-on-insulator structure substrate, which can process wafers in batches, improve the industrial production efficiency, and reduce the production cost.
[0005] According to one aspect of the present application, a bonding method of a germanium-on-insulator structure substrate is provided, comprising:
[0006] growing a first dielectric layer and a second dielectric layer on the surfaces of a first wafer and a second wafer, respectively;
[0007] performing plasma treatment on the surfaces of the first dielectric layer and the second dielectric layer, then immersing in water and blowing dry;
[0008] aligning and bonding the first dielectric layer and the second dielectric layer after plasma treatment;
[0009] thinning and etching the second wafer to form a germanium-on-insulator structure;
[0010] performing thinning treatment and polishing treatment on the germanium-on-insulator structure to obtain a germanium-on-insulator structure substrate.
[0011] According to an embodiment of the present application, wherein,
[0012] The second wafer includes a wafer with a silicon layer and a germanium epitaxial layer epitaxially grown on the silicon layer, and the thickness of the germanium epitaxial layer is 10-1000 nm.
[0013] According to an embodiment of the present application, the first wafer includes a single-side polished silicon wafer.
[0014] According to an embodiment of the present application, the first wafer includes a single-side polished silicon wafer.
[0015] The first dielectric layer and the second dielectric layer are one of SiO2, Al2O3, Si3N4, HfO2 or a stack of several of SiO2, Al2O3, Si3N4, HfO2.
[0016] The thickness of the first dielectric layer and the second dielectric layer is 10-1000 nm.
[0017] According to an embodiment of the present application, the aligning and bonding of the first dielectric layer and the second dielectric layer after plasma treatment includes:
[0018] The first dielectric layer and the second dielectric layer are aligned and brought close to each other until the first dielectric layer and the second dielectric layer are bonded together.
[0019] The first dielectric layer and the second dielectric layer bonded together are annealed.
[0020] The annealing temperature is 150-450°C and the annealing time is 20-300 min.
[0021] According to an embodiment of the present application, the thinning and etching of the second wafer includes:
[0022] The second wafer is etched until the silicon layer is completely etched away and the germanium epitaxial layer is left, forming a germanium-on-insulator structure.
[0023] According to an embodiment of the present application, the germanium-on-insulator structure is a structure of first wafer / first dielectric layer / second dielectric layer / germanium epitaxial layer.
[0024] According to an embodiment of the present application, in the polishing process of the germanium-on-insulator structure, the polishing depth is 10-500 nm.
[0025] According to an embodiment of the present application, the plasma treatment of the surfaces of the first dielectric layer and the second dielectric layer includes:
[0026] The first wafer and the second wafer are placed in a plasma atmosphere.
[0027] The surface of the first dielectric layer and the second dielectric layer is bombarded by the plasma, the plasma power is 10W-300W, and the gas flow is 10-300ml / min.
[0028] According to the embodiment of the present application, wherein the bombarding the surface of the first dielectric layer and the second dielectric layer by the plasma comprises:
[0029] The surface of the first dielectric layer and the second dielectric layer is bombarded by the plasma at least once;
[0030] The surface of the first dielectric layer and the second dielectric layer is bombarded by the oxygen plasma;
[0031] Or
[0032] The surface of the first dielectric layer and the second dielectric layer is bombarded by the oxygen plasma.
[0033] From the above technical solution, the bonding method of the Ge-on-insulator structure substrate provided by the present application has the following beneficial effects:
[0034] The present application uses plasma bombardment instead of the traditional CMP method to reduce the roughness of the dielectric layer surface, and realizes the high planarization of the bonding interface. The method can process wafers in batches, improve the industrial production efficiency, and reduce the production cost. BRIEF DESCRIPTION OF DRAWINGS
[0035] Figure 1 The bonding flow chart of the Ge-on-insulator structure substrate of the embodiment of the present application. DETAILED DESCRIPTION
[0036] In order to make the purpose, technical scheme and advantages of the present application more clear and obvious, the present application is further described in detail below in combination with specific embodiments and with reference to the drawings.
[0037] Similar to the preparation of SOI structure, the SmartCut TM technology is currently used to prepare GOI structure substrate. However, due to the limitation of Ge wafer size, the SmartCut TM technology cannot prepare GOI substrate with large size, especially the wafer substrate larger than 12 inches.
[0038] Therefore, a method of epitaxial germanium is developed to prepare the GOI substrate. The method of epitaxial germanium is to form a GOI structure by epitaxially growing Ge on a Si substrate as a Ge providing layer and then bonding the epitaxial germanium layer with the Si / SiO2 substrate. The method needs to perform chemical mechanical polishing (CMP) on two bonding surfaces to reduce the surface roughness of the two bonding surfaces to 0.5 nm or less. However, the chemical mechanical polishing equipment is expensive, and only one sample can be polished at a time, which reduces the work efficiency.
[0039] Figure 1 A bonding flowchart of the GOI structure substrate according to an embodiment of the present application.
[0040] According to an aspect of the overall inventive concept of the present application, as shown in Figure 1 a bonding method of a GOI structure substrate is provided, comprising:
[0041] S1: growing a first dielectric layer and a second dielectric layer on surfaces of a first wafer and a second wafer, respectively;
[0042] S2: performing plasma treatment on surfaces of the first dielectric layer and the second dielectric layer, then immersing in water and blowing dry;
[0043] S3: aligning and bonding the first dielectric layer and the second dielectric layer after the plasma treatment;
[0044] S4: thinning and etching the second wafer to form a GOI structure;
[0045] S5: thinning and polishing the GOI structure to obtain a GOI structure substrate.
[0046] The present application uses plasma bombardment instead of the conventional chemical mechanical polishing (CMP) method to reduce the roughness of the surface of the dielectric layer and achieve high planarization of the bonding interface. The method can process wafers in batches, greatly improving the production efficiency and reducing the production cost.
[0047] According to an embodiment of the present application, the second wafer includes a wafer with an epitaxial germanium epitaxial layer on a silicon layer, and the thickness of the germanium epitaxial layer is 10-1000 nm.
[0048] According to an embodiment of the present application, the thickness of the germanium epitaxial layer can be 10 nm, 100 nm, 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, or 1000 nm.
[0049] According to an embodiment of the present application, the first wafer includes a single-side polished silicon wafer.
[0050] According to an embodiment of the present application, the first dielectric layer and the second dielectric layer can be one of SiO2, Al2O3, Si3N4, HfO2, or a stack of several of SiO2, Al2O3, Si3N4, HfO2.
[0051] According to an embodiment of the present application, the first dielectric layer and the second dielectric layer can be one of SiO2, Al2O3, Si3N4, HfO2, or a stack of several of SiO2, Al2O3, Si3N4, HfO2.
[0052] According to an embodiment of the present application, in S1, the first dielectric layer and the second dielectric layer have a thickness of 10-1000 nm.
[0053] According to an embodiment of the present application, the first dielectric layer and the second dielectric layer can have a thickness of 10 nm, 100 nm, 200 nm, 300 nm, 400 nm, 500 nm, 600 nm, 700 nm, 800 nm, 900 nm, or 1000 nm.
[0054] According to an embodiment of the present application, in S2, the plasma treatment of the surfaces of the first dielectric layer and the second dielectric layer includes:
[0055] S21: placing the first wafer and the second wafer in a plasma atmosphere;
[0056] S22: bombarding the surfaces of the first dielectric layer and the second dielectric layer with plasma, the plasma power being 10-300 W and the gas flow being 10-300 ml / min.
[0057] According to an embodiment of the present application, in S22, the bombarding of the surfaces of the first dielectric layer and the second dielectric layer with the plasma includes:
[0058] bombarding the surfaces of the first dielectric layer and the second dielectric layer with plasma at least once;
[0059] bombarding the surfaces of the first dielectric layer and the second dielectric layer with oxygen plasma;
[0060] or
[0061] bombarding the surfaces of the first dielectric layer and the second dielectric layer with oxygen plasma.
[0062] In the hydrophilic bonding, the treatment of the surfaces of the dielectric layers with oxygen plasma can form oxygen dangling bonds on the surfaces of the dielectric layers, and the subsequent water immersion treatment can form -OH dangling bonds from the oxygen dangling bonds. In the subsequent van der Waals bonding, the -OH dangling bonds on the surfaces of the first dielectric layer and the second dielectric layer react with each other to form -O- (for example, Si-O-Si bonds between SiO2 and SiO2), and the bonding strength is high.
[0063] According to an embodiment of the present application, in S22, the plasma atmosphere is one or more of the plasma of oxygen, nitrogen, argon, etc.
[0064] According to an embodiment of the present application, in S2, each plasma process uses only one kind of gas, and the multiple plasma processes can use different gases.
[0065] According to an embodiment of the present application, in S22, the last plasma used for bombardment on the surfaces of the first dielectric layer and the second dielectric layer is oxygen plasma.
[0066] According to an embodiment of the present application, in S22, after the first wafer and the second wafer are treated by the plasma, they need to be soaked in water and dried.
[0067] According to an embodiment of the present application, in S3, the alignment bonding of the first dielectric layer and the second dielectric layer after plasma treatment includes:
[0068] S31: aligning and approaching the first dielectric layer and the second dielectric layer until the first dielectric layer and the second dielectric layer are bonded together;
[0069] S32: annealing bonding of the first dielectric layer and the second dielectric layer bonded together.
[0070] According to an embodiment of the present application, in S31, the dielectric layer of the first wafer and the dielectric layer of the second wafer are aligned and approached, and they are bonded together by van der Waals force.
[0071] According to an embodiment of the present application, in S32, annealing can enhance the bonding strength between the two wafers, so that they are successfully bonded.
[0072] According to an embodiment of the present application, in S32, the annealing bonding temperature is 150-450℃, and the time is 20-300min.
[0073] According to an embodiment of the present application, in S32, the optimal bonding temperature of the first wafer and the second wafer is less than 400℃.
[0074] According to an embodiment of the present application, in S4, the thinning and etching of the second wafer include:
[0075] The second wafer is etched until the silicon layer is completely etched, the germanium epitaxial layer is reserved, and a germanium-on-insulator structure is formed.
[0076] According to an embodiment of the present application, in S4, the thinning and etching of the second wafer substrate can be dry etching or wet etching.
[0077] According to an embodiment of the present application, in S4, the structure of the Ge-on-insulator is a structure of the first wafer / first dielectric layer / second dielectric layer / Ge epitaxial layer.
[0078] According to an embodiment of the present application, in S5, the polishing depth in the polishing process of the Ge-on-insulator structure is 10-500 nm.
[0079] The technical solutions of the present application are described in detail below through preferred embodiments. It should be noted that the specific embodiments below are only used for illustration and do not limit the present application.
[0080] Embodiment 1: Sample preparation.
[0081] Sample 1:
[0082] A first wafer and a second wafer are provided, wherein the first wafer is a single-side polished silicon wafer, and the second wafer is a wafer of epitaxial Ge on a silicon substrate, and the thickness of the epitaxial Ge is 1 μm.
[0083] A silicon dioxide layer is grown on the polished surface of the first wafer by thermal oxidation as a first dielectric layer, and the thickness is about 500 nm; a silicon dioxide layer is deposited on the surface of the epitaxial Ge of the second wafer by chemical vapor deposition as a second dielectric layer, and the thickness is about 500 nm.
[0084] The first wafer and the second wafer are placed in an oxygen plasma atmosphere, and the surface of the dielectric layer is bombarded by oxygen plasma. Then the surfaces of the two wafers are immersed in water and blown dry. The plasma power is about 200 W, the gas flow is about 200 ml / min, and the time is 3 min.
[0085] The first dielectric layer of the first wafer and the second dielectric layer of the second wafer are aligned and close to each other until they are bonded together by van der Waals force, and then annealing is performed to enhance the bonding strength between the two wafers, so that they are successfully bonded. The annealing temperature is about 400℃, and the annealing time is about 200 min.
[0086] The silicon substrate of the second wafer of the bonded combination of the two wafers is mechanically thinned until the remaining thickness of the silicon substrate of the second wafer is about 50 nm.
[0087] The thinned surface of the thinned wafer combination is etched by a 25% TMAH solution to remove the remaining about 50 nm of silicon of the second wafer substrate until the Ge layer is completely exposed, and a preliminary GOI structure is formed.
[0088] The Ge surface of the GOI structure is chemically mechanically polished to remove about 20 nm of Ge to form a final GOI structure substrate.
[0089] Sample 2:
[0090] A first wafer and a second wafer are provided, wherein the first wafer is a single-side polished silicon wafer, and the second wafer is a wafer with epitaxial germanium on a silicon substrate, and the thickness of the epitaxial germanium is 1 μm.
[0091] Silicon dioxide is grown on the polished surface of the first wafer as a first dielectric layer by thermal oxidation, and the thickness is about 500 nm; and a silicon dioxide layer is deposited on the surface of the epitaxial germanium of the second wafer as a second dielectric layer by chemical vapor deposition, and the thickness is about 500 nm.
[0092] The first wafer and the second wafer are placed in an oxygen plasma atmosphere, and the surfaces of the dielectric layers are bombarded by oxygen plasma, and the process is repeated three times. Then the surfaces of the two wafers are immersed in water and blown dry. The plasma power is about 200 W, the gas flow is about 300 ml / min, and the bombardment time is 1 min each time.
[0093] The first dielectric layer of the first wafer and the second dielectric layer of the second wafer are aligned and close to each other until they are bonded together by van der Waals force, and then annealing is performed to enhance the bonding strength between the two wafers and make them successfully bonded. The annealing temperature is about 400°C, and the annealing time is about 200 min.
[0094] The silicon substrate of the second wafer of the bonded combination of the two wafers is mechanically thinned until the remaining thickness of the silicon substrate of the second wafer is about 50 nm.
[0095] The thinned surface of the thinned wafer combination is etched by a 25% trimethylammonium hydroxide (TMAH) solution to remove about 50 nm of the remaining silicon of the second wafer substrate until the Ge layer is completely exposed, and a preliminary GOI structure is formed.
[0096] The Ge surface of the GOI structure is chemically mechanically polished to remove about 20 nm of Ge to form a final GOI structure substrate.
[0097] Sample 3:
[0098] Changing the type and number of plasma atmospheres in Embodiment 1 can also achieve the same purpose.
[0099] A first wafer and a second wafer are provided, wherein the first wafer is a single-side polished silicon wafer, and the second wafer is a wafer with epitaxial germanium on a silicon substrate, and the thickness of the epitaxial germanium is 1 μm.
[0100] Silicon dioxide is grown on the polished surface of the first wafer as a first dielectric layer by thermal oxidation, and the thickness is about 500 nm; and a silicon dioxide layer is deposited on the surface of the epitaxial germanium of the second wafer as a second dielectric layer by chemical vapor deposition, and the thickness is about 500 nm.
[0101] The first wafer and the second wafer are placed in an argon plasma atmosphere, and the surface of the dielectric layer is bombarded twice by argon plasma, the argon plasma power is about 150 W, the argon flow rate is about 200 ml / min, and each bombardment time is 1 min. Then the plasma chamber is pumped and cleaned, and oxygen is filled, and the surface of the dielectric layer is bombarded once by oxygen plasma, the oxygen plasma power is 200 W, the oxygen flow rate is 200 ml / min, and the time is 2 min. Then the surfaces of the two wafers are immersed in water and dried.
[0102] The first dielectric layer of the first wafer is aligned and close to the second dielectric layer of the second wafer until they are bonded together by van der Waals force, and then annealing is performed to enhance the bonding strength between the two wafers and make them successfully bonded. The annealing temperature is about 400℃, and the annealing time is about 200 min.
[0103] The silicon substrate of the second wafer of the bonded two-wafer combination is mechanically thinned until the remaining thickness of the silicon substrate of the second wafer is about 50 nm.
[0104] The thinned surface of the thinned wafer combination is wet etched by a 25% trimethylammonium hydroxide (TMAH) solution to remove about 50 nm of the remaining silicon of the second wafer substrate until the Ge layer is completely exposed, and a preliminary GOI structure is formed.
[0105] The Ge surface of the GOI structure is chemically mechanically polished to remove about 20 nm of Ge to form the final GOI structure substrate.
[0106] The above specific embodiments further illustrate the purpose, technical solutions and beneficial effects of the present application. It should be understood that the above description is only a specific embodiment of the present application and is not intended to limit the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.
Claims
1. A bonding method of a silicon-on-insulator-germanium structure substrate, comprising: providing a first wafer and a second wafer, the first wafer comprising at least a single-side polished silicon wafer, and the second wafer comprising a wafer of epitaxial germanium on a silicon substrate; growing a first dielectric layer and a second dielectric layer on a polished surface of the first wafer and an epitaxial germanium surface of the second wafer, respectively; performing plasma treatment on surfaces of the first dielectric layer and the second dielectric layer to perform a planarization process on the surfaces of the first dielectric layer and the second dielectric layer, and then immersing and drying with water; wherein the plasma treatment comprises at least one bombardment of the surfaces of the first dielectric layer and the second dielectric layer by plasma, and the last bombardment of the surfaces of the first dielectric layer and the second dielectric layer is performed by oxygen plasma, the plasma power is 10W-300W, and the gas flow is 10-300ml / min; aligning and approaching the first dielectric layer and the second dielectric layer after the plasma treatment until the first dielectric layer and the second dielectric layer are bonded together; and performing annealing bonding on the first dielectric layer and the second dielectric layer bonded together; thinning and etching the second wafer to form a germanium-on-insulator structure; performing thinning and polishing processes on the germanium-on-insulator structure to obtain a silicon-on-insulator-germanium structure substrate. 2.The method of claim 1, wherein a thickness of the epitaxial germanium layer is 10-1000nm. 3.The method of claim 1, wherein the first dielectric layer and the second dielectric layer are one of SiO2, Al2O3, Si3N4, HfO2, or a stack of several of SiO2, Al2O3, Si3N4, HfO2; and a thickness of the first dielectric layer and the second dielectric layer is 10-1000nm. 4.The method of claim 1, wherein a temperature of the annealing bonding is 150-450℃, and a time is 20-300min.
5. The method of claim 1, wherein, the thinning and etching of the second wafer comprises: etching the second wafer until the silicon layer is completely etched, the epitaxial germanium layer is reserved, and the germanium-on-insulator structure is formed.
6. The method of claim 5, wherein, the germanium-on-insulator structure is a structure of the first wafer / first dielectric layer / second dielectric layer / epitaxial germanium layer.
7. The method of claim 1, wherein, in the polishing process of the germanium-on-insulator structure, a polishing depth is 10-500nm.
8. The method of claim 1, wherein, the plasma treatment on the surfaces of the first dielectric layer and the second dielectric layer comprises: placing the first wafer and the second wafer in a plasma atmosphere; and bombarding the surfaces of the first dielectric layer and the second dielectric layer by the plasma.
Citation Information
Patent Citations
Wafer bonding method and method for fabricating corresponding heterojunction substrate
CN109786229A