Super junction carrier storage type IGBT device

Abstract

The application discloses a super-junction carrier storage type IGBT device, which comprises a super-junction structure formed on the top surface of a first N-type epitaxial layer, and the doping concentration of an N-type column is greater than that of the first N-type epitaxial layer. The body region of the device unit structure is formed in the surface region of the N-type column. The N-type column at the bottom of the body region constitutes a carrier storage layer. The first N-type epitaxial layer at the bottom of the carrier storage layer serves as a drift region. The thickness of the super-junction structure is set according to the thickness of the carrier storage layer, and the thickness of the carrier storage layer is set according to the required current capacity when the IGBT device is forward conducting. The thickness of the super-junction structure and the total withstand voltage of the IGBT device are independent. The application can avoid the adverse effect of the super-junction structure on the forward conducting current capacity of the device when the device withstand voltage is improved, thereby maximizing the forward conducting current capacity of the device by using the super-junction structure, and independently adjusting the reverse withstand voltage and the forward current conducting capacity of the device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a super junction (SJ) carrier storage (CS) insulated gate bipolar transistor (IGBT) device. Background Technology

[0002] IGBT is a voltage-controlled MOS and bipolar composite device that combines the main advantages of both bipolar junction power transistors and power MOSFETs: high input impedance, low input drive power, low on-resistance, large current capacity, and fast switching speed. This makes IGBT one of the important switching components for energy control and conversion in power electronic systems, and its performance directly affects the conversion efficiency, size, and weight of the power electronic system.

[0003] The IGBT structure is very similar to the VDMOS structure. It is formed by changing the N+ doped drain region to a P+ doped collector region on the basis of VDMOS. The collector region can inject holes into the drift region, thereby modulating the conductivity of the drift region, which can reduce the on-state voltage drop of the device and increase the current density of the device.

[0004] By incorporating a superjunction structure within the drift region of an IGBT device, a superjunction IGBT (SJ-IGBT) device can be obtained. SJ-IGBTs leverage the process capabilities of both SJ and IGBT technologies, combining the characteristics of both devices to significantly improve forward conduction performance and substantially increase power density.

[0005] like Figure 1 The diagram shown is a structural schematic of the first existing superjunction IGBT device; the first existing superjunction IGBT device includes:

[0006] The superjunction structure is composed of multiple N-type pillars and P-type pillars 209 arranged alternately, and one N-type pillar and one adjacent P-type pillar 209 form a corresponding superjunction unit.

[0007] The superjunction structure is formed in the first N-type epitaxial layer 202. A P-type doped collector region 201 is formed at the bottom of the first N-type epitaxial layer 202. The back side of the collector region 201 is connected to a collector electrode composed of a back metal layer.

[0008] The P-type pillar 209 is composed of a P-type epitaxial layer filled in a superjunction trench, the superjunction trench is formed in the first N-type epitaxial layer 202, and the N-type pillar is composed of the first N-type epitaxial layer 202 between the P-type pillars 209.

[0009] The first N-type epitaxial layer 202 is formed on the surface of a semiconductor substrate (not shown). The semiconductor substrate is removed during a back-side thinning process, therefore... Figure 1 It is not displayed.

[0010] The bottom of the P-shaped column 209 and the top surface of the current collection area 201 are spaced apart.

[0011] A top N-type epitaxial layer 208 is formed on the top of the superjunction structure.

[0012] In the device unit region 201a, a device unit structure of an IGBT device is formed in the top N-type epitaxial layer 208 of the top region of each superjunction unit. The IGBT device is formed by multiple device unit structures connected in parallel.

[0013] The device unit structure includes:

[0014] P-type doped body region 206, which is formed in the surface region of the top N-type epitaxial layer 208.

[0015] The trench gate is composed of a gate dielectric layer 204 and a gate conductive material layer 205 filled in a gate trench 203, wherein the gate trench 203 is located in the top region of the N-type pillar and passes through the body region 206.

[0016] The surface of the body region 206, which is covered by the side of the trench gate, is used to form a channel; the drift region consists of the first N-type epitaxial layer 202 at the bottom and the top N-type epitaxial layer 208 of the body region 206.

[0017] An emission region 207 composed of N+ regions is formed on the surface of the body region 206 on the side of the trench gate.

[0018] A first contact hole 211 is formed on the top of the emission region 207. The bottom of the first contact hole 211 contacts both the emission region 207 and the body region 206. The top of the first contact hole 211 is connected to the emitter composed of the front metal layer 212.

[0019] An N-type doped electric field cessation layer 214 is formed in the first N-type epitaxial layer 202 on the front side of the current collector region 201. The doping concentration of the electric field cessation layer 214 is greater than that of the first N-type epitaxial layer 202. There is a gap between the top surface of the electric field cessation layer 214 and the bottom surface of the P-type pillar 209.

[0020] The trench gate also extends into the gate lead-out region 201b, in which a second contact hole (not shown) is formed on the top of the gate conductive material layer 205, and the top of the second contact hole is connected to the gate composed of the front metal layer 212.

[0021] A passivation layer 213 is also formed on the surface of the front metal layer 212.

[0022] Both the first contact hole 211 and the second contact hole pass through the interlayer membrane 210.

[0023] Typically, the collector region 201 consists of a P-type doped back ion implantation region formed at the bottom of the first N-type epitaxial layer 202 after the back side of the semiconductor substrate is thinned.

[0024] like Figure 2 The diagram shown is a structural schematic of an existing second type of superjunction IGBT device; the existing second type of superjunction IGBT device includes:

[0025] The superjunction structure is composed of multiple N-type pillars and P-type pillars 309 arranged alternately, and one N-type pillar and one adjacent P-type pillar 309 form a corresponding superjunction unit.

[0026] The superjunction structure is formed in the first N-type epitaxial layer 302. A P-type doped collector region 301 is formed at the bottom of the first N-type epitaxial layer 302. The back side of the collector region 301 is connected to a collector electrode composed of a back metal layer.

[0027] The P-type pillar 309 is composed of a P-type epitaxial layer filled in a superjunction trench, the superjunction trench is formed in the first N-type epitaxial layer 302, and the N-type pillar is composed of the first N-type epitaxial layer 302 between the P-type pillars 309.

[0028] The first N-type epitaxial layer 302 is formed on the surface of a semiconductor substrate (not shown). The semiconductor substrate is removed during a back-side thinning process, therefore... Figure 2 It is not displayed.

[0029] The bottom of the P-shaped column 309 and the top surface of the current collection area 301 are spaced apart.

[0030] In the device unit region, a device unit structure of an IGBT device is formed in the top region of each of the superjunction units, and the IGBT device is formed by multiple device unit structures connected in parallel.

[0031] The device unit structure includes:

[0032] A P-type doped body region 306 is formed in the top region of the superjunction unit, that is, in the top region of the N-type pillar and the P-type pillar 309.

[0033] The trench gate comprises a gate dielectric layer 304 and a gate conductive material layer 305 filled in a gate trench 303. The gate trench 303 is located in the top region of the N-type pillar and passes through the body region 306.

[0034] The surface of the body region 306, which is covered by the side of the trench gate, is used to form a channel; the drift region is composed of the first N-type epitaxial layer 302 at the bottom of the body region 306.

[0035] Two gate trenches 303 are formed in the top region of the same N-type pillar.

[0036] An emission region 307 composed of N+ regions is formed on the surface of the body region 306 on the second side of the trench gate.

[0037] A first contact hole 311 is formed on the top of the emission region 307. The bottom of the first contact hole 311 contacts both the emission region 307 and the body region 306. The top of the first contact hole 311 is connected to the emitter composed of the front metal layer 312.

[0038] The body region 306 at the bottom of the first contact hole 311 is further formed with a body lead-out region 308 composed of a P+ region.

[0039] Depend on Figure 2 As shown, the P-shaped post 309 is located outside the first side of the trench gate. Since the first side and the second side of the trench gate are electrically isolated, the conductive path of the body region between the P-shaped post 309 and the second side of the trench gate, the emitter region 307, the first contact hole 311 and the emitter is disconnected by the trench gate.

[0040] An N-type doped electric field cessation layer 314 is formed in the first N-type epitaxial layer 302 on the front side of the current collector region 301. The doping concentration of the electric field cessation layer 314 is greater than the doping concentration of the first N-type epitaxial layer 302. There is a gap between the top surface of the electric field cessation layer 314 and the bottom surface of the P-type pillar 309.

[0041] A passivation layer 313 is also formed on the surface of the front metal layer 312.

[0042] Both the first contact hole 311 and the second contact hole pass through the interlayer membrane 310.

[0043] Typically, the collector region 301 consists of a P-type doped back ion implantation region formed at the bottom of the first N-type epitaxial layer 302 after the back side of the semiconductor substrate is thinned.

[0044] Existing superjunction IGBT devices can improve the breakdown voltage of the drift region by introducing a superjunction structure, thereby increasing the N-type doping concentration in the drift region. However, in reality, increasing the N-type doping concentration in the drift region does not improve the forward conduction current capability of the device, thus limiting the improvement of the device's forward performance. Summary of the Invention

[0045] The technical problem to be solved by the present invention is to provide a superjunction carrier storage IGBT device that can avoid the adverse effects of using a superjunction structure to improve the device's withstand voltage on the device's forward conduction current capability. Thus, the device's forward conduction current capability can be maximized by utilizing the superjunction structure, and the reverse withstand voltage and forward current conduction capability of the device can be independently adjusted.

[0046] To solve the above-mentioned technical problems, the superjunction carrier storage type IGBT device provided by the present invention includes:

[0047] A superjunction structure is formed on the top surface of the first N-type epitaxial layer. The superjunction structure is composed of multiple N-type pillars and P-type pillars arranged alternately. One N-type pillar and one adjacent P-type pillar form a corresponding superjunction unit.

[0048] The doping concentration of the N-type pillar is greater than that of the first N-type epitaxial layer.

[0049] A P-type doped collector region is formed at the bottom of the first N-type epitaxial layer, and the back side of the collector region is connected to a collector electrode composed of a back metal layer.

[0050] In the device unit region, a device unit structure of an IGBT device is formed in the top region of each of the superjunction units, and the IGBT device is formed by multiple device unit structures connected in parallel.

[0051] The device unit structure includes: a P-type doped body region, a gate structure, and an N+ doped emitter region.

[0052] The body region is formed in the surface region of the N-shaped column.

[0053] The surface of the body region covered by the gate structure serves as the channel region.

[0054] The emission region is formed on the surface of the body region.

[0055] The N-type pillars at the bottom of the body region form a carrier storage layer.

[0056] The first N-type epitaxial layer at the bottom of the carrier storage layer serves as a drift region.

[0057] The thickness of the superjunction structure is set according to the thickness of the carrier storage layer, and the thickness of the carrier storage layer is set according to the current capability required for the IGBT device to conduct in the forward direction.

[0058] When the IGBT device is reversed, the superjunction structure is used to deplete the carrier storage layer to increase the first breakdown voltage of the carrier storage layer. The total breakdown voltage of the IGBT device is the sum of the first breakdown voltage of the carrier storage layer and the second breakdown voltage of the drift region, making the thickness of the superjunction structure independent of the total breakdown voltage of the IGBT device.

[0059] A further improvement is that the carrier storage layer has an optimal thickness, which is the thickness corresponding to the strongest current capability when the IGBT device is forward-biased. The optimal thickness is located between the lower limit and the upper limit of the thickness range of the carrier storage layer.

[0060] A further improvement is that the optimal thickness is the thickness of the carrier storage layer corresponding to the strongest current capability when the IGBT device is forward-biased, as determined by experiments or simulations.

[0061] A further improvement is that the optimal thickness includes 10 micrometers.

[0062] A further improvement is that the thickness of the carrier storage layer ranges from 5 micrometers to 40 micrometers.

[0063] A further improvement is that the gate structure adopts a trench gate, which consists of a gate dielectric layer and a gate conductive material layer filled in the gate trench. The gate trench is located in the top region of the N-type pillar, and the gate trench passes through the body region and the bottom surface of the gate trench is located in the carrier storage layer.

[0064] A further improvement is that the top of the emission region is connected to the emitter, which is composed of a front metal layer, through a first contact hole.

[0065] The bottom of the first contact hole also contacts the body region.

[0066] An electrical isolation structure is provided between the P-type post and the body region, which disconnects the conduction path from the P-type post to the emitter through the body region.

[0067] A further improvement is that the electrical isolation structure is implemented using the trench gate.

[0068] Two trench gates are formed in the top region of the N-type post, and the emitter region is self-aligned and formed on the body region surface between the second sides of the two trench gates; the P-type post and the body region between the P-type post and the first side of the trench gate are electrically isolated by the trench gate and the body region between the second sides of the two trench gates.

[0069] A further improvement is that an N-type doped electric field cessation layer is formed in the first N-type epitaxial layer on the front side of the collector region, and the doping concentration of the electric field cessation layer is greater than the doping concentration of the first N-type epitaxial layer.

[0070] A further improvement is that the gate dielectric layer includes a gate oxide layer; and the gate conductive material layer includes a polysilicon gate.

[0071] A further improvement is that a body lead-out area composed of P+ regions is also formed on the surface of the body region at the bottom of the first contact hole.

[0072] A further improvement is that an N-type electrode region for a fast recovery diode is formed at the bottom of the first N-type epitaxial layer; the back side of the N-type electrode region is also in contact with the collector, and the collector also serves as the cathode of the fast recovery diode.

[0073] A further improvement is that the trench gate extends into the gate lead-out region, in which a second contact hole is formed on top of the gate conductive material layer, and the top of the second contact hole is connected to the gate composed of the front metal layer.

[0074] A further improvement is that the P-type pillar is composed of a P-type epitaxial layer filled in a superjunction trench, the superjunction trench is formed in a second N-type epitaxial layer, the N-type pillar is composed of the second N-type epitaxial layer between the P-type pillars, and the second N-type epitaxial layer is formed on the top surface of the first N-type epitaxial layer.

[0075] A further improvement is that the first N-type epitaxial layer is formed on the surface of a semiconductor substrate; or, the first N-type epitaxial layer is replaced with a zone melting (FZ) semiconductor substrate or a magnetically pulled (MCZ) semiconductor substrate.

[0076] Unlike existing structures that use superjunctions to improve the reverse breakdown voltage of IGBT devices and thus increase the doping concentration in the drift region to enhance forward current conduction, this invention addresses the drawback of using superjunctions to increase the N-type doping concentration in the drift region. This causes the entire drift region to simultaneously act as a carrier storage layer, resulting in a decrease in hole carrier concentration and limiting further improvement in forward current conduction. Instead, this invention dedicates the superjunction structure specifically to the carrier storage layer, ensuring its thickness is sufficient for forward conduction. The higher hole carrier concentration in the drift region enhances the device's forward current conduction capability. The device's total reverse breakdown voltage can be adjusted by setting the thickness and doping concentration of the drift region, based on the first breakdown voltage of the superjunction structure. Ultimately, the second breakdown voltage of the drift region, the first breakdown voltage of the superjunction structure, and the total reverse breakdown voltage of the device all meet the device's inversion breakdown voltage requirements. Therefore, this invention simultaneously improves the device's breakdown voltage capability and forward current conduction capability, and it is easy to obtain the optimal forward current conduction capability. Furthermore, since the N-type doping concentration in the drift region is very low, the second breakdown voltage is easily met. Attached Figure Description

[0077] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0078] Figure 1 This is a schematic diagram of the structure of the first existing superjunction IGBT device;

[0079] Figure 2 This is a schematic diagram of the structure of the second type of superjunction IGBT device.

[0080] Figure 3 This is a schematic diagram of the structure of an existing carrier storage type IGBT device;

[0081] Figure 4 This is a schematic diagram of the structure of a superjunction carrier storage IGBT device according to an embodiment of the present invention;

[0082] Figure 5 It is a simulation graph of the transfer characteristic curves corresponding to carrier storage layers of different thicknesses in existing carrier storage type IGBT devices;

[0083] Figure 6 This is a simulation diagram of the transfer characteristic curves corresponding to carrier storage layers of different thicknesses in the superjunction carrier storage type IGBT device according to an embodiment of the present invention;

[0084] Figure 7 This is a simulation diagram of the transfer characteristic curves corresponding to the optimal thickness of the carrier storage layer for existing carrier storage IGBT devices and the superjunction carrier storage IGBT device of the present invention.

[0085] Figure 8 These are electric field intensity distribution curves corresponding to two different thicknesses of carrier storage layers in the superjunction carrier storage type IGBT device according to an embodiment of the present invention.

[0086] Figure 9 These are the reverse breakdown curves corresponding to two different thicknesses of carrier storage layers in the superjunction carrier storage type IGBT device of this invention. Detailed Implementation

[0087] The superjunction carrier storage IGBT device of this invention is derived from an analysis of the problems existing in existing superjunction IGBT devices. Therefore, before describing the superjunction carrier storage IGBT device of this invention in detail, the applicant will first introduce the applicant's analysis of the problems existing in existing superjunction IGBT devices.

[0088] Existing conventional SJ-IGBTs lack a thorough understanding of their operational mechanism. All withstand voltage is achieved using an SJ structure or a semi-superjunction structure. Both full and semi-superjunction structures rely heavily on the concentration of the N-type epitaxial layer (NEPI) as the drift region. However, in-depth analysis reveals that the enhanced current density of SJ-IGBTs is not due to increased drift region concentration, but rather to the carrier storage effect generated by the denser N-type epitaxial layer (SJ-NEPI) region with a superjunction structure.

[0089] The applicant argues that during the forward conduction process of an IGBT, the drift region actually contains not only the majority carriers (electrons) provided by the N-type doped drift region itself, but also the minority carriers (holes) injected from the collector region. In existing superjunction IGBT devices, the doping concentration of the drift region increases after introducing a superjunction structure. This is equivalent to the drift region effectively acting as a carrier storage layer within the depth range of the entire superjunction structure. However, when the drift region acts as a carrier storage layer, a thicker drift region does not necessarily increase the number of hole carriers. Although the hole carrier concentration is related to the thickness of the carrier storage layer, a thicker layer does not necessarily mean a higher number of hole carriers. When the number of hole carriers cannot increase or even decreases, the device's forward conduction current capability decreases. The device's forward conduction current capability is expressed by the current density during forward conduction.

[0090] like Figure 3 The diagram shown is a structural schematic of an existing carrier-storage IGBT device; existing carrier-storage IGBT devices include:

[0091] A first N-type epitaxial layer 402 is formed on the surface of a semiconductor substrate (not shown). A P-type doped collector region 401 is formed at the bottom of the first N-type epitaxial layer 402, and the back side of the collector region 401 is connected to a collector electrode composed of a back metal layer. Typically, the collector region 401 consists of a P-type doped back ion implantation region formed at the bottom of the first N-type epitaxial layer 402 after thinning the back side of the semiconductor substrate. The semiconductor substrate is removed during the back side thinning process, therefore... Figure 4 It is not displayed.

[0092] In the device cell region 401a, the device cell structure of the IGBT device is formed on the surface of the first N-type epitaxial layer 402, and the IGBT device is formed by multiple device cell structures connected in parallel.

[0093] The device unit structure includes:

[0094] A P-type doped body region 406 is formed in the surface region of the first N-type epitaxial layer 402.

[0095] An N-type doped carrier storage layer 409 is also formed in the first N-type epitaxial layer 402 at the bottom of the body region 406, and the doping concentration of the carrier storage layer 409 is greater than the doping concentration of the first N-type epitaxial layer 402.

[0096] The first N-type epitaxial layer 402 at the bottom of the carrier storage layer 409 forms a drift region.

[0097] The trench gate is composed of a gate dielectric layer 404 and a gate conductive material layer 405 filled in a gate trench 403, the gate trench 403 being located in the top region of the N-type pillar and passing through the body region 406.

[0098] The surface of the body region 406, which is covered by the side of the trench gate, is used to form a channel.

[0099] An emission region 407 composed of N+ regions is formed on the surface of the body region 406 on the side of the trench gate.

[0100] A first contact hole 411 is formed at the top of the emission region 407, passing through the interlayer film 410. The bottom of the first contact hole 411 contacts both the emission region 407 and the body region 406. The top of the first contact hole 411 is connected to the emitter composed of the front metal layer 412.

[0101] The body region 406 at the bottom of the first contact hole 411 is further formed with a body lead-out region 408 composed of a P+ region.

[0102] An N-type doped electric field cessation layer 414 is formed in the first N-type epitaxial layer 402 on the front side of the current collector region 401. The doping concentration of the electric field cessation layer 414 is greater than the doping concentration of the first N-type epitaxial layer 402. There is a gap between the top surface of the electric field cessation layer 414 and the bottom surface of the P-type pillar 409.

[0103] A passivation layer 413 is also formed on the surface of the front metal layer 412.

[0104] Both the first contact hole 411 and the second contact hole pass through the interlayer membrane 410.

[0105] Figure 3 In this process, the doping concentration of the carrier storage layer 409 is greater than that of the first N-type epitaxial layer 402. Therefore, setting the carrier storage layer 409 can increase the hole carrier concentration in the entire drift region, and ultimately improve the forward conductivity of the device.

[0106] The applicant, through analysis, believes that when a superjunction structure is incorporated into an IGBT, it not only increases the device's breakdown voltage under reverse bias, but also increases the doping concentration of the N-type pillars. This not only adjusts the N-type carriers but, more importantly, allows the N-type pillars to simultaneously function as a carrier storage layer, thereby enabling the adjustment of hole carriers as well. Regarding the function of the N-type pillars as a carrier storage layer, existing technologies do not recognize this function, nor do they utilize it to determine the thickness of the superjunction structure, thus failing to address the insufficient improvement in forward conduction current capability in existing superjunction IGBTs. In contrast, the embodiments of this invention are based on the analysis of the N-type pillars' simultaneous function as a carrier storage layer in the superjunction structure.

[0107] This invention, through in-depth analysis of the device principle of SJ-IGBT, proposes that the essence of SJ-IGBT is an IGBT with an ultra-thick CS layer (in the forward direction). In the reverse direction, the SJ principle is utilized to deplete the ultra-thick CS layer, avoiding its impact on the withstand voltage.

[0108] Existing traditional SJ-IGBT devices use SJ or Semi-SJ transistors to handle the entire breakdown voltage, failing to grasp the essence of SJ-IGBT. Significant effort is invested, yet there is little improvement in the device's positive performance, and it may even lead to performance degradation.

[0109] After explaining the essence of SJ-IGBT in this embodiment of the invention, it is proposed that the CS layer is not necessarily better the thicker it is. Its thickness is not controlled by the breakdown voltage. The CS layer thickness that is most suitable for improving device performance can be made according to the actual situation. The SJ structure is used to ensure the breakdown voltage of the heavily doped part of CS, while the breakdown voltage of other parts can be left to the IGBT device, such as using a lighter EPI or FZ / MCZ substrate (Sub).

[0110] like Figure 4 The diagram shown is a structural schematic of a superjunction carrier memory IGBT device according to an embodiment of the present invention; the superjunction carrier memory IGBT device according to an embodiment of the present invention includes:

[0111] A superjunction structure is formed on the top surface of the first N-type epitaxial layer 102. The superjunction structure is composed of multiple N-type pillars and P-type pillars 115 arranged alternately. One N-type pillar and one adjacent P-type pillar 115 form a corresponding superjunction unit.

[0112] In this embodiment of the invention, the P-type pillar 115 is composed of a P-type epitaxial layer filled in a superjunction trench, the superjunction trench is formed in a second N-type epitaxial layer 109, the N-type pillar is composed of the second N-type epitaxial layer 109 between the P-type pillars 115, and the second N-type epitaxial layer 109 is formed on the top surface of the first N-type epitaxial layer 102.

[0113] The doping concentration of the N-type pillar is greater than the doping concentration of the first N-type epitaxial layer 102.

[0114] A P-type doped collector region 101 is formed at the bottom of the first N-type epitaxial layer 102, and the back side of the collector region 101 is connected to a collector electrode composed of a back metal layer (not shown).

[0115] In the device cell region, Figure 4 Only the device unit area is shown. The device unit structure in which IGBT devices are formed in the top region of each of the superjunction units is a device unit structure formed by multiple device unit structures connected in parallel.

[0116] The device unit structure includes: a P-type doped body region 106, a gate structure, and an N+ doped emitter region 107.

[0117] The body region 106 is formed in the surface region of the N-shaped column.

[0118] In this embodiment of the invention, the gate structure employs a trench gate, which comprises a gate dielectric layer 104 and a gate conductive material layer 105 filled in a gate trench 103. The gate trench 103 is located in the top region of the N-type pillar, passes through the body region 106, and its bottom surface is located in the carrier storage layer. In some preferred embodiments, the gate dielectric layer 104 includes a gate oxide layer; the gate conductive material layer 105 includes a polysilicon gate.

[0119] The surface of the body region 106 covered by the gate structure serves as the channel region.

[0120] The emission region 107 is formed on the surface of the body region 106.

[0121] In this embodiment of the invention, the top of the emitter region 107 is connected to the emitter composed of the front metal layer 112 through a first contact hole 111 passing through the interlayer film 110. A passivation layer 113 is also covered on the surface of the front metal layer 112.

[0122] The bottom of the first contact hole 111 also contacts the body region 106. In some embodiments, a body lead-out region 108 composed of a P+ region is further formed on the surface of the body region 106 at the bottom of the first contact hole 111.

[0123] The N-type pillars at the bottom of the body region 106 form a carrier storage layer.

[0124] The first N-type epitaxial layer 102 at the bottom of the carrier storage layer serves as a drift region.

[0125] In this embodiment of the invention, an electrical isolation structure is provided between the P-type post 115 and the body region 106, the electrical isolation structure disconnecting the conduction path from the P-type post 115 to the emitter through the body region 106. The electrical isolation structure is implemented using the trench gate.

[0126] Two trench gates are formed in the top region of the N-type post, and the emitter region 107 is self-aligned and formed on the surface of the body region 106 between the second sides of the two trench gates; the P-type post 115 and the body region 106 between the P-type post 115 and the first side of the trench gate are electrically isolated by the trench gate and the body region 106 between the second sides of the two trench gates.

[0127] In other embodiments, the electrical isolation structure can also be modified, as long as the conduction path from the P-shaped pillar 115 to the body region 106 and the emitter is disconnected.

[0128] The thickness of the superjunction structure is set according to the thickness of the carrier storage layer, and the thickness of the carrier storage layer is set according to the current capability required for the IGBT device to conduct in the forward direction.

[0129] When the IGBT device is reversed, the superjunction structure is used to deplete the carrier storage layer to increase the first breakdown voltage of the carrier storage layer. The total breakdown voltage of the IGBT device is the sum of the first breakdown voltage of the carrier storage layer and the second breakdown voltage of the drift region, making the thickness of the superjunction structure independent of the total breakdown voltage of the IGBT device.

[0130] In this embodiment of the invention, the carrier storage layer has an optimal thickness, and the optimal thickness is the thickness corresponding to the strongest current capability when the IGBT device is forward-biased. The optimal thickness is located between the lower limit and the upper limit of the thickness range of the carrier storage layer.

[0131] In some embodiments, the optimal thickness is the thickness of the carrier storage layer corresponding to the strongest current capability when the IGBT device is forward-biased, as determined by experiment or simulation.

[0132] In some preferred embodiments, the optimal thickness includes 10 micrometers. The thickness of the carrier storage layer ranges from 5 micrometers to 40 micrometers.

[0133] In this embodiment of the invention, the first N-type epitaxial layer 102 is formed on the surface of a semiconductor substrate. The semiconductor substrate is thinned by a back-side thinning process. After thinning, the semiconductor substrate is completely removed or partially retained, and the collector region 101 is formed on the back side. Figure 4 The semiconductor substrate is not shown in the image.

[0134] In other embodiments, the first N-type epitaxial layer 102 can also be replaced with a zone melting (FZ) semiconductor substrate or a magnetically pulled (MCZ) semiconductor substrate.

[0135] The doping concentrations of the first N-type epitaxial layer 102, the FZ semiconductor substrate (such as an FZ semiconductor silicon substrate), and the MCZ semiconductor substrate (such as an MCZ silicon substrate) can all be very light, thus making it easy to achieve a high second breakdown voltage in the drift region.

[0136] In this embodiment of the invention, the trench gate further extends into the gate lead-out region, in which a second contact hole is formed on the top of the gate conductive material layer 105, and the top of the second contact hole is connected to the gate composed of the front metal layer 112.

[0137] In this embodiment of the invention, an N-type doped electric field cessation layer 114 is formed in the first N-type epitaxial layer 102 on the front side of the collector region 101, and the doping concentration of the electric field cessation layer 114 is greater than the doping concentration of the first N-type epitaxial layer 102. In other embodiments, the front side of the collector region 101 may contact the back side of the first N-type epitaxial layer 102, that is, the electric field cessation layer 114 may not be formed.

[0138] In other embodiments, it may also include: an N-type electrode region of a fast recovery diode is formed at the bottom of the first N-type epitaxial layer 102; the back side of the N-type electrode region is also in contact with the collector, and the collector also serves as the cathode of the fast recovery diode.

[0139] Unlike existing structures that use superjunctions to improve the reverse breakdown voltage of IGBT devices and thus increase the doping concentration in the drift region to enhance forward current conduction, this invention addresses the drawback of using superjunctions to increase the N-type doping concentration in the drift region. This causes the entire drift region to simultaneously function as a carrier storage layer, resulting in a decrease in hole carrier concentration and limiting further improvement in forward current conduction. In this embodiment, the superjunction structure is specifically used to create the carrier storage layer, ensuring that its thickness is sufficient for forward conduction. The higher hole carrier concentration in the drift region enhances the forward current conduction capability of the device. The reverse total breakdown voltage can be adjusted by setting the thickness and doping concentration of the drift region, based on the first breakdown voltage of the superjunction structure. Ultimately, the second breakdown voltage of the drift region and the first breakdown voltage of the superjunction structure together meet the reverse total breakdown voltage requirement of the device. Therefore, this embodiment of the invention can simultaneously improve the breakdown voltage capability and the forward current conduction capability of the device, and it is easy to obtain the optimal forward current conduction capability. Furthermore, since the N-type doping concentration in the drift region is very low, the second breakdown voltage is easily met.

[0140] like Figure 5 The figure shown is a simulation diagram of the transfer characteristic curves corresponding to different thicknesses of the carrier storage layer of the existing carrier storage type IGBT device. The horizontal axis is the voltage Vge between the gate and the emitter, and the vertical axis represents the current density Ice between the collector and the emitter, which is the forward conduction current referred to in this application. Figure 5 Please refer to the existing carrier storage type IGBT devices corresponding to this. Figure 3As shown, no superjunction structure is set in the IGBT device. It can be seen that the thickness of the carrier storage layer corresponding to curve 500 is 0 micrometers, meaning no carrier storage layer is set. The thickness of the carrier storage layer corresponding to curve 501 is 5 micrometers, the thickness of the carrier storage layer corresponding to curve 502 is 10 micrometers, the thickness of the carrier storage layer corresponding to curve 503 is 20 micrometers, and the thickness of the carrier storage layer corresponding to curve 504 is 40 micrometers. It can be seen that curve 502 has the largest forward conduction current, but the thickness of the carrier storage layer in curve 502 is only 10 micrometers. This shows that a thicker carrier storage layer does not necessarily mean a larger forward conduction current. The epitaxial layer corresponding to the carrier storage layer is also called CS-NEPI. It is evident that a thicker CS-NEPI layer is not always better; among 0-5-10-20-40µm, 10µm has the optimal current capability.

[0141] like Figure 6 The figure shows simulation graphs of the transfer characteristic curves corresponding to different thicknesses of the carrier storage layer in the superjunction carrier storage IGBT device according to an embodiment of the present invention. It can be seen that curve 601 corresponds to a carrier storage layer thickness of 5 micrometers, curve 602 corresponds to a carrier storage layer thickness of 10 micrometers, curve 603 corresponds to a carrier storage layer thickness of 20 micrometers, and curve 604 corresponds to a carrier storage layer thickness of 40 micrometers. It can be seen that curve 602 has the largest forward conduction current, and the carrier storage layer thickness of curve 602 is 10 micrometers. Figure 5 The thickness of the carrier storage layer corresponds to curve 502. Therefore, in this embodiment of the invention, 10 micrometers is the optimal thickness of the carrier storage layer. The carrier storage layer with the superjunction structure is called the Super CS layer. Similarly, the current capability of the Super CS layer is not necessarily better the thicker it is; too thin or too thick is not the optimal choice. Among Super CS layers with a pillar structure, a 10-micrometer Super CS layer structure is also the optimal one, exhibiting the strongest current density.

[0142] like Figure 7 The figure shown is a simulation diagram of the transfer characteristic curves corresponding to the optimal thickness of the carrier storage layer for existing carrier storage IGBT devices and the superjunction carrier storage IGBT device of the present invention. Figure 7 China merged Figure 5 Curve 502 and Figure 6 As shown in curve 602, curves 502 and 602 are basically the same. Therefore, whether or not a superjunction structure is set in the carrier storage layer has little effect on the forward conduction current of the device. That is, the superjunction structure has no significant effect on the forward conduction of the device. Moreover, the presence of P-type pillars will quickly extract holes, so it must be handled carefully to avoid losing forward conduction performance.

[0143] like Figure 8 The figure shows the electric field intensity distribution curves corresponding to two different thicknesses of the carrier storage layer in the superjunction carrier storage type IGBT device according to an embodiment of the present invention. The X-axis of the horizontal axis represents the depth coordinate of the drift region, with the area near -60 micrometers corresponding to the top surface of the N-type pillar of the carrier storage type, and the area near 0 micrometers corresponding to the bottom surface of the drift region. The thickness of the carrier storage layer corresponding to curve 701 is 20 micrometers, and the thickness of the carrier storage layer corresponding to curve 702 is 40 micrometers. It can be seen that the electric field intensity curve of curve 702 is flatter and has better withstand voltage.

[0144] Therefore, in this embodiment of the invention, although the superjunction structure does not have a significant beneficial effect in the forward direction, it is indeed indispensable in the reverse direction. This is because the denser and thicker super CS layer must be exhausted by the SJ pillar to maintain a high breakdown voltage in the reverse direction. Taking 40-micron and 20-micron P-type pillars as examples, it can be seen that the electric field in the drift region corresponding to 40-micron is flatter and has a higher breakdown voltage. However, since the substrate (Sub) of the IGBT portion is very sparse, it is easy to increase the voltage. Therefore, it is not worthwhile to use the superjunction structure to increase the voltage without helping in the forward direction.

[0145] like Figure 9 The figures shown are reverse breakdown curves corresponding to two different thicknesses of the carrier storage layer in the superjunction carrier storage IGBT device according to an embodiment of the present invention. Curve 801 corresponds to a carrier storage layer thickness of 20 micrometers, and curve 802 corresponds to a carrier storage layer thickness of 40 micrometers. It can be seen that the breakdown voltage of curve 802 is slightly higher. Figure 8 The corresponding electric field intensity distribution curve is consistent.

[0146] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A superjunction carrier storage type IGBT device, characterized in that, include: A superjunction structure is formed on the top surface of the first N-type epitaxial layer. The superjunction structure is composed of multiple N-type pillars and P-type pillars arranged alternately. One N-type pillar and one adjacent P-type pillar form a corresponding superjunction unit. The doping concentration of the N-type pillar is greater than the doping concentration of the first N-type epitaxial layer; A P-type doped collector region is formed at the bottom of the first N-type epitaxial layer, and the back side of the collector region is connected to a collector electrode composed of a back metal layer. In the device unit region, a device unit structure of an IGBT device is formed in the top region of each superjunction unit, and the IGBT device is formed by multiple device unit structures connected in parallel; The device unit structure includes: a P-type doped body region, a gate structure, and an N+ doped emitter region. The body region is formed in the surface region of the N-shaped column; The surface of the body region covered by the gate structure serves as the channel region; The emission region is formed on the surface of the body region; The N-type pillars at the bottom of the body region form a carrier storage layer; The first N-type epitaxial layer at the bottom of the carrier storage layer serves as a drift region; The thickness of the superjunction structure is set according to the thickness of the carrier storage layer, and the thickness of the carrier storage layer is set according to the current capability required when the IGBT device is forward-biased. When the IGBT device is reversed, the superjunction structure is used to deplete the carrier storage layer to increase the first breakdown voltage of the carrier storage layer. The total breakdown voltage of the IGBT device is the sum of the first breakdown voltage of the carrier storage layer and the second breakdown voltage of the drift region, making the thickness of the superjunction structure independent of the total breakdown voltage of the IGBT device.

2. The superjunction carrier storage IGBT device as described in claim 1, characterized in that: The carrier storage layer has an optimal thickness, which is the thickness corresponding to the strongest current capability when the IGBT device is forward-biased. The optimal thickness is located between the lower limit and the upper limit of the thickness range of the carrier storage layer.

3. The superjunction carrier storage IGBT device as described in claim 2, characterized in that: The optimal thickness is the thickness of the carrier storage layer corresponding to the strongest current capability when the IGBT device is forward-biased, as determined by experiments or simulations.

4. The superjunction carrier storage IGBT device as described in claim 3, characterized in that: The optimal thickness includes 10 micrometers.

5. The superjunction carrier storage IGBT device as described in claim 4, characterized in that: The thickness of the carrier storage layer ranges from 5 micrometers to 40 micrometers.

6. The superjunction carrier storage IGBT device as described in claim 1, characterized in that: The gate structure employs a trench gate, which consists of a gate dielectric layer and a gate conductive material layer filled in the gate trench. The gate trench is located in the top region of the N-type pillar, passes through the body region, and the bottom surface of the gate trench is located in the carrier storage layer.

7. The superjunction carrier storage IGBT device as described in claim 6, characterized in that: The top of the emission region is connected to the emitter, which is composed of a front metal layer, through a first contact hole; The bottom of the first contact hole also contacts the body region; An electrical isolation structure is provided between the P-type post and the body region, which disconnects the conduction path from the P-type post to the emitter through the body region.

8. The superjunction carrier storage IGBT device as described in claim 7, characterized in that: The electrical isolation structure is implemented using the trench gate; Two trench gates are formed in the top region of the N-type post, and the emitter region is self-aligned and formed on the body region surface between the second sides of the two trench gates; the P-type post and the body region between the P-type post and the first side of the trench gate are electrically isolated by the trench gate and the body region between the second sides of the two trench gates.

9. The superjunction carrier storage IGBT device as described in claim 1, characterized in that: An N-type doped electric field cessation layer is formed in the first N-type epitaxial layer on the front side of the collector region, and the doping concentration of the electric field cessation layer is greater than that of the first N-type epitaxial layer.

10. The superjunction carrier storage IGBT device as described in claim 6, characterized in that: The gate dielectric layer includes a gate oxide layer; the gate conductive material layer includes a polysilicon gate.

11. The superjunction carrier storage IGBT device as described in claim 7, characterized in that: The body region surface at the bottom of the first contact hole is further formed with a body lead-out region composed of P+ regions.

12. The superjunction carrier storage IGBT device as described in claim 1 or 9, characterized in that: An N-type electrode region for a fast recovery diode is also formed at the bottom of the first N-type epitaxial layer; the back side of the N-type electrode region is also in contact with the collector, and the collector also serves as the cathode of the fast recovery diode.

13. The superjunction carrier storage IGBT device as described in claim 6, characterized in that: The trench gate also extends into the gate lead-out region, in which a second contact hole is formed on top of the gate conductive material layer, and the top of the second contact hole is connected to the gate composed of the front metal layer.

14. The superjunction carrier storage IGBT device as described in claim 1, characterized in that: The P-type pillar is composed of a P-type epitaxial layer filled in a superjunction trench, the superjunction trench being formed in a second N-type epitaxial layer, and the N-type pillar is composed of the second N-type epitaxial layer between the P-type pillars, the second N-type epitaxial layer being formed on the top surface of the first N-type epitaxial layer.

15. The superjunction carrier storage IGBT device as described in claim 1, characterized in that: The first N-type epitaxial layer is formed on the surface of a semiconductor substrate; or, the first N-type epitaxial layer is replaced by a zone-melted semiconductor substrate or a magnetically pulled Czochralski semiconductor substrate.

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