A high short-circuit capability carrier storage trench gate IGBT device

Abstract

The application discloses a high short-circuit resistance current carrier storage trench gate IGBT device, which is configured to comprise a plurality of interval trenches (1), and a P+ area (2) for improving short-circuit resistance of the IGBT is formed between adjacent trenches (1). The IGBT device provided by the application forms the P+ area periodically between the trenches, so that the trench sidewall of the P+ area cannot form a conductive channel, thereby reducing the overall channel density, reducing the saturation current of the device, and greatly improving the short-circuit resistance of the device.

Description

TECHNICAL FIELD

[0001] The present application relates to a carrier storage trench gate IGBT device with high short circuit resistance. BACKGROUND

[0002] IGBT (Insulated Gate Bipolar Transistor) is a kind of core power electronic device widely used in rail transit, industrial control, new energy vehicles and household appliances. The mainstream technology of IGBT at present is based on trench gate structure, combined with carrier storage technology, that is, carrier storage trench gate IGBT, the basic structure of which is shown in Figure 1 The structure increases a layer of N-type CS (Carrier Stored) layer between P body region and N drift region, which plays a role in blocking holes, thereby increasing the carrier concentration below the P body region and enhancing the conductance modulation effect, greatly reducing the on-state voltage drop of the device. However, in the prior art, in order to pursue lower saturation voltage drop and switching loss, the trench density of the carrier storage trench gate IGBT is made larger and larger, resulting in an increase in the corresponding channel density, which increases the saturation current density of the device, thereby reducing the short circuit resistance of the device. SUMMARY

[0003] To solve the above technical problems, the purpose of the present application is to provide a carrier storage trench gate IGBT device with high short circuit resistance, which has high short circuit resistance.

[0004] The IGBT device is configured to include a plurality of spaced trenches, and a P+ region for improving the short circuit resistance of the IGBT is periodically spaced between adjacent trenches.

[0005] The IGBT device provided by the present application forms a P+ region periodically between the trenches, so that the trench sidewall of the P+ region cannot form a conductive channel, thereby reducing the overall channel density, reducing the saturation current of the device, and greatly improving the short circuit resistance of the device.

[0006] In some embodiments, the sum of the coverage areas of all P+ regions 2 accounts for 1 / 10 to 4 / 5 of the sum of the areas between all trenches.

[0007] In some embodiments, the width of the P+ region is 1 to 100 um.

[0008] In some embodiments, the P+ region is configured as a plurality of spaced regions with a spacing of 1 to 100 um.

[0009] In some embodiments, a plurality of N+ regions are formed between adjacent trenches, and a P- region is formed at the bottom of the N+ region.

[0010] In some embodiments, the N+ region and the P- region are formed in the interval of the adjacent P+ region, the configuration of the P+ region eliminates part of the N+ region and the P region, reduces the channel, and improves the short-circuit resistance of the device.

[0011] In some embodiments, the bottom of the P region forms an N-type CS region for blocking holes.

[0012] In some embodiments, the P+ region is injected with a P-type impurity injection dose that is 1-2 orders of magnitude higher than the P-type impurity injection dose of the P- region; the P+ region has a high doping concentration and a low resistivity, and when the device is turned on, most of the hole current will pass through the P+ region, rather than directly below the N+ region, thereby reducing the risk of turning on the parasitic transistor and improving the anti-latch-up capability of the device.

[0013] In some embodiments, the junction depth H of the P+ region satisfies the following constraints:

[0014] H1≤H≤H1+H2; or H≤H2

[0015] Wherein H1 is the junction depth of the N+ region, and H2 is the junction depth of the P- region.

[0016] The technical solution achieves at least the following beneficial effects: greatly improves the short-circuit resistance and latch-up capability of the device. BRIEF DESCRIPTION OF DRAWINGS

[0017] The drawings incorporated by reference in the specification and forming a part thereof, illustrate embodiments in which the principles of the present application are applied, and together with the description, serve to explain the principles of the present application. It is clear that the drawings described below are only some embodiments of the present application, and other drawings can be obtained from these drawings without creative labor for those skilled in the art. In the drawings:

[0018] Figure 1 The structure of the conventional carrier storage trench gate IGBT described in the present application is shown in the schematic diagram;

[0019] Figure 2 The local structure of the IGBT device provided by the present application is shown in the schematic diagram;

[0020] Figure 3 The side view of the region between the two trenches of the present application is shown in the schematic diagram. DETAILED DESCRIPTION

[0021] Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments, however, can be implemented in many different forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the inventive concept to those skilled in the art.

[0022] Carrier Stored trench gate IGBT, the basic structure is as shown in Figure 1 The IGBT structure adds an N-type CS (Carrier Stored) region 5 between the P-body region and the N-drift region, which plays a role in blocking holes, thereby increasing the carrier concentration below the P-body region, enhancing the conductance modulation effect, and greatly reducing the on-state voltage drop of the IGBT device. In order to achieve lower saturation voltage drop and switching loss, the trench density of the carrier stored trench gate IGBT is made larger and larger, which leads to an increase in the corresponding channel density, increases the saturation current density of the device, and reduces the short circuit resistance of the device.

[0023] The IGBT device of the present application periodically and intervally injects P-type impurities between the trenches 1 of the conventional carrier stored trench gate IGBT to form a P+ region 2 for reducing the channel density and greatly improving the short circuit resistance of the device; as shown in Figure 2 , 3 The structure shown in the figure combines the structure shown in Figure 1 , that is, the overall structure of the IGBT device provided by the present application.

[0024] In combination with Figures 1-3 , the IGBT device includes the structure of the carrier stored trench gate IGBT as shown in Figure 1 , and P-type impurities are periodically and intervally injected in the region between the trenches 1 and are pushed to form a P+ region 2. The P+ region 2 is in contact with the sidewall of the trench 1 and cannot form a conductive channel, thereby reducing the channel density, reducing the saturation current of the device, and improving the short circuit resistance of the device.

[0025] The N+ region 3 and the P- region 4 are the basic units for forming a conductive channel of the IGBT device. The present disclosure increases the P+ region 2 on the basis of the conventional structure, eliminates part of the N+ region 3 and the P- region 4, that is, reduces the channel, and improves the short circuit resistance of the device.

[0026] The injection dose of the P-type impurities injected by the P+ region 2 is 1-2 orders of magnitude higher than the injection dose of the P- region 4, that is, 10 n , n represents 1 or 2, and the 1-2 power of 10. The P+ region 2 has high doping concentration and low resistivity. When the device is turned on, most of the hole current will pass through the P+ region 2, rather than directly below the N+ region 3, thereby reducing the risk of turning on the parasitic transistor and improving the anti-latch-up capability of the device.

[0027] In the present disclosure, the sum of the areas of all P+ regions 2 is 1 / 10 to 4 / 5 of the sum of the areas between all trenches, i.e., S2=(1 / 10-4 / 5)S1, where S1 is the sum of the areas between all trenches and S2 is the sum of the areas of all P+ regions 2 formed between the trenches.

[0028] The width of the P+ region 2 is 1-100 um, preferably 1-10 um. The P+ regions 2 are configured as multiple spaced-apart regions with a spacing of 1-100 um, preferably 1-10 um. The width and spacing of the P+ regions ensure uniformity of the current when the device is turned on.

[0029] In the present disclosure, the junction depth H of the P+ region 2 satisfies the following constraints: H1≤H≤H1+H2; or H≤H2; where H1 is the junction depth of the N+ region 3 and H2 is the junction depth of the P- region 4. The P+ region junction depth can be less than or equal to the P- region junction depth and greater than the N+ region junction depth. If the P+ region junction depth is greater than the P- region junction depth, it will affect the doping concentration of the CS region 5, which is not conducive to reducing the saturation voltage drop of the device. If the P+ region junction depth is less than the N+ region junction depth, the channel cannot be eliminated, which fails to improve the short-circuit resistance of the device.

[0030] The present disclosure has been described by the above-described embodiments, which are merely examples of implementing the present disclosure. It must be pointed out that the disclosed embodiments do not limit the scope of the present disclosure. On the contrary, modifications and improvements made without departing from the spirit and scope of the present disclosure are within the scope of the patent protection of the present disclosure.

Claims

1. A short-circuit resistant carrier storage trench gate IGBT device, characterized by, The IGBT device is configured to include a plurality of spaced grooves (1), and a hole blocking layer (5), a P- region (4), an N+ region (3) and a P+ region (2) for improving the short circuit capability of the IGBT are formed between adjacent grooves (1); the CS layer (5) extends longitudinally, the P- region (4) is formed between the N+ region (3) and the CS layer (5), the P+ region (2) is periodically spaced along the extension direction of the CS layer (5), the bottom surface directly contacts the CS layer (5), and the top surface is located at the same horizontal plane as the N+ region (3); The P+ region (2) is injected with a P-type impurity injection dose which is 1-2 orders of magnitude higher than the P-type impurity injection dose of the P- region (4).

2. The high short-circuit tolerant carrier storage trench gate IGBT device of claim 1, wherein, The sum of the coverage areas of all P+ regions (2) accounts for 1 / 10-4 / 5 of the sum of the areas between all grooves.

3. The high short-circuit resistant current carrier storage trench gate IGBT device of claim 1, wherein, The width of the P+ region (2) is 1-100 um.

4. The high short-circuit resistance carrier storage trench gate IGBT device according to claim 1, characterized by, The P+ region (2) is configured to be spaced and multiple, and the pitch is 1-100 um.

5. The high short-circuit resistant current carrier storage trench gate IGBT device of claim 1, wherein, The junction depth H of the P+ region (2) satisfies the following constraints: H1≤H≤H1+H2; or H≤H2 Wherein, H1 is the junction depth of the N+ region (3), and H2 is the junction depth of the P- region (4).

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