A data recovery method and system

Abstract

The application belongs to the technical field of embedded systems, and particularly relates to a data recovery method and system, the method comprising: obtaining a sampling value in current sampling period sampling data through a logic circuit, the sampling value comprising a data edge number and position; obtaining recovery data according to the sampling value and edge residual data of a previous sampling period; the recovery data is data obtained after the sampling data is recovered, and the edge residual data comprises a to-be-recovered flag and a to-be-recovered position of the sampling data. The data recovery method can reduce the number of system components and PCB layout area, and is beneficial to improving the anti-clock jitter performance and integration. Based on the method, 100BASE-FX can be realized in FPGA.

Description

Technical Field

[0001] This application belongs to the field of embedded system technology, and in particular relates to a data recovery method and system, specifically involving the design of a 100 Mbps optical port PHY module. Background Technology

[0002] The core of the physical layer of Ethernet communication is the PHY chip, and its performance directly determines the network's transmission performance. Typically, communication systems are implemented using dedicated PHY transceiver chips, which increases overall system power consumption, material costs, and PCB area.

[0003] In communication systems with FPGA devices, implementing an optical port PHY transceiver based on the FPGA's internal resources can reduce the number of onboard chips and enhance system stability. For example, the 100BASE-FX Ethernet standard uses the FDDI physical layer standard, and the signals transmitted on its physical layer are NRZI-encoded 4B5B asynchronous serial signals. Therefore, the core of implementing a 100BASE-FX PHY transceiver in logic devices such as FPGAs lies in the implementation of the receiver's CDR (Clock Data Recovery) structure.

[0004] BO-CDR (Blind Oversampling Clock and Aata Recovery) is the main method for implementing digital CDR, based on the direct-take / phase detection coding method. This method has several advantages:

[0005] 1. Oversampling and data recovery can be implemented in digital circuits, which facilitates implementation in different digital systems;

[0006] 2. BO-CDR can immediately lock onto serial data within one oversampling cycle, making instantaneous phase acquisition possible;

[0007] 3. Implementing CDR digitally eliminates the influence of noise signals.

[0008] However, BO-CDR also has its drawbacks:

[0009] 1. BO-CDR based on direct sampling requires a high-frequency encoding clock. When recovering data at a rate of N Mbps, the encoding clock is required to be M*N MHz (where M is the oversampling rate), which is a significant challenge for conventional FPGAs.

[0010] 2. Secondly, since BO-CDR only recovers 1 bit of sampled value per cycle, this algorithm can perform well when the reference clock and data source frequencies are the same, but its resistance to clock jitter is very weak. When the reference clock and input data drift to each other, the bit error rate will be very high.

[0011] 3. Third, the digital implementation of the direct sampling method is relatively complex. However, there is no good solution to the problems of poor resistance to clock jitter and complex implementation. Summary of the Invention

[0012] The purpose of this application is to provide a data recovery algorithm and system that aims to solve the problems of high oversampling rate requirements and high bit error rate in traditional clock data recovery methods.

[0013] A first aspect of this application provides a data recovery method, the method comprising the following steps:

[0014] The sampling values ​​in the current sampling period are obtained through logic circuits. The sampling values ​​include the number and position of data edges.

[0015] The recovered data is obtained based on the sampled values ​​and the edge residual data from the previous sampling period. The recovered data is the data obtained after the sampled data has been recovered. The edge residual data includes the recovery flag and recovery position of the sampled data.

[0016] Furthermore, the recovered data is obtained based on the sampled values ​​and the residual data from the edge of the previous sampling period, including:

[0017] The recovered data is determined based on the sampled values ​​and the edge residual data from the previous sampling period, through preset design rules and the results of the preset design rules.

[0018] Furthermore, after obtaining the recovered data based on the sampled values ​​and the residual data from the edge of the previous sampling period, the above method also includes the following steps:

[0019] Based on the sampled values ​​of the current sampling period, determine the edge residual data of the sampled data in the current sampling period.

[0020] Furthermore, if the number of data edges is less than or equal to 2, the residual data at the edges of the sampled data in the current sampling period is determined based on the sampled values ​​of the current sampling period, including:

[0021] The flags to be recovered for the sampled data in the current sampling period are determined based on the number and location of the data edges.

[0022] Based on the position of the data edge, determine the position of the data to be recovered in the current sampling period.

[0023] Furthermore, based on the number and location of data edges, the flags to be recovered for the sampled data in the current sampling period are determined, including:

[0024] When the number of data edges is 0, or the number of data edges is 1 and the data edge is in the first half of the sampling period, there is no flag to be recovered in the sampled data of the current sampling period.

[0025] When the number of data edges is 2, or when the number of data edges is 1 and the data edge is in the second half of the sampling period, there is a flag to be recovered in the sampled data of the current sampling period.

[0026] Furthermore, the sampled values ​​in the current sampling period are obtained through logic circuits, including:

[0027] Oversampling of the sampled data is performed using a sampling circuit.

[0028] The oversampled data is shaped and filtered using a filtering circuit to obtain the number of data edges in the sampled data.

[0029] The location of the data edge in the sampled data is determined by the number of data edges in the sampled data.

[0030] Furthermore, after obtaining the recovered data based on the sampled values ​​and the residual data from the edge of the previous sampling period, the above method also includes the following steps:

[0031] The recovered data is processed into a source synchronization signal, which is a signal that synchronizes the recovered data with the local clock signal.

[0032] Furthermore, the recovered data will be processed into a source synchronization signal, including:

[0033] The recovered data is input into the FIFO control circuit to obtain clock-synchronized read / write and reset signals. The FIFO control circuit is a shift register.

[0034] The clock-synchronized read / write signal and reset signal are input into the FIFO circuit to obtain the source synchronization signal.

[0035] A second aspect of this application provides a data recovery system, including:

[0036] The signal preprocessing unit is used to obtain the sampled values ​​in the sampled data of the current sampling period through logic circuits. The sampled values ​​include the number and position of data edges.

[0037] The data recovery unit is used to recover data based on the sampled values ​​and the edge residual data of the previous sampling period. The recovered data is the data obtained after the sampled data has been recovered. The edge residual data includes the recovery flag and recovery position of the sampled data.

[0038] Furthermore, the data recovery unit includes:

[0039] Storage unit, used to store preset design rules and the results of preset design rules;

[0040] The processing unit is used to determine the recovered data based on the sampled value and the edge residual data of the previous sampling period, through preset design rules and the results of the preset design rules.

[0041] The beneficial effects of this application's embodiments compared to existing technologies are as follows: the above-described data recovery method implements the communication protocol in an FPGA, which can reduce the overall number of system components and PCB layout area, and is beneficial for improving clock jitter resistance and integration. Based on the above method, 100BASE-FX can be implemented in an FPGA.

[0042] Compared with existing standalone PHY chips, the method provided in this application can reduce the overall number of system components and PCB layout area, which is beneficial for improving clock jitter resistance and integration. It facilitates the design of low-power, highly integrated, and highly reliable systems. Attached Figure Description

[0043] Figure 1 A detailed flowchart of a data recovery method provided in one embodiment of this application;

[0044] Figure 2 A schematic diagram illustrating the principle of a data recovery method provided in an embodiment of this application;

[0045] Figure 3 A schematic diagram of a DRC Table provided in an embodiment of this application;

[0046] Figure 4 A schematic diagram of a rate balancing structure provided in an embodiment of this application;

[0047] Figure 5 This is a schematic diagram of the data recovery system provided in the embodiments of this application. Detailed Implementation

[0048] To make the technical problems, technical solutions, and beneficial effects to be solved by this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and are not intended to limit the scope of this application.

[0049] It should be noted that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0050] Figure 1 A schematic diagram of the data recovery method provided in the first embodiment of this application is shown. For ease of explanation, only the parts relevant to this embodiment are shown, and are described in detail below:

[0051] S2. Obtain the sampled value in the current sampling period through logic circuits. The sampled value includes the number and position of data edges.

[0052] In one or more embodiments, the above method includes the following steps:

[0053] Oversampling of the sampled data is performed using a sampling circuit.

[0054] The oversampled data is shaped and filtered using a filtering circuit to obtain the number of data edges in the sampled data.

[0055] The location of the data edge in the sampled data is determined by the number of data edges in the sampled data.

[0056] S4. Obtain the recovered data based on the sampled values ​​and the edge residual data from the previous sampling period; the recovered data is the data obtained after the sampled data has been recovered, and the edge residual data includes the recovery flag and recovery position of the sampled data.

[0057] In one or more embodiments, the recovered data is determined based on the sampled value and the edge residual data of the previous sampling period, through preset design rules and the results of preset design rules. In the first embodiment of this application, the data to be recovered is the serial signal in the FPGA to be recovered as a source synchronization signal synchronized with the local clock. Depending on the data to be recovered, the preset design rules and the results of preset design rules can be determined according to the specific data to be recovered.

[0058] In one or more embodiments, after obtaining the recovered data based on the sampled value and the edge residual data from the previous sampling period, the above method further includes the following steps:

[0059] Based on the sampled values ​​of the current sampling period, determine the edge residual data of the sampled data in the current sampling period.

[0060] The residual edge data includes whether the sampled data in the current sampling period includes a residual flag indicating whether the data to be recovered is included, and the position of the data to be recovered in the sampled data of the current sampling period. Based on the residual flag of the data to be recovered, it can be determined whether there is data to be recovered in the current sampling period, and it can be recovered in the next sampling period according to the corresponding position.

[0061] It should be noted that no residual data from the previous sampling period is obtained in the first sampling period. Therefore, the technical solution provided in this application starts automatically at the beginning of the second sampling period.

[0062] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0063] The data recovery method provided in the second embodiment of this application has the following overall principle block diagram: Figure 2 As shown. In this embodiment, the input is a set of 125Mbps differential serial signals containing only data, and the output is a set of source synchronization signals that synchronize the data and the clock (a local 125MHz clock). The data recovery method consists of three parts: signal preprocessing, data recovery, and rate balancing.

[0064] In this embodiment, the signal preprocessing section first performs 8x oversampling on the differential input 125Mbps serial signal to obtain the sample value of the serial signal. Then, the sample value obtained by oversampling is shaped and filtered, and the filtered data of the output sample value is input into the data recovery section. At the same time, the edge position (edge_info) of the 8-bit signal in the current sampling period is calculated based on the filtered data (filter_data), and the number of edges (edge_num) in the sample value is calculated based on the edge position (edge_info). The obtained edge position (edge_info) and edge number (edge_num) are then input into the data recovery section.

[0065] In this embodiment, the data recovery section uses the edge position (edge_info) and the number of edges (edge_num) of the eight-fold oversampled signal output by the signal preprocessing section, combined with the signal fed back from the lookup table (DRC_Table) preset by the data recovery algorithm in the previous sampling period, to perform a lookup table and recover the data included in the serial differential signal from the sampled values.

[0066] In this embodiment, the rate balancing section recovers the data stream from the sampled values, namely {valid1, valid0} and {data1, data0} in the figure, and inputs it into the FIFO control circuit and then into the FIFO circuit. The rate is balanced according to the local clock signal (local_dock) and processed into a uniform and uninterrupted data stream output synchronized with the local 125M clock.

[0067] The following is in conjunction with the instruction manual. Figure 3 The data recovery structure of the present invention will be further described. In this embodiment, specifically, the data recovery part further includes inferring the data recovery legacy flags and locations of the current sampling period, specifically including the following steps:

[0068] 1. Based on the number of edges (edge_num), edge position (edge_info) in the current sampling period, the position of the data edge in the previous sampling period (data_position), and the data to be recovered flag (get_before_data_en), query the preset data recovery table (DRC_Table) to generate the data recovered in this sampling period, a flag indicating whether there is any data to be recovered, and the position of the data to be recovered.

[0069] 2. The edge information of the current sampling period, including the position of the data edge (data_position) and the data to be recovered (get_before_data_en), is fed back into the preset data recovery table (DRC_Table). This information is then combined with the number of edges and the edge position of the next sampling period as input data for searching in the preset data recovery table.

[0070] In one or more embodiments, a preset data recovery table is as follows: Figure 3 As shown, in the data recovery table, each input data has a unique and definite output result. For example, if the input data has 2 data edges in the current sampling period, the edge position is represented by an 8-bit signal as 10000010, there is no data left to be recovered in the previous sampling period, and the position of the data to be recovered, then by using the preset data recovery table, the output recovered data [valid1,valid0}<={1'b1,1'b1};[data1,data0}<={filter data[data position],filter data[4]} can be determined. The recovered data includes the valid signal valid and the data signal data.

[0071] Meanwhile, based on the fact that there are 2 data edges in the current sampling period of the input data and the edge position is represented by an 8-bit signal as 10000010, the edge residual data of the current sampling period can be determined according to the preset data recovery table. In the current sampling period, there is a flag for data to be recovered, and the data to be recovered is located at the fifth bit.

[0072] In this embodiment, by Figure 3 As can be seen from the table, when the number of data edges is 0, or the number of data edges is 1 and the data edge is in the first half of the sampling period, there is no flag to be recovered in the sampled data of the current sampling period.

[0073] When the number of data edges is 2, or the number of data edges is 1 and the data edge is in the second half of the sampling period, there is a flag to be recovered in the sampled data of the current sampling period.

[0074] Then, based on the position of the data edge, the location of the data to be recovered in the current sampling period is determined.

[0075] Furthermore, the following will be combined with the appendix Figure 4 The working principle of the rate balancing section of this application is further described as follows:

[0076] 1. The principle of writing the recovered data to the FIFO control is as follows:

[0077] When implementing the write FIFO circuit, a 9-bit left shift register is used. The number of bits shifted to the left by the shift register is determined by the valid[1:0] signal in the valid signal of the above-mentioned recovered data, and the value shifted into the shift register is determined by the data[1:0] signal in the data signal of the above-mentioned recovered data.

[0078] As shown in Case 1 of the figure, when one bit of the valid signal is valid, the register is shifted to the left by 1 bit, and the value shifted into the register is the value of the data bit corresponding to the valid bit.

[0079] When two bits of the valid signal are valid, the register is shifted left by 2 bits, and the value shifted into the register is the value of the data bit corresponding to the valid bit.

[0080] As shown in Cases 2 and 3, when the total number of bits in the shift register is 8 bits, the value of the rightmost 8 bits is written to the FIFO circuit. When the total number of bits in the shift register is 9 bits, the value of the leftmost 8 bits is written to the FIFO circuit.

[0081] 2. The control principle of the FIFO circuit for reading FIFO data is as follows:

[0082] Once the register output value is detected to contain JK code, the FIFO circuit is reset, thus resetting its read / write pointer.

[0083] When the userdw value of the FIFO read port equals the set threshold, the read operation of the FIFO circuit is initiated until the FIFO is empty.

[0084] The third embodiment of this application is described in [reference 1]. Figure 5 A data recovery system is provided, comprising:

[0085] The signal preprocessing unit is used to obtain the sampled values ​​in the sampled data of the current sampling period through logic circuits. The sampled values ​​include the number and position of data edges.

[0086] The data recovery unit is used to recover data based on the sampled values ​​and the edge residual data of the previous sampling period. The recovered data is the data obtained after the sampled data has been recovered. The edge residual data includes the recovery flag and recovery position of the sampled data.

[0087] Furthermore, the data recovery unit includes:

[0088] Storage unit, used to store preset design rules and the results of preset design rules;

[0089] The processing unit is used to determine the recovered data based on the sampled value and the edge residual data of the previous sampling period, through preset design rules and the results of the preset design rules.

[0090] Based on the above embodiments, the data recovery method provided in this application implements the communication protocol in an FPGA, which can reduce the overall number of system components and PCB layout area, and is beneficial to improving clock jitter resistance and integration. Based on the above method, 100BASE-FX can be implemented in an FPGA.

[0091] Compared with existing standalone PHY chips, the method provided in this application can reduce the overall number of system components and PCB layout area, which is beneficial for improving clock jitter resistance and integration. It facilitates the design of low-power, highly integrated, and highly reliable systems.

[0092] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0093] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0094] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0095] In the embodiments provided in this application, it should be understood that the disclosed devices / terminal equipment and methods can be implemented in other ways. For example, the device / terminal equipment embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the displayed or discussed mutual coupling or direct coupling or communication connection may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0096] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0097] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0098] If the integrated module / unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments can also be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by a processor, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable medium can include: any entity or device capable of carrying the computer program code, recording media, USB flash drives, portable hard drives, magnetic disks, optical disks, computer memory, read-only memory (ROM), random access memory (RAM), electrical carrier signals, telecommunication signals, and software distribution media, etc. It should be noted that the content included in the computer-readable medium can be appropriately added or removed according to the requirements of legislation and patent practice in the jurisdiction. For example, in some jurisdictions, according to legislation and patent practice, computer-readable media do not include electrical carrier signals and telecommunication signals.

[0099] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A data recovery method, characterized in that, To implement the 100BASE-FX Ethernet standard in an FPGA, the following steps are included: The sampling value in the sampling data of the current sampling period is obtained through logic circuits, and the sampling value includes the number and position of data edges; The recovered data is obtained based on the sampled values ​​and the edge residual data from the previous sampling period; the recovered data is the data obtained after data recovery of the sampled data, and the edge residual data includes the recovery flag and recovery position of the sampled data; The process of obtaining recovered data based on the sampled value and the edge residual data from the previous sampling period includes: Based on the number of edges and edge positions in the current sampling period, as well as the position of data edges and the data to be recovered flags from the previous sampling period, a preset data recovery table is queried to generate the data recovered in the current sampling period, a flag indicating whether any data to be recovered remains, and the position of the data to be recovered. The information of the position of data edges and the data to be recovered flags in the current sampling period is fed back into the preset data recovery table and combined with the number of edges and edge positions in the next sampling period as input data for searching in the preset data recovery table. After obtaining the recovered data based on the sampled values ​​and the edge residual data from the previous sampling period, the method further includes the following steps: The recovered data is input into the FIFO control circuit to obtain clock-synchronized read / write signals and reset signals. The FIFO control circuit is a shift register. The clock-synchronized read / write signal and reset signal are input into the FIFO circuit to obtain the source synchronization signal, which is the signal that synchronizes the recovered data with the local clock signal.

2. The method as described in claim 1, characterized in that, After obtaining the recovered data based on the sampled values ​​and the edge residual data from the previous sampling period, the method further includes the following steps: Based on the sampled value of the current sampling period, determine the edge residual data of the sampled data in the current sampling period.

3. The method as described in claim 2, characterized in that, The number of data edges is less than or equal to 2. Determining the edge-residual data of the sampled data in the current sampling period based on the sampled value in the current sampling period includes: The recovery flag of the sampled data in the current sampling period is determined based on the number and position of the data edges. Based on the data edge position, determine the position to be recovered of the sampled data in the current sampling period.

4. The method as described in claim 3, characterized in that, The step of determining the flag to be recovered for the sampled data in the current sampling period based on the number and position of the data edges includes: When the number of data edges is 0, or the number of data edges is 1, and the data edge is in the first half of the sampling period, there is no flag to be recovered in the sampled data of the current sampling period; When the number of data edges is 2, or the number of data edges is 1 and the data edge is in the second half of the sampling period, there is a flag to be recovered in the sampled data of the current sampling period.

5. The method as described in claim 1, characterized in that, The step of obtaining the sampled value from the sampled data of the current sampling period through logic circuits includes: The sampled data is oversampled by a sampling circuit; The oversampled data is shaped and filtered using a filtering circuit to obtain the number of data edges in the sampled data. The position of the data edge in the sampled data is determined based on the number of data edges in the sampled data.

6. A data recovery system, characterized in that, Used to implement the 100BASE-FX Ethernet standard in FPGAs, including, The signal preprocessing unit is used to obtain the sampled values ​​in the sampled data of the current sampling period through logic circuits. The sampled values ​​include the number and position of data edges. A data recovery unit is used to obtain recovered data based on the sampled value and the edge residual data of the previous sampling period; the recovered data is the data obtained after data recovery of the sampled data, and the edge residual data includes the recovery flag and recovery position of the sampled data; Storage unit, used to store preset design rules and the results of preset design rules; The processing unit is used to query a preset data recovery table based on the number of edges and edge positions in the current sampling period, the position of data edges in the previous sampling period, and the data to be recovered flag, to generate the data recovered in the current sampling period, a flag indicating whether there is any data to be recovered, and the position of the data to be recovered; and to feed back the information of the position of the data edges and the data to be recovered flag in the current sampling period to the preset data recovery table, and combine it with the number of edges and edge positions in the next sampling period as input data to search the preset data recovery table; The data recovery system is further configured to: after obtaining the recovered data based on the sampled value and the edge residual data of the previous sampling period, input the recovered data into a FIFO control circuit to obtain clock-synchronized read / write signals and reset signals, wherein the FIFO control circuit is a shift register; input the clock-synchronized read / write signals and reset signals into the FIFO circuit to obtain a source synchronization signal, wherein the source synchronization signal is a signal that synchronizes the recovered data with the local clock signal.

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