MEMS device and method of manufacturing the same

Abstract

The application discloses a MEMS device and a manufacturing method thereof. The manufacturing method comprises the following steps: forming a dielectric layer on a substrate, forming a patterned first conductive layer on the dielectric layer; forming an isolation layer on the dielectric layer and the first conductive layer, the isolation layer covering the first conductive layer; forming a barrier layer on the isolation layer, the barrier layer covering the isolation layer; forming a first groove in the isolation layer and the barrier layer, the first groove exposing part of the first conductive layer; forming a sacrificial layer on the barrier layer and the exposed first conductive layer, the sacrificial layer covering the barrier layer and filling the first groove; forming a second groove in the sacrificial layer, the second groove exposing part of the first conductive layer; forming a second conductive layer on the sacrificial layer and the exposed first conductive layer, the second conductive layer covering the sacrificial layer and filling the second groove; forming a third groove in the second conductive layer; and releasing the sacrificial layer. The manufacturing method can improve the structural stability of the MEMS device.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular to a MEMS device and a manufacturing method thereof. BACKGROUND

[0002] MEMS devices such as inertial sensors manufactured based on a MEMS (Micro Electro Mechanical System) processing technology have been widely applied, and have attracted wide attention due to advantages such as simple structure, good compatibility with microelectronic manufacturing technology, mass production, small area occupation, and convenient use.

[0003] Taking an inertial sensor as an example, the inertial sensor usually includes a device wafer. Referring to FIG. 1, the existing device wafer usually includes, from bottom to top, a substrate 10, a first dielectric layer 20, a first conductive layer 30, a second dielectric layer 40, and a second conductive layer 50. Figure 1 The first conductive layer 30 and the second conductive layer 50 are patterned conductive layers. The patterned first conductive layer 30 serves as a wiring and a capacitor plate of a detection capacitor, and the patterned second conductive layer 50 forms a comb structure. The second dielectric layer 40 under the comb structure is released by an etching process to form a cavity, so that the comb structure becomes partially movable.

[0004] Referring to FIG. 2, the existing device wafer does not have a barrier layer, and when the second dielectric layer 40 under the comb structure is released by the etching process, the first dielectric layer 20 under the first conductive layer 30 (the first dielectric layer 20 and the second dielectric layer 40 are usually made of the same material, such as silicon oxide) is side-etched. When the side-etching is too large, the structural stability of the device wafer is affected. Figure 2 Therefore, improvements are needed to at least partially solve the above problems.

[0005] SUMMARY

[0006] A series of simplified concepts are introduced in the summary section, which will be further described in detail in the detailed description section. The summary section of the present application does not mean to attempt to limit the key features and essential technical features of the claimed technical solutions, nor to determine the protection scope of the claimed technical solutions.

[0007] In order to at least partially solve the above problems, according to a first aspect of the present application, a manufacturing method of a MEMS device is provided, which includes:

[0008] forming a dielectric layer on a substrate, and forming a patterned first conductive layer on the dielectric layer;

[0009] ​forming an isolation layer on the dielectric layer and the first conductive layer, the isolation layer covering the first conductive layer;

[0010] forming a barrier layer on the isolation layer, the barrier layer covering the isolation layer;

[0011] forming a first trench in the isolation layer and the barrier layer, the first trench exposing a portion of the first conductive layer;

[0012] forming a sacrificial layer on the barrier layer and the exposed first conductive layer, the sacrificial layer covering the barrier layer and filling the first trench;

[0013] forming a second trench in the sacrificial layer on the first conductive layer, the second trench partially located in the first trench, the second trench exposing a portion of the first conductive layer;

[0014] forming a second conductive layer on the sacrificial layer and the exposed first conductive layer, the second conductive layer covering the sacrificial layer and filling the second trench;

[0015] forming a third trench in the second conductive layer, the third trench exposing a portion of the sacrificial layer;

[0016] releasing the sacrificial layer.

[0017] Exemplarily, a width of the second trench is smaller than a width of the first trench, and the second trench does not expose the barrier layer.

[0018] Exemplarily, a material of the dielectric layer comprises silicon oxide;

[0019] a material of the first conductive layer comprises doped polysilicon;

[0020] a material of the isolation layer comprises silicon oxide;

[0021] a material of the barrier layer comprises undoped polysilicon;

[0022] a material of the sacrificial layer comprises silicon oxide;

[0023] a material of the second conductive layer comprises doped polysilicon.

[0024] Exemplarily, the manufacturing method comprises:

[0025] releasing the sacrificial layer by gaseous hydrofluoric acid.

[0026] Exemplarily, the dielectric layer is formed by an oxidation process;

[0027] the isolation layer and the sacrificial layer are formed by a PECVD process;

[0028] The second conductive layer is formed by a vapor phase epitaxy process.

[0029] Exemplarily, the third trench is formed in the second conductive layer to make the second conductive layer have a comb structure.

[0030] The sacrificial layer is released to make the comb structure partially movable.

[0031] Exemplarily, the manufacturing method further comprises:

[0032] After the isolation layer is formed on the medium layer and the first conductive layer, the isolation layer is planarized;

[0033] After the sacrificial layer is formed on the barrier layer, the sacrificial layer is planarized;

[0034] After the second conductive layer is formed on the sacrificial layer, the second conductive layer is planarized.

[0035] According to a second aspect of the present application, a MEMS device is provided, which comprises:

[0036] a substrate;

[0037] a medium layer on the substrate;

[0038] a first conductive layer on the medium layer, the first conductive layer having a first opening exposing part of the medium layer;

[0039] an isolation layer on the medium layer and in the first opening, an upper surface of the isolation layer being higher than an upper surface of the first conductive layer;

[0040] a barrier layer on the isolation layer, the isolation layer and the barrier layer having a second opening on the first conductive layer, the second opening exposing part of the first conductive layer;

[0041] a second conductive layer on the first conductive layer and partially in the second opening.

[0042] Exemplarily, the medium layer comprises silicon oxide;

[0043] The first conductive layer comprises doped polysilicon;

[0044] The isolation layer comprises silicon oxide;

[0045] The barrier layer comprises undoped polysilicon;

[0046] The second conductive layer comprises doped polysilicon.

[0047] Exemplarily, the second conductive layer has a cavity between the isolation layer and the barrier layer, and the second conductive layer is not in contact with the barrier layer.

[0048] Exemplarily, the second conductive layer has a comb structure.

[0049] Exemplarily, the MEMS device is an inertial sensor.

[0050] According to the MEMS device and the manufacturing method thereof, by arranging the barrier layer in the MEMS device, side notching under the first conductive layer can be effectively avoided, and the structural stability of the MEMS device is ensured. BRIEF DESCRIPTION OF DRAWINGS

[0051] The following drawings for this application are hereby incorporated into this application as part of this application for the purpose of understanding this application. The embodiments of this application and the description thereof illustrated in the drawings explain the apparatus and principles of this application. In the drawings,

[0052] Figure 1 It is a structural schematic diagram of a device wafer in the prior art, wherein the second dielectric layer is not released;

[0053] Figure 2 It is a structural schematic diagram of a device wafer in the prior art, wherein the second dielectric layer is released;

[0054] Figure 3 It is a flowchart of a manufacturing method of a MEMS device according to an embodiment of this application;

[0055] Figures 4-10 It is a cross-sectional schematic diagram in the manufacturing process of a MEMS device according to an embodiment of this application;

[0056] Figure 11 It is a structural schematic diagram of a MEMS device according to an embodiment of this application.

[0057] Explanation of reference signs:

[0058] 10-substrate, 20-first dielectric layer, 30-first conductive layer, 40-second dielectric layer, 50-second conductive layer;

[0059] 100-substrate, 200-dielectric layer, 300-first conductive layer, 400-isolation layer, 500-barrier layer, 600-sacrificial layer, 700-second conductive layer, 710-first comb portion, 720-second comb portion;

[0060] A-first trench, B-second trench, C-third trench, D-second opening. DETAILED DESCRIPTION

[0061] In the following description, numerous specific details are set forth to provide a more thorough understanding of the present application. However, it will be apparent to one of skill in the art upon

[0062] It should be understood that the present application can be carried out in various forms without departing from the spirit or essential characteristics thereof. Rather, the present application is to cover all possible modifications and equivalents falling within the spirit and scope of the application. In the drawings, the size and relative sizes of layers and regions can be exaggerated for clarity. Like reference numerals can represent like elements throughout.

[0063] It should be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.

[0064] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures.

[0065] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0066] Embodiments of the application are described herein with reference to the drawings, which show ideal embodiments (and intermediate structures) of the application as schematic cross-sectional views. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments of the application should not be construed as limited to the particular shapes of the illustrations but are to include deviations in shapes that result from, for example, manufacturing. Thus, the shapes shown in the figures are illustrative and should not be construed as limited in any respect.

[0067] Reference is made to the drawings, which show ideal embodiments (and intermediate structures) of the application as schematic cross-sectional views. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments of the application should not be construed as limited to the particular shapes of the illustrations but are to include deviations in shapes that result from, for example, manufacturing. Thus, the shapes shown in the figures are illustrative and should not be construed as limited in any respect. Figures 3-10 A method for manufacturing a MEMS device according to an embodiment of the application is exemplarily illustrated, which comprises the following steps:

[0068] S100: Forming a dielectric layer 200 on a substrate 100, and forming a patterned first conductive layer 300 on the dielectric layer 200.

[0069] Specifically, reference is made to the drawings, which show ideal embodiments (and intermediate structures) of the application as schematic cross-sectional views. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are to be expected. Thus, embodiments of the application should not be construed as limited to the particular shapes of the illustrations but are to include deviations in shapes that result from, for example, manufacturing. Thus, the shapes shown in the figures are illustrative and should not be construed as limited in any respect. Figure 4 In step S100, the dielectric layer 200 can be formed on the substrate 100 by an oxidation process, which can be a thermal oxidation process, a wet oxidation process or a chemical oxidation process, and the dielectric layer 200 covers the upper surface of the substrate 100. After the formation of the dielectric layer 200, a trench can be formed in the dielectric layer 200 by a dry etching process or a wet etching process, which penetrates through the dielectric layer 200 and exposes the substrate 100. Then, the first conductive layer 300 can be formed on the dielectric layer 200 by a chemical vapor deposition process, which covers and fills the upper surface of the dielectric layer 200, and then a resist layer is formed on the surface of the first conductive layer 300, the resist layer is patterned by a photolithography process to form a resist mask, and the first conductive layer 300 is etched via the resist mask to form the patterned first conductive layer 300. After that, the resist mask can be removed by dissolving or ashing with a solvent. The substrate 100 can be a silicon substrate. In some embodiments, the material of the substrate 100 can also include Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs or other III / V compound semiconductors, and can also include a multi-layer structure composed of these semiconductors, etc. Alternatively, the substrate 100 can be a silicon-on-insulator (SOI), a stacked silicon-on-insulator (SSOI), a stacked silicon germanium-on-insulator (S-SiGeOI), a silicon germanium-on-insulator (SiGeOI) and a germanium-on-insulator (GeOI), etc. Those skilled in the art can select as needed. The material of the dielectric layer 200 includes but is not limited to silicon oxide. The material of the first conductive layer 300 includes but is not limited to doped polysilicon (Dpoly). In some embodiments, the material of the first conductive layer 300 can also be doped monocrystalline silicon or metal.

[0070] S200: Forming an isolation layer 400 on the dielectric layer 200 and the first conductive layer 300, the isolation layer 400 covering the first conductive layer 300.

[0071] Specifically, referring to the accompanying drawings, Figure 4 After the patterned first conductive layer 300 is formed on the dielectric layer 200 by step S100, the first conductive layer 300 has a first opening exposing the dielectric layer 200. In step S200, the isolation layer 400 can be deposited on the dielectric layer 200 and the first conductive layer 300 by a CVD (Chemical Vapor Deposition) process, such as a PECVD (Plasma Enhanced Chemical Vapor Deposition) process or other suitable CVD process. The isolation layer 400 covers the upper surface of the first conductive layer 300 and fills the first opening in the first conductive layer 300. After the isolation layer 400 is formed, the upper surface thereof can be planarized, such as by a CMP (Chemical Mechanical Polishing) process, so that the upper surface of the isolation layer 400 becomes a plane. The material of the isolation layer 400 includes but is not limited to silicon oxide.

[0072] S300: Forming a barrier layer 500 on the isolation layer 400, the barrier layer 500 covering the isolation layer 400.

[0073] Specifically, referring to the accompanying drawings, Figure 4 In step S300, the barrier layer 500 can be deposited on the isolation layer 400 by a CVD (Chemical Vapor Deposition) process, covering the upper surface of the isolation layer 400. The material of the barrier layer 500 includes but is not limited to undoped polysilicon (Upoly). The isolation layer 400 is used to isolate the first conductive layer 300 and the barrier layer 500, avoiding ions in the first conductive layer 300 from entering the barrier layer 500 (Upoly) to make the barrier layer 500 conductive and cause the MEMS device to fail.

[0074] S400: Forming a first trench A in the isolation layer 400 and the barrier layer 500, the first trench A exposing part of the first conductive layer 300.

[0075] Specifically, referring to the accompanying drawings, Figure 5In step S400, the isolation layer 400 and the barrier layer 500 above the first conductive layer 300 are etched using a dry etching process or a wet etching process to form a first trench A within the isolation layer 400 and the barrier layer 500. The first trench A exposes a portion of the first conductive layer 300. The width of the first trench A can be smaller than the width of the first conductive layer 300 below it, so that the bottom of the first trench A is completely located on the first conductive layer 300.

[0076] S500: A sacrificial layer 600 is formed on the barrier layer 500 and the exposed first sacrificial layer 600, the sacrificial layer 600 covering the barrier layer 500 and filling the first trench A.

[0077] Specifically, see Appendix Figure 6 In step S400, a sacrificial layer 600 can be deposited on the barrier layer 500 and the first conductive layer 300 exposed through the first trench A using a CVD process, such as PECVD or other suitable CVD processes. The sacrificial layer 600 covers the upper surface of the barrier layer 500 and fills the first trench A. After the sacrificial layer 600 is formed, its upper surface can be planarized, for example, by a CMP process, making the upper surface of the barrier layer 500 planar. The sacrificial layer 600 and the isolation layer 400 can be made of the same material, that is, the material of the sacrificial layer 600 includes, but is not limited to, silicon oxide. The sacrificial layer 600 (silicon oxide) and the barrier layer 500 (Upoly) are made of different materials, so that when the sacrificial layer 600 is subsequently released, the barrier layer 500 will not be released, and the isolation layer 400 below the barrier layer 500 is also not easily released.

[0078] S600: A second trench B is formed in the sacrificial layer 600 on the first conductive layer 300. The second trench B is partially located in the first trench A, and a portion of the first conductive layer 300 is exposed in the second trench B.

[0079] Specifically, see Appendix Figure 7The second trench B is formed in the sacrificial layer 600 by etching the sacrificial layer 600 above the first conductive layer 300 through a dry etching process or a wet etching process. The lower part of the second trench B is located in the first trench A (in the sacrificial layer 600), and the lower part of the second trench B exposes part of the first conductive layer 300. The upper part of the second trench B is located above the first trench A (in the sacrificial layer 600). In the embodiment of the present application, the width of the second trench B is smaller than the width of the first trench A, and the second trench B does not expose the barrier layer 500. That is, there is a certain thickness of the sacrificial layer 600 between the side surface of the barrier layer 500 and the second trench B as a spacing. The presence of the sacrificial layer 600 makes the second conductive layer 700 not in direct contact with the barrier layer 500 when the second conductive layer 700 is formed in the second trench B later, avoiding the ions in the first conductive layer 300 from entering the barrier layer 500 (Upoly) to make the barrier layer 500 conductive, thereby protecting the insulating properties of the barrier layer 500 and avoiding device failure caused by doping and conduction. In some other embodiments, the barrier layer 500 can be an insulating material that is not Upoly. In this case, the width of the second trench B can be smaller than or equal to the width of the first trench A, and the second trench B can expose the barrier layer 500.

[0080] S700: Forming a second conductive layer 700 on the sacrificial layer 600 and the exposed first conductive layer 300, the second conductive layer 700 covering the sacrificial layer 600 and filling the second trench B.

[0081] Specifically, referring to FIG. 6, the second conductive layer 700 is formed on the sacrificial layer 600 and the exposed first conductive layer 300 by a vapor phase epitaxy process. The second conductive layer 700 covers the upper surface of the sacrificial layer 600 and fills the second trench B. Figure 8 The second conductive layer 700 is formed on the sacrificial layer 600 and the exposed first conductive layer 300 by a vapor phase epitaxy process. The second conductive layer 700 covers the upper surface of the sacrificial layer 600 and fills the second trench B. After the second conductive layer 700 is formed, the upper surface thereof can be planarized, for example, by a CMP process to make the upper surface of the epitaxial layer planar. The material of the second conductive layer 700 includes but is not limited to doped polysilicon.

[0082] S800: Forming a third trench C in the second conductive layer 700, the third trench C exposing part of the sacrificial layer 600;

[0083] Specifically, referring to FIG. 7, the third trench C is formed in the second conductive layer 700 by etching the second conductive layer 700 through a dry etching process or a wet etching process. The third trench C exposes part of the sacrificial layer 600. Figure 9In step S800, a resist layer can be formed on the upper surface of the second conductive layer 700, the resist layer is patterned by a photolithography process to form a resist mask, and the second conductive layer 700 is etched through the resist mask to form a third trench C penetrating through the second conductive layer 700, and the third trench C exposes part of the second sacrificial layer 600. Then, the resist mask can be removed by solvent dissolution or ashing. The third trench C formed in the second conductive layer 700 is used to make the second conductive layer 700 have a comb structure, which includes a first comb portion 710 and a second comb portion 720. The first comb portion 710 is directly connected with the first conductive layer 300 as a fixed electrode, and the second comb portion 720 is spaced apart from the first comb portion 710 (spaced apart by the third trench C) and not directly connected with the first conductive layer 300 as an inertial electrode.

[0084] S900: releasing the sacrificial layer 600.

[0085] Specifically, referring to the accompanying drawings, Figure 10 In step S900, the sacrificial layer 600 is released by using a gaseous etchant, which can be gaseous hydrofluoric acid (HF) for example. The release of the sacrificial layer 600 is used to form a cavity between the second conductive layer 700 and the barrier layer 500 and the isolation layer 400, i.e., to form a cavity between the second comb portion 720 and the barrier layer 500, so that the second comb portion 720 becomes a movable structure, thereby forming a MEMS device. It should be noted that the sacrificial layer 600 between the barrier layer 500 and the second conductive layer 700 is not completely released, and the edge of the second comb portion 720 can be connected with the sacrificial layer 600 that is not released. That is, the first comb portion 710 is directly connected with the first conductive layer 300; and the second comb portion 720 is connected with the first conductive layer 300 through the sacrificial layer 600 that is not released. After the second comb portion 720 becomes a movable structure, it can change its position relative to the first comb portion 710 under the action of an inertial force, so that the inertial force can be measured by detecting the change of capacitance between the first comb portion 710 and the second comb portion 720, and the MEMS device realizes the function of an inertial sensor.

[0086] In the embodiments of the present application, since the material of the barrier layer 500 is Upoly, it will not be corroded by the hydrofluoric acid in step S900, and can effectively prevent the hydrofluoric acid from corroding the isolation layer 400 (and the dielectric layer 200) below the barrier layer 500, thereby avoiding side etching under the first conductive layer 300 and ensuring the structural stability of the MEMS device. Even if the isolation layer 400 below the barrier layer 500 has some side etching, it will not affect the overall structural stability of the MEMS device. Using Upoly as the barrier layer 500 can effectively avoid the generation of difficult-to-remove byproducts of gaseous hydrofluoric acid (HF) when releasing the sacrificial layer 600, thereby ensuring the performance of the MEMS device. In some embodiments, silicon nitride can also be used as the barrier layer 500, but this solution will be difficult to remove byproducts generated in the process of releasing the sacrificial layer 600 by gaseous hydrofluoric acid, which will affect the performance of the MEMS device to some extent. Using Upoly as the barrier layer 500 can also optimize the stress state of the MEMS device. In the embodiments of the present application, the barrier layer 500 (Upoly) and the first conductive layer 300 are isolated by the isolation layer 400, and the barrier layer 500 (Upoly) and the second conductive layer 700 (Dpoly) are isolated by the sacrificial layer 600, so that the barrier layer 500 is not in direct contact with the first conductive layer 300 and the second conductive layer 700, thereby effectively preventing the barrier layer 500 from being doped by ions in the first conductive layer 300 and the second conductive layer 700, which can cause device failure.

[0087] In some embodiments, the method for manufacturing the MEMS device further includes a step of forming a cap sheet and a step of bonding the cap sheet with the second conductive layer 700, the specific implementation manners of which are known to those skilled in the art, and thus will not be described in detail herein.

[0088] Referring to FIG. 1, Figure 11 The present application also provides a MEMS device, which can be formed by the above manufacturing method. The MEMS device includes a substrate 100, a dielectric layer 200, a first conductive layer 300, an isolation layer 400, a barrier layer 500, and a second conductive layer 700.

[0089] The substrate 100 can be a silicon substrate. In some embodiments, the material of the substrate 100 can also include Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP, InGaAs, or other III / V compound semiconductors, and can also include a multilayer structure formed by these semiconductors, etc. Alternatively, the substrate 100 can be a silicon-on-insulator (SOI), a stacked silicon-on-insulator (SSOI), a stacked germanium-silicon-on-insulator (S-SiGeOI), a germanium-silicon-on-insulator (SiGeOI), and a germanium-on-insulator (GeOI), etc. Those skilled in the art can select as needed.

[0090] The dielectric layer 200 is on the substrate 100, and the material of the dielectric layer 200 includes but is not limited to silicon oxide.

[0091] The first conductive layer 300 is on the dielectric layer 200, and the first conductive layer 300 has a first opening formed by patterning the first conductive layer 300, and the first opening exposes part of the dielectric layer 200. The material of the first conductive layer 300 includes but is not limited to doped polysilicon (Dpoly). In some embodiments, the material of the first conductive layer 300 can also be doped monocrystalline silicon or metal.

[0092] The isolation layer 400 is on the dielectric layer 200 and in the first opening, and the upper surface of the isolation layer 400 is higher than the upper surface of the first conductive layer 300. The material of the isolation layer 400 includes but is not limited to silicon oxide.

[0093] The barrier layer 500 is on the isolation layer 400, and the material of the barrier layer 500 includes but is not limited to undoped polysilicon (Upoly). The isolation layer 400 is used to isolate the first conductive layer 300 and the barrier layer 500, so as to avoid ions in the first conductive layer 300 from entering the barrier layer 500 (Upoly) to make the barrier layer 500 conductive and cause the MEMS device to fail. The isolation layer 400 and the barrier layer 500 have a second opening D on the first conductive layer 300, and the second opening D exposes part of the first conductive layer 300.

[0094] The second conductive layer 700 is located on the exposed first conductive layer 300 and partially in the second opening D. The material of the second conductive layer 700 includes but is not limited to doped polysilicon. The second conductive layer 700 includes a comb structure, specifically, the comb structure includes a first comb portion 710 and a second comb portion 720, the first comb portion 710 is directly connected with the first conductive layer 300 as a fixed electrode, and the second comb portion 720 is spaced apart from the first comb portion 710 and is not directly connected with the first conductive layer 300 as an inertial electrode. The second conductive layer 700 has a cavity between the isolation layer 400 and the barrier layer 500, which makes the second conductive layer 700 not directly contact with the barrier layer 500 (Upoly), avoids ions in the second conductive layer 700 from entering the barrier layer 500 to make the barrier layer 500 conductive, protects the insulation properties of the barrier layer 500, and avoids device failure caused by doped conduction. In some other embodiments, the barrier layer 500 can be an insulating material that is not Upoly, at this time, the second conductive layer 700 can partially contact with the barrier layer 500. The second conductive layer 700 has a cavity between the isolation layer 400 and the barrier layer 500, that is, the second comb portion 720 has a cavity between the second comb portion 720 and the barrier layer 500, which makes the second comb portion 720 a movable structure, which will change its position relative to the first comb portion 710 under the action of an inertial force, so that by detecting the capacitance change between the first comb portion 710 and the second comb portion 720, the inertial force can be measured, so that the MEMS device realizes the function of an inertial sensor. That is, the MEMS device of the embodiments of the present application can be an inertial sensor. The inertial sensor can further include a cap sheet, the cap sheet can be bonded with the second conductive layer 700 through a bonding structure to form a closed cavity, so that the groove in the second conductive layer 700 and the cavity between the second conductive layer 700 and the isolation layer 400 and the barrier layer 500 are isolated from the external environment, avoiding the internal structure of the inertial sensor from being affected by the external environment to cause poor working stability.

[0095] Although example embodiments have been described herein with reference to the accompanying drawings, it is to be understood that the example embodiments are only exemplary and are not intended to limit the scope of the present application. Those of ordinary skill in the art can make various changes and modifications without departing from the scope and spirit of the present application. All such changes and modifications are intended to be included within the scope of the present application as claimed.

[0096] In the specification provided herein, a large number of specific details are described. However, it can be understood that the embodiments of the present application can be practiced without these specific details. In some examples, well-known methods, structures and techniques are not shown in detail in order not to obscure the understanding of the present specification.

[0097] Similarly, it should be understood that, in order to streamline this application and aid in understanding one or more of the various inventive aspects, features of this application may sometimes be grouped together in a single embodiment, figure, or description thereof in the description of exemplary embodiments of this application. However, this approach should not be construed as reflecting an intention that the claimed application requires more features than are expressly recited in each claim. Rather, as reflected in the corresponding claims, its inventive point lies in solving the corresponding technical problem with features fewer than all features of a single disclosed embodiment. Therefore, the claims following the detailed description are hereby expressly incorporated into that detailed description, wherein each claim itself is a separate embodiment of this application.

[0098] Those skilled in the art will understand that, apart from the mutual exclusion of features, all features disclosed in this specification (including the accompanying claims, abstract, and drawings) and all processes or elements of any method or apparatus so disclosed can be combined in any combination. Unless otherwise expressly stated, each feature disclosed in this specification (including the accompanying claims, abstract, and drawings) may be replaced by an alternative feature serving the same, equivalent, or similar purpose.

[0099] Furthermore, those skilled in the art will understand that although some embodiments described herein include certain features but not others included in other embodiments, combinations of features from different embodiments are intended to be within the scope of this application and form different embodiments. For example, in the claims, any one of the claimed embodiments can be used in any combination.

[0100] It should be noted that the above embodiments are illustrative of this application and not restrictive of this application, and that those skilled in the art can devise alternative embodiments without departing from the scope of the appended claims.

Claims

1. A method of manufacturing a MEMS device, characterized by, Comprising: forming a dielectric layer on a substrate, forming a patterned first conductive layer on the dielectric layer; forming an isolation layer on the dielectric layer and the first conductive layer, the isolation layer covering the first conductive layer; forming a barrier layer on the isolation layer, the barrier layer covering the isolation layer; forming a first trench in the isolation layer and the barrier layer, the first trench exposing part of the first conductive layer; forming a sacrificial layer on the barrier layer and the exposed first conductive layer, the sacrificial layer covering the barrier layer and filling the first trench; forming a second trench in the sacrificial layer on the first conductive layer, the second trench partially located in the first trench, the second trench exposing part of the first conductive layer; forming a second conductive layer on the sacrificial layer and the exposed first conductive layer, the second conductive layer covering the sacrificial layer and filling the second trench; forming a third trench in the second conductive layer, the third trench exposing part of the sacrificial layer; releasing the sacrificial layer.

2. The production method according to claim 1, characterized by Comprising: a material of the dielectric layer comprises silicon oxide; a material of the first conductive layer comprises doped polysilicon; a material of the isolation layer comprises silicon oxide; a material of the barrier layer comprises undoped polysilicon; a material of the sacrificial layer comprises silicon oxide; a material of the second conductive layer comprises doped polysilicon.

3. The manufacturing method of claim 2, wherein: a width of the second trench is smaller than a width of the first trench, the second trench does not expose the barrier layer.

4. The manufacturing method of claim 2, wherein: the manufacturing method comprises: releasing the sacrificial layer by gaseous hydrofluoric acid.

5. The manufacturing method of claim 2, wherein: the dielectric layer is formed by an oxidation process; the isolation layer and the sacrificial layer are formed by a PECVD process; the second conductive layer is formed by a vapor phase epitaxy process.

6. The manufacturing method of claim 1, wherein: forming the third trench in the second conductive layer to have a comb structure in the second conductive layer; releasing the sacrificial layer to have the comb structure partially movable.

7. The manufacturing method of claim 1, wherein: the manufacturing method further comprises: planarizing the isolation layer after forming the isolation layer on the dielectric layer and the first conductive layer; planarizing the sacrificial layer after forming the sacrificial layer on the barrier layer and the exposed first conductive layer; planarizing the second conductive layer after forming the second conductive layer on the sacrificial layer and the exposed first conductive layer.

8. A MEMS device, characterized by Comprising: a substrate; a dielectric layer on the substrate; a first conductive layer on the dielectric layer, the first conductive layer having a first opening therein, the first opening exposing part of the dielectric layer; an isolation layer on the dielectric layer and in the first opening, an upper surface of the isolation layer being higher than an upper surface of the first conductive layer; a blocking layer on the isolation layer, the isolation layer and the blocking layer having a second opening on the first conductive layer, the second opening exposing part of the first conductive layer; a second conductive layer on the first conductive layer and partially in the second opening. 9.The MEMS device of claim 8, wherein: a material of the dielectric layer comprises silicon oxide; a material of the first conductive layer comprises doped polysilicon; a material of the isolation layer comprises silicon oxide; a material of the blocking layer comprises undoped polysilicon; a material of the second conductive layer comprises doped polysilicon. 10.The MEMS device of claim 9, wherein: the second conductive layer has a cavity between the second conductive layer and the isolation layer and the blocking layer, and the second conductive layer does not contact the blocking layer. 11.The MEMS device of claim 8, wherein: the second conductive layer has a comb structure. 12.The MEMS device of claim 8, wherein: the MEMS device is an inertial sensor.

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