Bandgap reference circuit

Abstract

This disclosure relates to a bandgap reference circuit. A bandgap voltage reference circuit includes a plurality of incremental base-emitter voltage (ΔVbe) cells arranged in series extending between a first voltage rail and a second voltage rail. Each ΔVbe cell includes a transistor having a single first emitter connection and eight second emitter connections. The single first emitter connection of a second transistor in the series arrangement is coupled to one of the eight second emitter connections of a first transistor in the series arrangement, and one of the eight second emitter connections of the second transistor is coupled to the single first emitter connection of a third transistor in the series arrangement to form an electrical path from the first transistor to the third transistor. A resistor is located at the distal end of the series arrangement. The output voltage across the resistor includes the sum of the incremental base-emitter voltages generated by the plurality of ΔVbe cells.

Description

Technical Field

[0001] This disclosure generally relates to a reference circuit, and more specifically, to a bandgap reference circuit having a multi-NPN transistor configuration with minimal possible surface area, thereby enabling the reduction of incremental mechanical stress on the incremental base-emitter voltage (ΔVbe) cells of the circuit and generating a highly accurate bandgap voltage. Background Technology

[0002] Bandgap reference voltage circuits are widely used in integrated circuits that require a fixed reference voltage that does not change with variations in supply voltage, temperature, and other factors. Therefore, reference generators are implemented in a wide range of electronic applications requiring precise signal processing and voltage reference circuitry.

[0003] Mechanical stress in the reference voltage circuit formed in traditional plastic packages can lead to temperature drift or lifetime drift due to aging and inaccurate bandgap voltage reference caused by packaging. This stress manifests as localized variations in chip area and causes changes and drift in the base-emitter voltage of the bipolar transistor, and consequently, in the output voltage of the bandgap reference. Summary of the Invention

[0004] According to one aspect of the present invention, a bandgap voltage reference circuit is provided, comprising:

[0005] A plurality of incremental base-emitter voltage (ΔVbe) units arranged in series extending between a first voltage rail and a second voltage rail, wherein each ΔVbe unit includes a transistor comprising:

[0006] A single first emitter connection; and

[0007] Eight (8) second emitter connections;

[0008] The single first emitter connection of the second transistor in the series arrangement is coupled to one of the eight second emitter connections of the first transistor in the series arrangement, and one of the eight second emitter connections of the second transistor is coupled to the single first emitter connection of the third transistor in the series arrangement to form an electrical path from the first transistor to the third transistor.

[0009] The resistor at the far end of the series arrangement, wherein the output voltage across the resistor includes the sum of the incremental base-emitter voltages generated by the plurality of ΔVbe units.

[0010] According to one or more embodiments of the present invention, the ΔVbe cells in the plurality of ΔVbe cells are constructed and arranged in a 3×3 array, the single first emitter connected to the center of the array and surrounded by the eight second emitter connections, wherein the single first emitter connection has a different size or other configuration than the eight second emitter connections.

[0011] According to one or more embodiments of the present invention, the 3×3 array of the ΔVbe cells has approximately 295 μm. 2 The area.

[0012] According to one or more embodiments of the present invention, the single first emitter connection at the center of the array is separated from the peripheral emitters of the eight (8) second emitter connections by a distance of approximately 4.3 μm.

[0013] According to one or more embodiments of the present invention, the transistors of the plurality of ΔVbe units include only NPN transistors.

[0014] According to one or more embodiments of the present invention, the bandgap voltage reference circuit further includes an NPN transistor having: an emitter coupled to a portion of the electrical path between the base of the series-connected distal multi-emitter emitters and the eight emitters of the preceding emitter emitter; and a collector driving an NMOS transistor arrangement to control the gate current of the output transistor of the bandgap voltage reference circuit.

[0015] According to one or more embodiments of the present invention, the bandgap voltage reference circuit further includes:

[0016] A first current source is coupled to a plurality of PMOS transistors and provides a first current, each PMOS transistor having a source coupled to the collector of a ΔVbe unit transistor.

[0017] A second current source, coupled to the electrical path and providing a second current; and

[0018] A third current source is used to provide a current difference to the base of the multi-emitter transistor.

[0019] According to one or more embodiments of the present invention, the bandgap voltage reference circuit further includes a resistor divider coupled to the base of each transistor.

[0020] According to one or more embodiments of the present invention, the output voltage Vbg is determined by the following equation:

[0021]

[0022] Where n is ΔV be The number of units.

[0023] According to another aspect of the present invention, a battery management system is provided, comprising: a bandgap voltage reference circuit according to any one of claims 1 to 9.

[0024] According to one or more embodiments of the present invention, the ΔVbe cells in the plurality of ΔVbe cells are constructed and arranged in a 3×3 array, wherein the single first emitter is connected to the center of the array and is surrounded by the eight (8) second emitters connected together.

[0025] According to one or more embodiments of the present invention, the transistors of the plurality of ΔVbe units are only NPN transistors.

[0026] According to one or more embodiments of the present invention, the battery management system further includes an NPN transistor having: an emitter coupled to a portion of the electrical path between the base of the series-arranged distal multi-emitter emitters and the eight emitters of the preceding emitter emitter; and a collector driving an NMOS transistor arrangement to control the gate current of the output transistor of the bandgap voltage reference circuit.

[0027] According to one or more embodiments of the present invention, the battery management system further includes:

[0028] A first current source is coupled to a plurality of PMOS transistors and provides a first current, each PMOS transistor having a source coupled to the collector of a ΔVbe unit transistor.

[0029] A second current source, coupled to the electrical path and providing a second current; and

[0030] A third current source is used to provide a current difference to the base of the multi-emitter transistor.

[0031] According to one or more embodiments of the present invention, the battery management system further includes a resistive voltage divider coupled to the base of each transistor. Attached Figure Description

[0032] This invention is illustrated by way of example and is not limited to the accompanying drawings, in which similar reference numerals indicate similar elements. Elements in the figures are shown for simplicity and clarity, and these elements are not necessarily drawn to scale.

[0033] Figure 1 This is a schematic diagram of a traditional reference circuit.

[0034] Figure 2 yes Figure 1 A diagram showing the surface area layout of the reference circuit.

[0035] Figure 3 This is a schematic diagram of a semiconductor device having a ΔVbe circuit including a plurality of multi-emitter transistors according to an embodiment.

[0036] Figure 4 According to the embodiments Figure 3 A diagram illustrating the surface layout of the ΔVbe cell in a semiconductor device.

[0037] Figure 5 This is a schematic diagram of the layout of a ΔVbe circuit with multiple daisy-chain ΔVbe units according to an embodiment.

[0038] Figure 6 It is constructed and arranged as a bandgap reference voltage circuit according to the embodiment. Figure 5 A schematic circuit diagram of the ΔVbe circuit.

[0039] Figure 7 This is a schematic circuit diagram of a bandgap reference voltage circuit according to another embodiment.

[0040] Figure 8 This is a schematic circuit diagram of a bandgap reference voltage circuit according to another embodiment.

[0041] Figure 9 This is a diagram of a comparative ΔVbe cell layout according to another embodiment. Detailed Implementation

[0042] Embodiments of the present invention solve the above-mentioned problems by providing a semiconductor device with a bandgap reference voltage circuit, wherein the bandgap reference voltage circuit comprises a multi-emitter transistor as a ∑ΔV that accommodates the minimum possible surface area. be This reduces the mechanical stress on the reference voltage as part of the circuit. ΔV be It is the difference between the base-emitter voltages of the differential transistor pair. The output voltage Vbg of the bandgap reference voltage circuit is derived from the sum of the ΔVbe values ​​from multiple cascaded multi-emitter transistors, the number of which can vary depending on the required reference voltage and the ΔVbe value in each transistor.

[0043] like Figure 1 and 2As shown, the conventional ΔVbe circuit 100 uses nine (9) different and independent NPN transistors 102A-102F, 103, each transistor having its own base, emitter, and collector. The transistors can be arranged in a 3×3 array, where eight (8) NPN transistors 102A-102F (totaling as 102), referred to as the first transistor, are connected in parallel, forming an 8:1 ratio relative to the second transistor 103, or configured with 1 and 8 emitter areas. Here, the same current is applied to the junction branches of the first transistor 102. Under mechanical plastic encapsulation stress, each Vbe junction may experience lifetime drift. For example, the maximum distance between emitters is 54.2 μm, therefore the area of ​​the 3×3 array of the conventional 8:1 ΔVbe circuit is 2307 μm. 2 .

[0044] However, in some embodiments, Figure 4 The maximum distance between the emitters of the ΔVbe unit 400 shown is 19.4 μm, and the area of ​​the ΔVbe unit 400 is 295 μm². 2 , or more Figure 2 The area of ​​the ΔVbe circuit shown is 7.8 times smaller, or for example, in the 250-350 μm range. 2 Within a certain range. In some embodiments, the distance between the central emitter 404 and each of the eight peripheral emitters 402 can be 4.3 μm, or within the range of 4.0-5.0 μm. Compared to the area of ​​conventional circuits, the smaller area increases efficiency in a smaller area (e.g., 250-350 μm). 2 This increases the likelihood of achieving equal local mechanical stress on the circuit, thereby increasing the probability that the circuit will achieve a expected lifetime ΔVbe value of 0 or other minimum values. Additionally, the diagonal distance between the centers of the center emitter 404 and the corner emitter 402 can be divided by 2.6. If the gradient of the isostress lines is linear over this small distance, the stress on circuit 300 can be three times less than that on conventional circuit 100, and the lifetime drift can also be three times less.

[0045] More specifically, to achieve minimal lifetime drift with respect to ΔVbe caused by mechanical packaging stress, an 8:1 emitter-to-emitter ratio occupies the minimum surface area, thereby achieving minimal incremental stress between each emitter. The solution is to apply... Figure 3-4 The topology shown is in which the nine emitters of a single NPN transistor 400 are constructed and arranged such that eight emitters are positioned around one emitter. The transistor 400 may have a single base and collector and nine (9) emitters, including a first emitter 511 (referred to as emitter 8) and a second emitter 512 (referred to as emitter 1).

[0046] like Figure 3As shown, this topology is applied to form the ∑ΔVbe circuit 300. Circuit 300 includes a stack of multi-emitter transistors 410. Each transistor 410 is... Figure 4 A portion of the ΔVbe cell 400 is shown. Transistor 410 may be a bipolar NPN transistor, but is not limited thereto. In some embodiments, the emitter 410 of the ΔVbe cell is an NPN transistor, either exclusively or specifically. Each transistor 410 may have nine (9) emitters sharing a common base and collector. Here, the emitters are constructed and arranged in an 8:1 ratio, comprising a plurality of first emitters 402, also referred to as an emitter 8 configuration or emitter 1 configuration positioned around a single central emitter 404 (referred to as a second emitter 404). As described above, the maximum distance between two emitters in the first emitters 402 is 19.4 μm, but is not limited thereto. The nine emitters of the ΔVbe cell 400 occupy an area of ​​295 μm². 2 However, it is not limited to this. In some embodiments, the area can be 250 μm. 2 With 350μm 2 between.

[0047] Figure 5 It is according to the embodiment having Figure 4 A schematic diagram of the layout of a ΔVbe circuit 500 comprising multiple daisy-chain ΔVbe units 400. In a preferred embodiment, the emitter 1 of a ΔVbe unit (e.g., ΔVbe unit 400A) may be coupled to the emitter 8 of an adjacent ΔVbe unit (e.g., ΔVbe unit 400B), such that all units 400A-400N (e.g., N=10) in the ΔVbe circuit 500 are electrically connected in a daisy-chain configuration (shown in electrical path 515). However, units 400 may have different emitter sizes (1 and 8) attached in series, as shown. Specifically, unit 400A has an emitter size 8 (611) coupled to emitter size 1 (612) of unit 400B. Thus, each emitter from one unit 400 is attached to an adjacent unit 400.

[0048] Figure 6 yes Figure 5 A schematic circuit diagram of a ΔVbe circuit 500, which is constructed and arranged as a bandgap reference circuit 600, specifically a bandgap reference voltage circuit.

[0049] The common emitter assemblies (size 1 (611) and size 8 (612)) are equipped with current sources 620. The transistors 410A-410N (overall 410) are connected in a manner similar to back-to-back diodes, where the collector 613 and base 614 can be short-circuited. A first current source 620 can be coupled to the collector 613, and a second current source 621 can be coupled to the emitter 1 611 of each multi-emitter transistor 410. Therefore, in Figure 6 In the bandgap reference voltage circuit 600, the top and bottom currents (I) are equal or nearly equal.

[0050] The chain of transistors 410 extending between voltage rails 601 and 602 generates a bandgap reference voltage Vbg, which is the base-emitter voltage V of transistor 410. be The sum is because the emitter 1 611 of each transistor in the chain is coupled to the emitter 8 612 of the next transistor 410. The bandgap reference voltage Vbg or output voltage of the bandgap reference voltage circuit is the Vbe voltage from ground (see...). Figure 5-8 The sum of the voltages of the emitter 1 611 and the voltage of the emitter 8 612 in each of the 10 cells 400 is the sum of the voltages of the emitter 1 611 (Vbe1) and the voltage of the emitter 8 612 (Vbe8) in each of the 10 cells 400.

[0051] The last or furthest ΔVbe cell (400N, where N is 10 in this example) in the chain has the same configuration as the first ΔVbe cell (410A), with the addition of an NPN transistor 632 connected to the base of the last multi-emitter emitter 410N. The collector of the last multi-emitter emitter 410N drives an arrangement of NMOS transistors 640, 643, 653, which controls the base current of the output NPN bipolar transistor 652. Using this topology, the bandgap value is specifically the sum and difference of the NPN Vbe from the NPN bipolar transistor 651 to the top of the main resistor 618. In some embodiments, the bandgap voltage value (e.g., as shown in the figure) is... Figure 5-7 (Shown) is the base voltage (Vbe) between the bottom voltage rails of the NPN bipolar transistor 651 coupled to the main resistor 618, added to the sum of the voltages of the ΔVbe cells 400. In some embodiments, the sum of the ten (10) ΔVbe cells is equal to or approximately 600 mV at room temperature. This voltage is applied to the sensor contacts of the main resistor 618, with little or no current, or only base current. The voltage drop formed by multiplying the resistor current at the top and bottom resistor contacts of the resistor 618 is possible if the contacts move or change during their lifetime and / or due to mechanical stress. However, the voltage drop is not included in the bandgap voltage equation because the bandgap value is Vbe from ground to the bottom sensing contact of the main resistor 618 plus ∑ΔVbe connected to the top sensing contact of the resistor 618.

[0052] Figure 7 This is a schematic circuit diagram of a bandgap reference voltage circuit 700 according to another embodiment. The components of the bandgap reference voltage circuit 700 are... Figure 4-6 The components shown are similar or identical. For the sake of brevity, details of these similar or identical components are not repeated.

[0053] Figure 6 The bandgap reference voltage circuit 600 and Figure 7 One difference between the bandgap reference voltage circuits 700 and others is that... Figure 6 The bandgap reference voltage circuit 600 describes top source 620 and bottom source 621 that are equal relative to the current source. The base current acts directly on the collector. Therefore, the last stage or output stage, including the last multi-emitter emitter 410N in the chain, includes NMOS transistors 640, 643, which are configured to collect base current Ib from the collector to re-inject into the base of the last stage emitter 410N, ensuring that the top and bottom currents are equal.

[0054] On the other hand, the bandgap reference voltage circuit 700 includes two different current sources 720 and 721. The top current source 720 generates a current (Ip), and the bottom current source 721 generates a current (I), while current source 722 provides current (Ib) to the base of the differential multi-emitter transistor 410. Here, the multi-emitter transistor 510A, connected to the first ΔVbe unit of the bandgap voltage Vbe, has its base coupled to an NPN transistor 531. The emitter of the NPN transistor 531 can be connected in a diode with an NMOS transistor 540, the gate of which is coupled to the collector of the NPN transistor 531, the source of which is coupled to the junction between the base of the NPN transistors 531 and 510A and the top current source 720 controlled by the PMOS transistor 541, and the drain of which is coupled to ground. The current loop formed by the NPN transistor 531 and the NMOS transistor 540 drives the current (Ip) of the top current source 720. An external bias current drives the bottom current (emitter current) so that the top current (Ip) can be equal to the bottom current (I) minus the base current (Ib) formed by the base current source 722 and the follower NMOS transistor 516 coupled between the top current source 720 and the base of the multi-emitter transistor 510. Therefore, the base current (Ib) acts directly on the collector.

[0055] like Figure 7 As shown in circuit 700, the emitter current supplied by current source 520 is equal to that of the other NPN collectors. A bias is formed at current sources 541 (8I) and 561 (9I) because the Vbe of NPN transistor 531 is connected in parallel with emitter 1 of the multi-emitter circuit 520A. The 2I bias provided by current source 520 will bias one I in emitter cell 1 and one I in emitter cell 8 of the circuit.

[0056] To achieve the same voltage (Vbe) across the multi-emitter circuit 520A of the NPN transistor 531, the same current density is set, which means a current I from one emitter and a current 8I from eight emitters, since the NPN transistor 531 has eight emitters. Therefore, the sink current is 9I, which is the current 8I from the eight emitters of the NPN transistor 531 and a current I from a single emitter.

[0057] In doing so, the multi-emitter transistor 510A connected to the first ΔVbe cell of the bandgap voltage Vbe has a base coupled to the NPN transistor 531. The emitter of the NPN transistor 521 is parallel to the emitter size 1 of the ΔVbe cell 510A and is connected in a diode with the NMOS transistor 540, the gate of which is coupled to the collector of the NPN transistor 531, the source of which is coupled to the junction between the base of the BJT 531 and 510A and the current source 541, and the drain of which is coupled to ground.

[0058] The current mirror can be formed by NMOS transistor 540, NPN transistor 531, and emitter size 1 of the first ΔVbe cell 510A. Here, PMOS transistors 541 and 542 replicate the collector current of the first ΔVbe cell 510A to the NPN mirror input, i.e., NMOS transistor 540 and NPN transistor 531. The collector current of the first ΔVbe cell 510A is replicated to the other ΔVbe cells 510. The bases of the other ΔVbe cells 510 are supplied by following NMOS transistor 516, except that the first ΔVbe cell 510A is controlled by NMOS transistor 540 with the assistance of NPN transistor 531, and the last ΔVbe cell 510N is controlled by NMOS transistor 543 with the assistance of NPN transistor 532.

[0059] Another feature involves a buffer that supplies the bandgap voltage of the main resistor. As shown and described, a stack of N (where N = 10 in this example) ΔVbe cells begins at the PN junction of the BJT assembly arrangement 551 connected to ground and extends to the top of the resistor 518, defining the current in the BJT 551 by Equation (Eq.) 1: ∑ΔVbe / R (118).

[0060] The last ΔVbe cell (510N, where N is an integer, e.g., 10) in the chain has the same configuration as the first ΔVbe cell (510A), with the addition of an NPN transistor 532 connected to the NMOS transistor 543. The collector of the last ΔVbe cell (510N) drives the NMOS transistors 552 and 553 to control the gate current of the output NMOS transistor 554 via a mirror formed by the NMOS transistors 555 and 556. Using this topology, the bandgap value is specifically the sum and difference of the NPN Vbe from transistor 551 to the top of the main resistor 518. In some embodiments, the sum of the ten (10) ΔVbe cells is equal to or approximately 600 mV at room temperature. Applying this voltage to the sensor contacts of the main resistor 518 results in little or no current, or only base current. The current is output to the resistor 518 via the source junction of the output NMOS transistor 554 and via the collector of transistor 551. The voltage drop formed by multiplying the resistor current at the top and bottom resistor contacts of resistor 518 may shift or change if the contacts move or change during their lifetime and / or due to mechanical stress. However, the voltage drop is not included in the bandgap voltage equation because the bandgap value is Vbe from ground to the bottom sensing contact of main resistor 518 plus ∑ΔVbe connected to the top sensing contact of resistor 518.

[0061] Figure 8 This is a schematic circuit diagram of a bandgap reference voltage circuit 800 according to another embodiment. The components of the bandgap reference voltage circuit 700 are... Figure 4-7 The components shown are similar or identical. For the sake of brevity, details of these similar or identical components are not repeated.

[0062] In the bandgap reference voltage circuit 800, the base 814 of each multi-emitter transistor 810A-810N (collectively 810) is coupled to a resistor divider 805. An NMOS transistor 815 extends from the junction between the emitter 812 of a transistor in the chain (e.g., 810A) and the emitter 1 811 of an adjacent multi-emitter transistor (e.g., 810B) to a current source coupled to ground. This topology can improve parameters related to bandgap voltage (Vbg) expansion by reducing standard deviations due to manufacturing processes. Therefore, bandgap expansion can be reduced compared to other manufacturing processes.

[0063] As described above, in some embodiments, Figure 3-8 The distance between the central emitter and the eight peripheral emitters of the ΔVbe cell shown and described is 4.3 μm. (As...) Figure 9As shown, this is due to the reduced ratio between ΔVbe cell 900C and other layouts (e.g., ΔVbe cells 900A and 900B). For example, the maximum-minimum bandgap drift shown at ΔVbe cell area 900A is 322 ppm. The distance ratio (D3 / D2) between ΔVbe cell areas 900A and 900B is 1.8, where the bandgap of ΔVbe cell area 900B is reduced, with a maximum-minimum drift of 203 ppm. The lifetime drift of ΔVbe cell 400 can be reduced by a factor of 1.6. However, the distance ratio (D2 / D1) between ΔVbe cell areas 900B and 900C is 2.6, which is at least partly due to the distance (D1) between the central emitter 404 and the peripheral emitter 402 being 4.3 μm, indicating that the ΔVbe cell area provides a preferred result, and cell 400 achieves a further minimum feasible ΔVbe result.

[0064] therefore, Figure 9 This demonstrates the measurable effect of minimizing the ΔVbe area to minimize incremental mechanical stress between each emitter based on area size. This feature is useful in many applications requiring high precision (e.g., fine-tuning operations around 0.05%), such as battery management system (BMS) applications. By reducing parameter variations, the reference voltage is required to remain within + / -0.1% over the circuit lifetime. This can be achieved by reducing the ΔVbe cell area to reduce incremental mechanical stress, which in turn reduces the circuit's bandgap lifetime drift.

[0065] As mentioned above, the bandgap structure of the circuit consumes the minimum possible ΔVbe circuit area. In some embodiments, the ΔVbe voltage is 60mV or approximately 600mV compared to 600mV at the PN junction. Therefore, the sensitivity of ΔVbe to Vbe variations is increased by a factor of 10. The ΔVbe circuit 400 described herein provides the difference between these Vbe values. If the Vbe variation is due to mechanical packaging stress, the two PN junctions must have the same stress, which can be achieved by the minimum silicon area consumed by the bandgap reference circuit.

[0066] As will be understood, the disclosed embodiments may include at least the following embodiments. In one embodiment, a bandgap voltage reference circuit may include a plurality of incremental base-emitter voltage (ΔVbe) units arranged in series extending between a first voltage rail and a second voltage rail. Each ΔVbe unit may include a transistor including a single first emitter connection and eight second emitter connections. The single first emitter connection of a second transistor in the series arrangement may be coupled to one of the eight second emitter connections (611) of a first transistor in the series arrangement, and one of the eight second emitter connections of the second transistor may be coupled to the single first emitter connection of a third transistor in the series arrangement to form an electrical path from the first transistor to the third transistor. A resistor is located at the distal end of the series arrangement. The output voltage across the resistor includes the sum of the incremental base-emitter voltages generated by the plurality of ΔVbe units.

[0067] Alternative embodiments of the bandgap voltage reference circuit may include one or any combination of the following features.

[0068] The ΔVbe cells in the plurality of ΔVbe cells may be constructed and arranged in a 3×3 array, wherein a single first emitter is connected to the center of the array and surrounded by eight second emitter connections, and wherein the single first emitter connection has a different size or other configuration than the eight second emitter connections.

[0069] The 3×3 array of the ΔVbe unit can have approximately 295 μm. 2 The area.

[0070] The single first emitter connection at the center of the array is separated from the peripheral emitters of the eight (8) second emitter connections by a distance of approximately 4.3 μm.

[0071] The transistors of the plurality of ΔVbe units may be NPN transistors and / or may include only NPN transistors.

[0072] The bandgap voltage reference circuit may further include an NPN transistor having: an emitter coupled to a portion of the electrical path between the base of the series-connected distal multi-emitter emitters and the eight emitters of the preceding emitter emitter; and a collector driving an NMOS transistor arrangement to control the gate current of the output transistor of the bandgap voltage reference circuit.

[0073] The bandgap voltage reference circuit may further include: a first current source coupled to a plurality of PMOS transistors and providing a first current, each PMOS transistor having a source coupled to the collector of a ΔVbe unit transistor; a second current source coupled to the electrical path and providing a second current; and a third current source for providing a current difference to the base of the multi-emitter transistor.

[0074] The bandgap voltage reference circuit may additionally include a resistor divider coupled to the base of each transistor.

[0075] The output voltage Vbg can be determined by the following equation:

[0076]

[0077] Where n is ΔV be The number of units.

[0078] The output voltage Vbg can be determined by the following equation:

[0079]

[0080] Where n is ΔV be The number of units.

[0081] In another embodiment, a battery management system may include a bandgap voltage reference circuit, which may include a plurality of incremental base-emitter voltage (ΔVbe) units arranged in series extending between a first voltage rail and a second voltage rail, wherein each ΔVbe unit includes a transistor comprising: a single first emitter connection and eight (8) second emitter connections; wherein the single first emitter connection of the second transistor in the series arrangement may be coupled to one of the eight second emitter connections of the first transistor in the series arrangement, and one of the eight second emitter connections of the second transistor may be coupled to the single first emitter connection of the third transistor in the series arrangement to form an electrical path from the first transistor to the third transistor; and a resistor at the distal end of the series arrangement, wherein the output voltage across the resistor may include the sum of the incremental base-emitter voltages generated by the plurality of ΔVbe units.

[0082] Alternative embodiments of the battery management system may include one or any combination of the following features.

[0083] The ΔVbe cells in the plurality of ΔVbe cells can be constructed and arranged in a 3×3 array, wherein the single first emitter is connected to the center of the array and surrounded by the eight (8) second emitters connected together.

[0084] The 3×3 array of the ΔVbe unit can have approximately 295 μm. 2 The area.

[0085] The single first emitter connection at the center of the array is separated from the peripheral emitters of the eight (8) second emitter connections by a distance of approximately 4.3 μm.

[0086] The transistors of the plurality of ΔVbe units may be NPN transistors, specifically NPN transistors.

[0087] The battery management system may further include an NPN transistor having: an emitter coupled to a portion of the electrical path between the base of the series-connected distal multi-emitter emitters and the eight emitters of the preceding emitter emitter; and a collector driving an NMOS transistor arrangement to control the gate current of the output transistor of the bandgap voltage reference circuit.

[0088] The battery management system may further include: a first current source coupled to a plurality of PMOS transistors and providing a first current, each PMOS transistor having a source coupled to the collector of a ΔVbe unit transistor; a second current source coupled to the electrical path and providing a second current; and a third current source for providing a current difference to the base of the multi-emitter transistor.

[0089] The battery management system may additionally include a resistor divider coupled to the base of each transistor.

[0090] In another embodiment, an incremental base-emitter voltage (ΔVbe) unit of a bandgap reference circuit may include a single first emitter connection and eight (8) second emitter connections, the ΔVbe units being constructed and arranged in a 3×3 array, the single first emitter connection being at the center of the array and surrounded by the eight (8) second emitter connections, and wherein the single first emitter connection may be constructed and arranged in series with the second emitter connections of adjacent ΔVbe units to form an electrical path with the adjacent ΔVbe units.

[0091] Alternative embodiments of the ΔVbe unit may include one or any combination of the following features.

[0092] The ΔVbe unit may further include an NPN transistor, which includes a de facto first emitter connection and a second emitter connection.

[0093] The 3×3 array of the ΔVbe unit can have approximately 295 μm. 2 The area of ​​the array, and the single first emitter connection at the center of the array is separated from the peripheral emitters of the eight (8) second emitter connections by a distance of approximately 4.3 μm.

[0094] While the invention has been described herein with reference to specific embodiments, various modifications and changes may be made without departing from the scope of the invention as set forth in the appended claims. For example, while specific voltage levels, sizes, and configurations are shown and described in various embodiments of the ΔVbe unit, other suitable voltage levels, sizes, and configurations may be used. Therefore, the specification and drawings should be considered illustrative and not restrictive, and all such modifications are intended to be included within the scope of the invention. It is not intended that any benefit, advantage, or solution to the problem described herein with respect to specific embodiments be construed as a key, necessary, or essential feature or element of any or all claims.

[0095] Unless otherwise stated, terms such as “first” and “second” are used to arbitrarily distinguish the elements described by these terms. Therefore, these terms are not necessarily intended to indicate the temporal or other priority order of such elements.

Claims

1. A bandgap voltage reference circuit, characterized in that, include: Multiple incremental base-emitter voltage ΔVbe units arranged in series extending between a first voltage rail and a second voltage rail, wherein each ΔVbe unit includes a transistor comprising: A single first emitter connection; and Eight second emitter connections; The single first emitter connection of the second transistor in the series arrangement is coupled to one of the eight second emitter connections of the first transistor in the series arrangement, and one of the eight second emitter connections of the second transistor is coupled to the single first emitter connection of the third transistor in the series arrangement to form an electrical path from the first transistor to the third transistor. The ΔVbe cells in the plurality of ΔVbe cells are constructed and arranged in a 3×3 array, the single first emitter is connected to the center of the array and surrounded by the eight second emitter connections, and the single first emitter connection has a different size or other configuration than the eight second emitter connections; A resistor, wherein the first end of the resistor is located at the far end of the series arrangement, and wherein the output voltage across the resistor comprises the sum of the incremental base-emitter voltages generated by the plurality of ΔVbe units; A bipolar transistor, the bipolar transistor being coupled to the second voltage rail and the second end of the resistor.

2. The bandgap voltage reference circuit according to claim 1, characterized in that, The 3×3 array of the ΔVbe unit has approximately 295 μm. 2 The area.

3. The bandgap voltage reference circuit according to claim 1 or 2, characterized in that, The single first emitter connection at the center of the array is separated from the peripheral emitters connected to the eight second emitters by a distance of approximately 4.3 μm.

4. The bandgap voltage reference circuit according to claim 1 or 2, characterized in that, The transistors of the plurality of ΔVbe units include only NPN transistors.

5. The bandgap voltage reference circuit according to claim 1 or 2, characterized in that, Additionally, an NPN transistor is included, the NPN transistor having: an emitter coupled to a portion of the electrical path between the base of a series-arranged distal multi-emitter transistor and the eight emitters of a preceding emitter transistor; and a collector driving an NMOS transistor arrangement to control the gate current of the output transistor of the bandgap voltage reference circuit.

6. The bandgap voltage reference circuit according to claim 1 or 2, characterized in that, In addition, including: A first current source is coupled to a plurality of PMOS transistors and provides a first current, each PMOS transistor having a source coupled to the collector of a ΔVbe unit transistor. A second current source is coupled to the electrical path and provides a second current. as well as A third current source is used to provide a current difference to the base of the multi-emitter transistor.

7. The bandgap voltage reference circuit according to claim 1 or 2, characterized in that, In addition, including: A resistor divider coupled to the base of each transistor.

8. The bandgap voltage reference circuit according to claim 1 or 2, characterized in that, The output voltage Vbg is determined by the following equation: Where n is ΔV be Number of units; V be1 It is the voltage of the emitter of each cell.

9. A battery management system, characterized in that, include: The bandgap voltage reference circuit according to any one of claims 1 to 8.

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