Access request processing method, multi-core processor system, chip and electronic device

Abstract

Embodiments of the present application provide a kind of access request processing method, multi-core processor system, chip and electronic equipment, the method is applied to home agent, comprising: the sending frequency of detecting return consistency invalid;When it is higher than the preset frequency threshold, target data is acquired for the target address of the data access request of processor core;The consistency state of target cache line corresponding to target address is recorded in the target entry of consistency directory;The identification of carrying temporary storage state is set in the response packet of data access request, and feedback is given to processor core;Identification is used for processor core to load target data in the target cache line in non-end cache, and end cache is set temporary storage state for target cache line, so that when non-end cache eliminates target cache line, target cache line is directly written back to memory without passing through end cache;The write-back request of target cache line is acquired, and target entry is released.The technical scheme provided in the embodiments of the present application can improve the performance of multi-core processor system.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to an access request processing method, a multi-core processor system, a chip, and an electronic device. Background Technology

[0002] In modern computer architectures, processor cores can improve data access efficiency through caching. A cache stores data in units of cache lines, temporarily storing data previously accessed by the processor core or frequently accessed data in memory.

[0003] In a multi-core processor system architecture, each processor core has a cache. In this case, a cache line at the same address may be mapped to the caches of multiple processor cores. If one processor core modifies the data in the cache line, it may cause inconsistencies in the corresponding cache lines in other processor cores, resulting in a cache inconsistency problem.

[0004] To ensure cache consistency, a cache coherence protocol can be used to manage the consistency status of cache lines. Under a cache coherence protocol, the consistency directory can use entries to record the consistency status of cache lines. However, the number of entries in the consistency directory is limited. Therefore, how to provide technical solutions to improve the performance of the consistency directory, and thus improve the performance of multi-core processor systems, has become a technical problem that urgently needs to be solved by those skilled in the art. Summary of the Invention

[0005] The technical problem addressed by the embodiments of this application is how to improve the performance of using the consistency catalog, thereby improving the performance of multi-core processor systems.

[0006] To address the aforementioned issues, embodiments of this application provide an access request processing method, a multi-core processor system, a chip, and an electronic device.

[0007] In a first aspect, embodiments of this application provide an access request processing method, applied to a home agent, comprising:

[0008] The frequency at which invalid transmissions are detected and returned is checked;

[0009] When the frequency of sending invalid return values ​​is higher than a preset frequency threshold, for the data access request issued by the processor core, the target data is obtained according to the target address indicated by the data access request; wherein, the consistency status of the target cache line corresponding to the target address is recorded in the target entry of the consistency directory;

[0010] In addition, an identifier carrying a temporary storage status is set in the response packet corresponding to the data access request, and the response packet is fed back to the processor core; the identifier is used to enable the processor core to load the target data in the target cache line in the non-last-level cache, and set a temporary storage status for the target cache line in the last-level cache, so that when the non-last-level cache removes the target cache line, the target cache line is written back to memory directly without going through the last-level cache.

[0011] Obtain the write-back request for the target cache line and release the target entry in the consistency directory.

[0012] Secondly, embodiments of this application provide an access request processing method applied to a processor core, comprising:

[0013] Send a data access request to the home agent;

[0014] Obtain the target data and response packet corresponding to the data access request;

[0015] If the response packet contains an identifier carrying a temporary state, the target data is loaded into the target cache line (not in the last-level cache), and the temporary state of the target cache line is saved in the last-level cache. When the frequency of the home agent sending invalid return values ​​exceeds a preset frequency threshold, the home agent sets the identifier in the response packet for the data access request. The temporary state indicates that when the target cache line is removed from the processor core's cache, it is written directly back to memory without going through the last-level cache.

[0016] When the target cache line is removed from the cache, a write-back request for the target cache line is sent. The write-back request is used to remove the target cache line from memory and instruct the home agent to release the target entry corresponding to the target cache line in the consistency directory.

[0017] Thirdly, embodiments of this application also provide a multi-core processor system, including:

[0018] A proxy is used to detect the frequency of sending messages that return inconsistency invalidity. When the frequency of sending messages that return inconsistency invalidity is higher than a preset frequency threshold, the proxy retrieves the target data according to the target address indicated by the data access request for the processor core. The consistency status of the target cache line corresponding to the target address is recorded in the target entry of the consistency directory. The proxy also sets an identifier carrying the temporary storage status in the response packet corresponding to the data access request and feeds the response packet back to the processor core. The proxy retrieves the write-back request for the target cache line and releases the target entry in the consistency directory.

[0019] The processor core is used to send a data access request to the home agent; obtain the target data and response packet corresponding to the data access request; if the response packet is set with an identifier carrying a temporary state, load the target data into the target cache line in the non-last-level cache, and save the temporary state of the target cache line in the last-level cache; wherein, the temporary state is used to indicate that when the target cache line is removed from the processor core's cache, it is written back to memory directly without going through the last-level cache; when the target cache line is removed from the cache, a write-back request for the target cache line is sent.

[0020] Fourthly, embodiments of this application also provide a chip, including the multi-core processor system described in the third aspect.

[0021] Fifthly, embodiments of this application also provide an electronic device, including the chip described in the fourth aspect.

[0022] It should be noted that when the home agent processes a data access request from a processor core, it can query the consistency status of the cache line corresponding to the address indicated by the data access request in the connected consistency catalog. If the consistency status of the cache line corresponding to the address is not recorded in the consistency catalog, it means that the data requested by the data access request is not recorded in the cache of the multi-core processor, but in memory, and the data requested by the data access request needs to be read from memory. At this time, for the data read from memory, the cache line corresponding to the address of the data is a new cache line, and the home agent needs to record the consistency status of the new cache line in the consistency catalog. If the consistency catalog has no available entries to record the consistency status of the new cache line, the home agent needs to release an already used entry in the consistency catalog, obtain a usable entry, and return a consistency invalidation to the processor core to notify the processor core to remove the cache line corresponding to the already used entry from the cache to memory. It is evident that for data access requests with a low hit rate in the cache of a multi-core processor, the home agent will frequently return inconsistency invalidation to the processor core. This forces the home agent to wait for the processor core to remove the cache line from the cache of the released used entries before it can record the consistency status of the new cache line in the available entries of the consistency catalog. This reduces the overall data access request processing efficiency of the multi-core processor system and affects the performance of the multi-core processor system.

[0023] Based on this, in the access request processing method provided in this application embodiment, the home agent can detect the sending frequency of returning inconsistency invalidity; when the sending frequency of returning inconsistency invalidity is higher than a preset frequency threshold, it indicates that the occupied entries in the consistency catalog are frequently released, and the data in the processor core's cache is frequently written back to memory; at this time, in order to prevent the consistency catalog from frequently returning inconsistency invalidity to the processor core, and to increase the time for the processor core to remove the cache lines released in the consistency catalog from the cache to memory, for the data access request issued by the processor core, in addition to obtaining the target data according to the target address indicated by the data access request, the home agent also needs to set an identifier carrying a temporary storage status in the response packet corresponding to the data access request, and feed the response packet back to the processor core; the identifier is used to enable the processor core to load the target data in the target cache line in the non-last-level cache, and set a temporary storage status for the target cache line in the last-level cache, so that when the non-last-level cache removes the target cache line, the target cache line is directly written back to memory without going through the last-level cache. In other words, based on the identifier carrying the temporary storage status set in the response packet, when the target cache line is temporarily stored in the processor core's cache, the target data is loaded into the processor core's non-last-level cache. Furthermore, when the target cache line is evicted from the cache, it is directly evicted from the processor core's non-last-level cache into memory without going through the processor core's last-level cache. This saves the time spent waiting for the processor core to evict the target cache line from the non-last-level cache to the last-level cache, and then from the last-level cache into memory, thus improving the overall access request processing efficiency of the processor core. Furthermore, when the home agent obtains the write-back request for the target cache line, it can release the target entry in the consistency directory; wherein, the consistency status of the target cache line corresponding to the target address is recorded in the target entry in the consistency directory.

[0024] As can be seen, the access request processing method provided in this application detects the sending frequency of the consistency directory's feedback return of invalid consistency. When the sending frequency reaches a frequency threshold, it can be determined that the consistency directory has frequently issued returns of invalid consistency. To avoid the low processing efficiency of multi-core processor systems caused by returns of invalid consistency, this application sets an identifier carrying a temporary storage status in the response packet of the data access request for the processor core by the home agent. Based on the identifier, the processor core can load the target data into the target cache line in the non-last-level cache; and set a temporary storage status for the target cache line in the last-level cache, so that when the target cache line is evicted from the non-last-level cache, the target cache line is written back to memory directly without going through the last-level cache. This saves time for the processor core to evict the corresponding target cache line, eliminating the need for the home agent to wait for the processor core to remove the target cache line from the cache to memory. Simultaneously, since the processor core sends the write-back request for the target cache line to the home agent based on the temporary state identifier, and then directly writes it back to memory, the home agent can find the target entry containing the target cache line in the consistency catalog. The home agent can then release the target cache line from the target entry based on the received write-back request, i.e., write the target cache line back to memory. This achieves the goal of pre-releasing used entries in the consistency catalog, improving the performance of the consistency catalog and thus enhancing the performance of the multi-core processor system. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0026] Figure 1 An example block diagram of a multi-core processor system is shown as an example.

[0027] Figure 2 An exemplary flowchart is shown for a home agent processing data access requests.

[0028] Figure 3 This is a flowchart illustrating the access request processing method provided in the embodiments of this application.

[0029] Figure 4 This is another flowchart illustrating the access request processing method provided in the embodiments of this application.

[0030] Figure 5 This is another flowchart illustrating the access request processing method provided in the embodiments of this application. Detailed Implementation

[0031] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0032] In modern computer architectures, when a processor core accesses data, it can first read the data from its own cache. If the data is temporarily stored in the cache due to previous data access requests by the processor core, the core can read the data directly from the cache without needing to access main memory or the cache of other processor cores, thus improving the processor core's data access efficiency. In other words, the cache acts as a temporary storage between the processor core and main memory, temporarily storing data that the processor core has previously accessed or frequently accessed, thereby improving data access efficiency. It should be noted that if the processor core cannot find the required data in its own cache, it can read the data from main memory or other processor cores and then move the read data into its cache.

[0033] With the continuous development of multi-core technology, chips can now incorporate multi-core processor systems with multiple processor cores, each with its own cache. For ease of understanding, Figure 1 An example block diagram of a multi-core processor system is shown as an example.

[0034] As shown in the figure, the multi-core processor system includes multiple core clusters 10, an on-chip network 11, multiple memory controllers 12, and corresponding multiple DDR (Double Data Rate) memory modules 13, input / output interfaces (IO) 14, etc. Each core cluster includes a processor core and multiple levels of cache, such as L1, L2, and Last Level Cache (LLC). The technical solution described in this application mainly addresses the process of saving cache lines invalidated by the processor core according to the consistency catalog by removing the corresponding cache lines from the cache into memory. The input / output interface 14 is a bus interface for various input / output devices 15, such as Peripheral Component Interconnect (PCI), Peripheral Component Interconnect Express (PCIE), Universal Serial Bus (USB), etc. The multiple memory controllers 12 are used to control access to the corresponding memory modules 13. The on-chip network 11 is used to connect other components in the system.

[0035] The on-chip network 11 includes multiple core request ports 110 and multiple home agents 111. Devices in the on-chip network 11 are connected via a routing network within the on-chip network. Each core request port 110 connects to a core cluster 10, such as... Figure 1 As shown, the number of kernel request ports 110 corresponds to the number of kernel clusters 10. A home agent connects to a memory controller and a coherence directory 112, similarly... Figure 1 As shown, the number of home agents 111, memory controllers 12, and consistency directories 112 are the same.

[0036] Whenever a processor core in a kernel cluster has a data access request, if the processor core in the kernel cluster cannot find the data in its own cache, it can issue a data access request to the connected kernel request port to access memory or the cache of another processor core. The kernel request port can then send the data access request to a home agent. The home agent, based on the address indicated in the data access request, queries the consistency directory for the consistency status of the cache line corresponding to that address. The consistency directory may record the consistency status of the cache line corresponding to the address, indicating that the data required by the processor core that issued the data access request exists on other processor cores. In this case, the required data can be obtained from the corresponding other processor core based on the consistency status of the cache line recorded in the consistency directory entry. The consistency directory may not record the consistency status of the cache line corresponding to the address, indicating that the required data is not stored in the caches of any processor core in the kernel cluster. In this case, the required data needs to be obtained from memory. It should be noted that a cache line can correspond to an address in memory, and a cache line can be mapped to the caches of multiple processor cores, thus a cache line can have multiple copies in multiple kernel clusters. The consistency state of a cache line refers to the overall state of the cache line across its replicas in multiple kernel clusters; and the consistency state of the cache line is recorded in the consistency catalog.

[0037] The consistency directory can be used to track information such as the consistency status of cache lines corresponding to the memory addresses it is connected to. For example, if the address range of the first memory is [0-7] and the address range of the second memory is [8-15], then the consistency directory connected to the first memory will track cache lines in the address range [0-7] (these cache lines already exist in one or more kernel clusters), and the consistency directory connected to the second memory will track cache lines in the address range [8-15].

[0038] To better understand how the home agent handles data access requests, please refer to [link / reference]. Figure 2 , Figure 2 An exemplary flowchart is shown for a home agent processing data access requests.

[0039] As shown in the figure, the process may include the following steps:

[0040] Step S001: Receive a data access request from the processor core.

[0041] It should be noted that the data access request is routed to the home proxy when the data is not found in the processor core's cache. Specifically, the request is sent from the processor core to the kernel request port, and then via the on-chip network to the home proxy.

[0042] Step S002: Query whether the entries in the consistency catalog record the consistency status of the target cache line. If not, proceed to step S003; if yes, proceed to step S008.

[0043] It is easy to understand that the target cache line is the target cache line corresponding to the target address indicated by the target cache behavior data access request.

[0044] As described above, the consistency directory tracks the consistency status of cache lines corresponding to the addresses of the memory cores it is associated with. For example, if a processor core issues a data access request with a target address of [0-7], the memory core associated with that address is the aforementioned first memory. The entries in the consistency directory track the consistency status of the target cache line corresponding to the memory address of the first memory core. Therefore, when the home agent receives a data access request from a processor core, it first determines whether the consistency status of the target cache line corresponding to the target address is recorded in the consistency directory entry. If it is recorded in the consistency directory entry, it means that the target data (the target data being the data at the target address indicated by the data access request) is stored in the cache of another processor core. In this case, the target data is retrieved from the cache of the corresponding processor core based on the consistency status recorded in the consistency directory entry.

[0045] If the target data is not recorded in the consistency directory, it means that other processor cores also do not store the target data. Since the consistency status of cache lines tracked by the consistency directory corresponds one-to-one with the cache lines corresponding to the addresses of the memory associated with them, the consistency directory to be accessed can be determined based on the target address, and then the memory associated with the consistency directory can be accessed to obtain the target data.

[0046] For ease of explanation, the address indicated by the data access request is referred to as the target address, which can be the memory address of the data to be accessed; the cache line corresponding to the target address is called the target cache line. Based on the target address indicated by the data access request, the home agent searches the consistency directory corresponding to it. If the consistency status of the target cache line corresponding to the target address is not recorded in the consistency directory entry, it means that the caches in other kernel clusters also do not store the data corresponding to the target address. In this case, the data at the target address needs to be read from memory and moved to the processor core's cache. Therefore, for the target cache line corresponding to the target address, the consistency directory needs to determine the current position of the target cache line, and thus the consistency directory needs to determine whether there is a usable entry in the consistency directory to record the consistency status of the target cache line. If the consistency status of the target cache line is recorded in the consistency directory entry, it means that the data corresponding to the target cache line is stored in the caches of other kernel clusters. The processor core that issued the data access request can retrieve the target data from the corresponding processor core based on the consistency status of the target cache line recorded in the consistency directory.

[0047] Step S003: Determine whether there are any usable entries in the consistency directory. If not, proceed to step S004; if yes, proceed to step S007.

[0048] If no entry exists in the consistency directory to record the target cache line, it means that the target data required by the data access request needs to be retrieved from memory. Based on the consistency protocol followed by multi-core processor systems for accessing data, after the home agent retrieves the target data from memory, it records the target cache line corresponding to the target address in the consistency directory, enabling the multi-core processor system to function normally. Therefore, it is necessary to further determine whether there are usable entries in the consistency directory to record the consistency status of the target cache line.

[0049] Step S004: Invalidate the cached lines in the used entries in the consistency catalog to obtain usable entries, and send a return message of consistency invalidation to the processor core.

[0050] If there are no usable entries in the consistency catalog, the used entries are invalidated, that is, the cached lines recorded in the entry are invalidated, and a consistency invalidation is returned to the processor core.

[0051] After receiving a return indicating invalidity, the processor core removes the invalidated cache lines from the consistency catalog and sends a write-back signal to the home agent to write the invalidated cache lines back to memory.

[0052] Step S005: Receive a write-back signal from the processor core. The write-back signal is used to instruct the processor core to remove the cache line that has been invalidated in the consistency catalog stored in the cache to memory, and to allocate the usable entry for the target cache line.

[0053] The consistency catalog tracks the consistency status of cache lines corresponding to their associated memory addresses. When a cache line in a used entry is invalidated in the consistency catalog, the invalidated cache line stored in the processor core's cache needs to be synchronously removed or invalidated to maintain the consistency status of the cache line. After the home agent receives the processor core's notification that the invalidated cache line has been removed from memory or invalidated, it can allocate a free, usable entry for the target cache line.

[0054] Step S006: Based on the consistency status of the target cache line, retrieve the data of the data access request from memory.

[0055] Once the agent receives the cache line write-back signal from the processor core and allocates a usable entry that can record the consistency state for the target cache line, it can then execute the data access request normally, retrieve the corresponding target data from memory according to the target address, and complete the processing of the data access request.

[0056] Step S007: Assign the available entries to the target cache line.

[0057] If a usable entry exists in the consistency directory, the cache line corresponding to the address of the data in the data access request, i.e., the target cache line, can be allocated directly. Then, proceed to step S006 to retrieve the data of the data access request from memory based on the consistency status of the target cache line.

[0058] Step S008: Based on the consistency status of the target cache line, retrieve the data of the data access request from the cache of other processor cores.

[0059] Since the consistency status of the target cache line is already recorded in the consistency catalog, it means that the data access request data is stored in the cache of other processor cores. The data can be retrieved directly from the corresponding cache line of other processor cores based on the consistency status of the target cache line.

[0060] As can be seen, when a usable entry exists in the consistency directory, the usable entry is directly assigned to the target cache line to record and track the consistency status of the target cache line, mainly to record the consistency status of the target cache line corresponding to the target address.

[0061] The consistency directory needs to cover as much of the cache as possible, but an excessively large consistency directory will affect the overall chip area. Therefore, the chip area occupied by the consistency directory needs to be considered to meet the usage requirements. The consistency directory has a size limit, and the corresponding record space is also limited. Therefore, when encountering specific data access requests, such as those with many index conflicts, sparse memory accesses, or poor spatial locality, the cache hit rate of data access requests will be low. This will lead to frequent access to data in memory, requiring the consistency directory to have sufficient space to record the consistency status of cache lines corresponding to newly retrieved data from memory. Therefore, in order to have free, usable entries to record the consistency status of new cache lines, the consistency directory will frequently invalidate cache lines recorded in already used entries, resulting in a decrease in overall system performance.

[0062] To solve the above problems, the common approach is to avoid using the consistency directory. This approach wastes resources that could otherwise be used in the consistency directory, thereby reducing the overall performance of the system.

[0063] To address the problems encountered during the use of the consistency directory, this application provides an access request processing method to optimize the consistency directory's operation and improve overall system performance. For details, please refer to... Figure 3 , Figure 3 This is a flowchart illustrating the access request processing method provided in the embodiments of this application.

[0064] Based on the foregoing description, it can be understood that when a multi-core processor system processes a data access request, if the required data is not found in the cache inside the processor core, the processor core sends a data access request to the home agent. The home agent then processes the data access request and returns the processing result, i.e., the response packet, to the processor core. Therefore, in order to facilitate the explanation of the implementation process of the technical solution described in this application, the processing process of the home agent will be discussed first.

[0065] like Figure 3 As shown, the process of handling a home agent may include the following steps:

[0066] Step S100: The home agent detects and returns a transmission frequency that is inconsistent and invalid.

[0067] The return of "invalid consistency" refers to the process described above: after receiving a data access request from the processor core, the home agent queries the consistency directory of the corresponding connection. If it determines that there is no entry in the consistency directory recording the consistency status of the cache line corresponding to the data access request, and there are no usable entries in the consistency directory, the home agent returns "invalid consistency" to the processor core. In other words, when there are no free entries in the consistency directory recording the consistency status of the new cache line, the home agent releases the occupied entries in the consistency directory and notifies the processor core's cache to remove the cache line corresponding to the occupied entry by sending a "invalid consistency" return. The new cache line represents the cache line corresponding to the address of the data retrieved from memory.

[0068] Based on the foregoing, it can be seen that when the home agent frequently sends and returns inconsistency invalidation, it means that the consistency catalog will frequently invalidate the cached lines recorded in the used entries. At the same time, the home agent also needs to wait for a long time for the processor core to complete the processing signal, thereby reducing the overall performance of the system.

[0069] Therefore, the technical solution described in this application determines the working status of the consistency catalog by detecting the frequency of invalidation of used entries returned by the home agent, thereby specifically solving the problem of reduced overall processing efficiency of multi-core processor systems caused by the frequent invalidation of cached lines in the consistency catalog.

[0070] In order to detect transmission frequencies that return invalid consistency in a timely manner, in one implementation, step S100 may include:

[0071] The counter value set in the home agent is detected, and the counter counts according to the number of times the home agent sends and returns invalid consistency.

[0072] Specifically, when there are no free entries in the consistency directory to record the consistency status of a new cache line, the home agent releases the occupied entries in the consistency directory and notifies the processor core's cache to remove the cache line corresponding to the occupied entry by sending a return message indicating consistency invalidity; the new cache line is the cache line corresponding to the address of the data when data is retrieved from memory into the cache.

[0073] In this embodiment, a counter can be set in the home agent. When the home agent sends a signal of invalid consistency back to the processor core, the counter value is incremented by one. Thus, the current usage status of the consistency catalog can be determined based on the counter value, and whether there are frequent sending and returning of invalid consistency, that is, the consistency catalog frequently invalidates cached lines in used entries.

[0074] By setting a counter in the home agent, the frequency of sending messages that return invalid consistency is counted, the frequency of sending messages that return invalid consistency is accurately obtained, and the technical solution described in this application is determined in a timely manner.

[0075] When a processor core sends a data access request for a cache line whose address corresponds to a cache line not recorded in the consistency directory, and there are no free entries in the consistency directory recording the consistency status of the new cache line, the home agent releases the occupied entries in the consistency directory and notifies the processor core's cache to remove the cache line corresponding to the occupied entry. The home agent can select occupied entries to release from the consistency directory, for example, selecting the occupied entry that has existed for the longest time in the consistency directory, or selecting the occupied entry with the lowest access hit rate in the consistency directory. The strategy for the home agent to select occupied entries to release from the consistency directory can be set according to actual conditions, and this application embodiment does not impose limitations.

[0076] In step S101, the processor core sends a data access request to the home agent.

[0077] When a processor core needs to access target data at a target address, it can look up the target data in the processor core's cache. If the target data is not found in the processor core's cache, the processor core can send a data access request to the home agent.

[0078] Step S102: When the home agent detects that the frequency of sending messages that return inconsistency is higher than a preset frequency threshold, it obtains the target data according to the target address indicated by the data access request issued by the processor core.

[0079] The consistency status of the target cache line corresponding to the target address is recorded in the target entry of the consistency directory.

[0080] The preset frequency threshold can be obtained by conducting performance analysis on the chip according to actual needs, or by trying various design values ​​of the frequency threshold on the performance model, running various benchmark programs, and obtaining an optimal value, which is the preset frequency threshold.

[0081] By detecting the frequency of invalidation messages, we can determine the current usage status of the consistency catalog and whether the consistency catalog is frequently invalidating cached lines in used entries. This allows us to promptly prevent the consistency catalog from frequently invalidating cached lines.

[0082] Step S103: The home agent sets an identifier carrying the temporary storage status in the response packet corresponding to the data access request.

[0083] The identifier is used to enable the processor core to load the target data into the target cache line in the non-last-level cache and to set a temporary state for the target cache line in the last-level cache, so that when the non-last-level cache removes the target cache line, the target cache line is written back to memory directly without going through the last-level cache.

[0084] When the home agent detects a frequency of invalid consistency transmissions, if the detected frequency exceeds a preset frequency threshold, a data access request is received from the processor core. As an improvement, in the access request processing method provided in this embodiment, in addition to obtaining the target data according to the target address indicated by the data access request, the home agent also sets an identifier carrying a temporary storage status in the response packet based on the data access request. When the processor core receives the response packet of the data access request and stores the target data in the processor core's non-last-level cache, it can further set the status of the target cache line corresponding to the target data in the non-last-level cache to a temporary storage status based on the identifier. This allows the non-last-level cache to remove the target cache line from the non-last-level cache directly into memory without going through the non-last-level cache. This saves the home agent the processing time of waiting for the processor core to remove the target cache from the non-last-level cache to the last-level cache and then to memory, improving the processing efficiency of the multi-core processor system. It should be noted that "exceeding" in the context of "exceeding the preset frequency threshold" means greater than or equal to the preset frequency threshold, thus accurately obtaining the current usage status of the consistency directory.

[0085] In order to enable the target cache line to be written back to memory directly without going through the last-level cache when it is removed from the non-last-level cache, the corresponding target cache line in the last-level cache will also be removed, so that the system as a whole can run normally. In one embodiment, the temporary state is used to indicate that when the target cache line is removed from the cache of the processor core, it is written back to memory directly without going through the last-level cache.

[0086] This application embodiment can remove the target cache line from the cache into memory. This allows the target cache line, which is loaded with target data in the processor core's non-last-level cache, to be directly removed from the non-last-level cache into memory without going through the last-level cache, based on the temporary state of the target cache line set in the last-level cache. This saves the agent the processing time of waiting for the processor core to remove the target cache line from the cache into memory.

[0087] In one implementation, step S102 may include:

[0088] If the counter value exceeds the counting threshold within a predetermined time, it is determined that the sending frequency of returning invalid consistency is higher than the preset frequency threshold.

[0089] To ensure that the obtained transmission frequency count accurately represents the current consistency directory's frequent invalidation of used entries, the size of the count needs to be designed, and a time range for frequently releasing used entries in the consistency directory needs to be set. Therefore, this embodiment allows setting a predetermined time range. If the counter value exceeds the count threshold within the predetermined time range, it indicates that the consistency directory is frequently releasing used entries within that time range. This means that within the predetermined time, processor core data access requests are frequently not hitting the cache, requiring frequent reading of data from memory and temporary storage in the processor core's cache. Simultaneously, the consistency directory entries are frequently full. In other words, within the predetermined time, processor core data access requests are frequently not hitting the cache, and the consistency directory is frequently in a state of having no usable entries. Therefore, the consistency directory needs to frequently release used entries to free up usable entries to record the consistency status of cache lines corresponding to data read from memory. Based on this, the present application embodiment can activate the access request processing method provided in the present application embodiment when the counter value exceeds the counting threshold within a predetermined time, so as to alleviate the situation where the consistency directory is frequently in a state of having no usable entries, thereby optimizing the performance of the consistency directory.

[0090] As an optional implementation, in order to adapt to the actual performance of various chips, in one embodiment, the predetermined time includes a predetermined number of clock cycles.

[0091] By conducting an analysis of the product's performance targets, a suitable predetermined timeframe, such as within n clock cycles, can be determined. For example, it could be 3 or 4 clock cycles; the number of clock cycles is not specifically limited, as long as it meets the actual usage requirements.

[0092] As an optional implementation, the home agent may obtain target data based on the target address indicated by the data access request in the following ways: when the consistency status of the target cache line corresponding to the target address is recorded in the consistency directory, the target data is obtained in other processor cores according to the location of the target address contained in the target cache line recorded in the target entry; when the target address contained in the target cache line is not recorded in the consistency directory, the target data is obtained in memory, and the consistency status of the target cache line is recorded in the usable entry of the consistency directory, where the usable entry is the target entry.

[0093] Optional, you can refer to Figure 4, Figure 4 This is another flowchart illustrating the access request processing method provided in the embodiments of this application.

[0094] As shown in the figure, the process may include the following steps:

[0095] Step S200: Detect the transmission frequency that returns invalid consistency.

[0096] The content of step S200 can be referred to the content of step S100, and will not be repeated here.

[0097] Step S201: Determine whether the transmission frequency is higher than the preset frequency threshold. If yes, proceed to step S202; otherwise, proceed to step S205.

[0098] When it is determined that the sending frequency is higher than the preset frequency threshold, it indicates that the consistency catalog will frequently invalidate used entries, affecting the performance of the multi-core processor system. At this time, step S202 is executed.

[0099] Step S202: Determine whether the target entry in the consistency catalog has recorded the consistency status of the target cache line. If yes, proceed to step S203; otherwise, proceed to step S204.

[0100] For the target address indicated by the data access request issued by the processor core, determine whether there is a corresponding target entry record in the consistency catalog.

[0101] Step S203: Based on the consistency status of the target entry record, determine the cache of the processor core that caches the target cache line; retrieve the target data of the target cache line from the determined processor core's cache.

[0102] Step S204: Obtain the target data at the target address from memory.

[0103] If the preset frequency threshold is not reached, then proceed according to... Figure 2 The normal process shown is for processing data access requests, i.e., step S205.

[0104] Step S205: Process the data access request received by the current home agent.

[0105] By setting a counter in the home agent, the number of times the home agent returns invalid consistency is counted. When the count value is higher than the preset frequency threshold, it indicates that the home agent is frequently sending invalid returns, which will in turn frequently invalidate the cache lines of used entries in the consistency catalog, affecting the processing performance of multi-core processor systems.

[0106] When the count value does not exceed the preset frequency threshold, it indicates that the home agent will not frequently invalidate cached lines of used entries in the consistency directory. In this case, the data access requests received by the home agent can be processed according to the normal data request processing flow, i.e., ... Figure 2 The diagram illustrates the processing flow. This approach prevents frequent invalidation of cached lines in the consistency catalog due to frequent feedback of consistency invalidation by the home agent, without affecting the normal data access request processing flow of the multi-core processor system. This optimizes the use of the consistency catalog and improves the processing efficiency of the multi-core processor system.

[0107] If the consistency catalog does not contain a target entry with the consistency status of the target cache line, the data access request is processed according to the normal consistency catalog procedure. Optionally, please refer to... Figure 5 , Figure 5 This is another flowchart illustrating the access request processing method provided in the embodiments of this application.

[0108] As shown in the figure, the processing flow of step S205 may include the following steps:

[0109] Step S300: Determine that the consistency status of the target entry in the consistency directory does not record the consistency status of the target cache line corresponding to the target address.

[0110] Step S301: Determine whether there are any usable entries in the consistency directory. If yes, proceed to step S302; otherwise, proceed to step S304.

[0111] Since the target entry for the target cache line is not recorded in the consistency catalog, meaning that the target cache line is not stored in the cache of other processor cores, it is necessary to retrieve the data corresponding to the target address of the target cache line from memory.

[0112] To achieve a consistent cache line state, ensuring that the multi-core processor system meets the consistency protocol and functions correctly, the consistency state of the target cache line needs to be recorded in the consistency directory after data is retrieved from memory. However, as mentioned earlier, the consistency directory has limited space; other data access requests have already been processed before the current one. Therefore, when processing the current data access request and recording the consistency state of the target cache line in the consistency directory, it's necessary to first determine if there are any free, usable entries in the consistency directory to satisfy the requirement of recording the consistency state of the target cache line.

[0113] Step S302: Allocate the usable entries to the target cache line and use the allocated usable entries as target entries to record the consistency status of the target cache line.

[0114] When it is determined that there are available, usable entries in the consistency directory, the available entries are used as target entries and directly assigned to the target cache line to record the consistency status of the target cache line.

[0115] Step S303: Obtain the target data at the target address from memory.

[0116] Based on the consistency status of the target cache line recorded in the target entry, the target data corresponding to the target address of the target cache line is retrieved from memory.

[0117] Step S304: Release the occupied entries in the consistency directory to obtain free target entries, send a return message indicating inconsistency to the processor core, and use the free target entries to record the consistency status of the target cache line.

[0118] When it is determined that there are no usable entries in the consistency directory, it means that the consistency directory is full and all entries are occupied. At this point, the consistency directory will release one of the occupied entries. Based on the consistency protocol, the processor core's cache will also invalidate or remove the cache line released in the consistency directory from the corresponding cache and move it to memory. The occupied entry can be a cache line recorded in the entry that is not frequently accessed by the processor core. This way, after the processor core invalidates or removes the corresponding cache line, it will not have a significant impact on other data access requests of the processor core.

[0119] The execution of data access requests is completed according to the normal processing flow of the consistency catalog, which does not affect the normal operation of the multi-core processor system, nor does it cause improper use of the consistency catalog, thereby improving the processing performance of the multi-core processor system.

[0120] Please continue to refer to this. Figure 3 As shown in the figure, the process may include the following steps:

[0121] In step S104, the home agent sends the response packet back to the processor core.

[0122] The agent responds to the data access request received from the processor core by sending the target data of the data access request back to the processor core in the form of an acknowledgment packet. After receiving the acknowledgment packet, the processor core can cache the target data of the target cache line in the non-last-level cache based on the temporary state identifier carried in the acknowledgment packet, and set the target cache line in the last-level cache to the temporary state. Thus, when the processor core removes the target cache line from the non-last-level cache, it can remove the target cache line directly from the last-level cache without going through the last-level cache, saving the processor core's processing time for removing the target cache line and improving the efficiency of the consistency catalog in recording the consistency state of the target cache line using entries.

[0123] In step S105, the processor core loads the target data into the target cache line in the non-last-level cache based on the identifier carrying the temporary storage status set in the response packet, and saves the temporary storage status of the target cache line in the last-level cache.

[0124] It is easy to understand that when the frequency of invalid return messages from the home agent is higher than a preset frequency threshold, the home agent sets the identifier in the response packet of the data access request accordingly; the temporary state is used to indicate that when the target cache line is removed from the cache of the processor core, it is written back to memory directly without going through the last-level cache.

[0125] By setting an identifier carrying the temporary status in the response packet, the time it takes for the processor core to remove the target cache line from the cache to memory is saved. Correspondingly, the time it takes for the agent to wait for the processor core to process the data can be saved, ultimately improving the processing efficiency of multi-core processor systems.

[0126] Step S106: The processor core sends a write-back request for the target cache line to the home agent.

[0127] The write-back request is used to remove the target cache line into memory and instruct the home agent to release the target entry corresponding to the target cache line in the consistency directory.

[0128] The write-back request sent by the processor core to the home agent causes the home agent to release the target entry corresponding to the target cache line in the consistency catalog. This allows the home agent to not only acquire the data requested by the data access request, but also release the target entry already occupied by the target cache line in the consistency catalog, thus achieving the effect of pre-releasing the target entry before receiving the next data access request.

[0129] In step S107, the home agent obtains the write-back request for the target cache line and releases the target entry corresponding to the target cache line in the consistency directory.

[0130] Since the home agent returns a response packet after responding to a data access request, the consistency state of the target cache line corresponding to the target address is already recorded in the consistency directory after the home agent retrieves the target data from memory. This entry is the target entry. Therefore, the home agent can release the target entry corresponding to the target cache line according to the write-back request.

[0131] As can be seen, the access request processing method provided in this application detects the sending frequency of the consistency directory's feedback return of invalid consistency. When the sending frequency reaches a frequency threshold, it can be determined that the consistency directory has frequently issued returns of invalid consistency. To avoid the low processing efficiency of multi-core processor systems caused by returns of invalid consistency, this application sets an identifier carrying a temporary storage status in the response packet of the data access request for the processor core by the home agent. Based on the identifier, the processor core can load the target data into the target cache line in the non-last-level cache; and set a temporary storage status for the target cache line in the last-level cache, so that when the target cache line is evicted from the non-last-level cache, the target cache line is written back to memory directly without going through the last-level cache. This saves time for the processor core to evict the corresponding target cache line, eliminating the need for the home agent to wait for the processor core to remove the target cache line from the cache to memory. Simultaneously, since the processor core sends the write-back request for the target cache line to the home agent based on the temporary state identifier, and then directly writes it back to memory, the home agent can find the target entry containing the target cache line in the consistency catalog. The home agent can then release the target cache line from the target entry based on the received write-back request, i.e., write the target cache line back to memory. This achieves the goal of pre-releasing used entries in the consistency catalog, improving the performance of the consistency catalog and thus enhancing the performance of the multi-core processor system.

[0132] This application also provides a multi-core processor system, including:

[0133] A proxy is used to detect the frequency of sending messages that return inconsistency invalidity. When the frequency of sending messages that return inconsistency invalidity is higher than a preset frequency threshold, the proxy retrieves the target data according to the target address indicated by the data access request for the processor core. The consistency status of the target cache line corresponding to the target address is recorded in the target entry of the consistency directory. The proxy also sets an identifier carrying the temporary storage status in the response packet corresponding to the data access request and feeds the response packet back to the processor core. The proxy retrieves the write-back request for the target cache line and releases the target entry in the consistency directory.

[0134] The processor core is used to send a data access request to the home agent; obtain the target data and response packet corresponding to the data access request; if the response packet is set with an identifier carrying a temporary state, load the target data into the target cache line in the non-last-level cache, and save the temporary state of the target cache line in the last-level cache; wherein, the temporary state is used to indicate that when the target cache line is removed from the processor core's cache, it is written back to memory directly without going through the last-level cache; when the target cache line is removed from the cache, a write-back request for the target cache line is sent.

[0135] As can be seen, the multi-core processor system provided in this application embodiment can, when the home agent detects that the frequency of sending invalid consistency messages reaches a preset frequency threshold, respond to the data access request sent by the processor core based on the received data access request, and set an identifier carrying a temporary state in the response packet returned to the processor core. Thus, when the processor core receives the returned response packet, it sets the target cache line in the last-level cache to a temporary state based on the identifier in the response packet. In this way, when the processor core's non-last-level cache removes the target cache line to memory, it does not need to go through the last-level cache. Then, when the home agent receives the write-back request sent by the processor core to write the target cache line back to memory, it responds to the write-back request and releases the target cache line recorded in the target entry of the consistency directory. When the home agent receives the next data access request, the target entry of the target cache line is released because there is a usable entry in the consistency directory, without having to send an invalid consistency message to the processor core again and wait for the processor core's processing result. This allows the home agent to prepare a usable entry in advance for the next data access request, saving the time of waiting for the processor core to remove the target cache line from the cache to memory.

[0136] In some implementations, the home agent is used to detect transmission frequencies that return invalid consistency, including:

[0137] The counter value set in the home agent is detected, and the counter counts according to the number of times the home agent sends and returns invalid consistency.

[0138] Specifically, when there are no free entries in the consistency directory to record the consistency status of a new cache line, the home agent releases the occupied entries in the consistency directory and notifies the processor core's cache to remove the cache line corresponding to the occupied entry by sending a return message indicating consistency invalidity; the new cache line is the cache line corresponding to the address of the data when data is retrieved from memory into the cache.

[0139] In some implementations, the home agent is used to detect that the frequency of sending messages returning invalid consistency is higher than a preset frequency threshold, including:

[0140] If the counter value exceeds the counting threshold within a predetermined time, it is determined that the sending frequency of returning invalid consistency is higher than the preset frequency threshold.

[0141] In some implementations, the predetermined time includes a predetermined number of clock cycles.

[0142] In some implementations, the home agent is used to set an identifier carrying a temporary status in the response packet corresponding to the data access request, including: setting the identifier using a reserved space in the original response packet.

[0143] In some implementations, the temporary state is used to indicate that when the target cache line is removed from the processor core's cache, it is written directly back to memory without going through the last-level cache.

[0144] In some implementations, the processor core is configured to load target data into a target cache line that is not the last-level cache, based on an identifier carrying a temporary storage status set in the response packet, wherein the identifier is set using a reserved bit in the original response packet.

[0145] In some implementations, the processor core is configured to send a data access request to the home agent, including:

[0146] When it is determined that the target data at the target address is not stored in the cache of the processor core, a data access request corresponding to the target address is sent to the home agent.

[0147] This application also provides a chip, including the multi-core processor system described in the above embodiments.

[0148] This application also provides an electronic device, including the chip described above.

[0149] While the embodiments disclosed above are described in this application, this application is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of this application; therefore, the scope of protection of this application should be determined by the scope defined in the claims.

Claims

1. An access request processing method, characterized in that, Applied to home agents, including: The frequency at which invalid transmissions are detected and returned is checked; When the frequency of sending invalid return values ​​is higher than a preset frequency threshold, for the data access request issued by the processor core, the target data is obtained according to the target address indicated by the data access request; wherein, the consistency status of the target cache line corresponding to the target address is recorded in the target entry of the consistency directory; In addition, an identifier carrying a temporary storage status is set in the response packet corresponding to the data access request, and the response packet is fed back to the processor core; the identifier is used to enable the processor core to load the target data in the target cache line in the non-last-level cache, and set a temporary storage status for the target cache line in the last-level cache, so that when the non-last-level cache removes the target cache line, the target cache line is written back to memory directly without going through the last-level cache. Obtain the write-back request for the target cache line and release the target entry in the consistency directory.

2. The access request processing method as described in claim 1, characterized in that, The frequency at which the detection returns invalid consistency includes: The counter value set in the home agent is detected, and the counter counts according to the number of times the home agent sends and returns invalid consistency. Specifically, when there are no free entries in the consistency directory to record the consistency status of a new cache line, the home agent releases the occupied entries in the consistency directory and notifies the processor core's cache to remove the cache line corresponding to the occupied entry by sending a return message indicating consistency invalidity; the new cache line is the cache line corresponding to the address of the data when data is retrieved from memory into the cache.

3. The access request processing method as described in claim 2, characterized in that, The detection of the sending frequency of invalid return consistency being higher than a preset frequency threshold includes: If the counter value exceeds the counting threshold within a predetermined time, it is determined that the sending frequency of returning invalid consistency is higher than the preset frequency threshold.

4. The access request processing method as described in claim 3, characterized in that, The predetermined time includes a predetermined number of clock cycles.

5. The access request processing method as described in claim 1, characterized in that, Setting an identifier carrying a temporary status in the response packet corresponding to the data access request includes: setting the identifier using the existing reserved space in the response packet.

6. The access request processing method as described in claim 1, characterized in that, The temporary state is used to indicate that when the target cache line is removed from the processor core's cache, it is written directly back to memory without going through the last-level cache.

7. The access request processing method as described in claim 1, characterized in that, The step of obtaining target data according to the target address indicated by the data access request includes: If the target entry in the consistency directory has been recorded, the consistency status of the target cache line corresponding to the target address is determined based on the consistency status recorded in the target entry; the target data of the target cache line is then obtained from the determined processor core's cache. If the consistency directory does not contain an entry recording the consistency status of the target cache line, the target data at the target address is retrieved from memory.

8. The access request processing method as described in claim 7, characterized in that, Also includes: If there is no entry in the consistency directory that records the consistency status of the target cache line, then it is determined whether there is a usable entry in the consistency directory. When it is determined that there is a usable entry in the consistency directory, the usable entry is allocated to the target cache line, and the allocated usable entry is used as the target entry to record the consistency status of the target cache line; When it is determined that there are no usable entries in the consistency directory, the occupied entries in the consistency directory are released to obtain free target entries; at the same time, a consistency invalid return is sent to the processor core, and the consistency status of the target cache line is recorded using the free target entries.

9. An access request processing method, characterized in that, Applied to processor cores, including: Send a data access request to the home agent; Obtain the target data and response packet corresponding to the data access request; If the response packet contains an identifier carrying a temporary state, the target data is loaded into the target cache line (not in the last-level cache), and the temporary state of the target cache line is saved in the last-level cache. When the frequency of the home agent sending invalid return values ​​exceeds a preset frequency threshold, the home agent sets the identifier in the response packet for the data access request. The temporary state indicates that when the target cache line is removed from the processor core's cache, it is written directly back to memory without going through the last-level cache. When the target cache line is removed from the cache, a write-back request for the target cache line is sent. The write-back request is used to remove the target cache line from memory and instruct the home agent to release the target entry corresponding to the target cache line in the consistency directory.

10. The access request processing method as described in claim 9, characterized in that, The identifier is set using the reserved space originally provided in the response packet.

11. The access request processing method as described in claim 9, characterized in that, Sending a data access request to the home agent includes: When it is determined that the target data at the target address is not stored in the cache of the processor core, a data access request corresponding to the target address is sent to the home agent.

12. A multi-core processor system, characterized in that, include: A proxy is used to detect the frequency of sending messages that return inconsistency invalidity. When the frequency of sending messages that return inconsistency invalidity is higher than a preset frequency threshold, the proxy retrieves the target data according to the target address indicated by the data access request for the processor core. The consistency status of the target cache line corresponding to the target address is recorded in the target entry of the consistency directory. The proxy also sets an identifier carrying the temporary storage status in the response packet corresponding to the data access request and feeds the response packet back to the processor core. The proxy retrieves the write-back request for the target cache line and releases the target entry in the consistency directory. The processor core is used to send a data access request to the home agent; obtain the target data and response packet corresponding to the data access request; if the response packet is set with an identifier carrying a temporary state, load the target data into the target cache line in the non-last-level cache, and save the temporary state of the target cache line in the last-level cache; wherein, the temporary state is used to indicate that when the target cache line is removed from the processor core's cache, it is written back to memory directly without going through the last-level cache; when the target cache line is removed from the cache, a write-back request for the target cache line is sent.

13. The multi-core processor system as described in claim 12, characterized in that, The home agent, used to detect the frequency of transmissions returning invalid consistency, includes: The counter value set in the home agent is detected, and the counter counts according to the number of times the home agent sends and returns invalid consistency. Specifically, when there are no free entries in the consistency directory to record the consistency status of a new cache line, the home agent releases the occupied entries in the consistency directory and notifies the processor core's cache to remove the cache line corresponding to the occupied entry by sending a return message indicating consistency invalidity; the new cache line is the cache line corresponding to the address of the data when data is retrieved from memory into the cache.

14. The multi-core processor system as described in claim 13, characterized in that, The home agent is used to detect that the frequency of sending messages that return invalid consistency is higher than a preset frequency threshold, including: If the count value exceeds the count threshold within a predetermined time, it is determined that the sending frequency of returning invalid consistency is higher than the preset frequency threshold.

15. The multi-core processor system as described in claim 14, characterized in that, The predetermined time includes a predetermined number of clock cycles.

16. The multi-core processor system as described in claim 12, characterized in that, The home agent is used to set an identifier carrying a temporary status in the response packet corresponding to the data access request, including: setting the identifier using the original reserved space in the response packet.

17. The multi-core processor system as described in claim 12, characterized in that, The temporary state is used to indicate that when the target cache line is removed from the processor core's cache, it is written directly back to memory without going through the last-level cache.

18. The multi-core processor system as described in claim 12, characterized in that, The processor core is used to load target data into a target cache line that is not the last-level cache, based on an identifier carrying a temporary storage status set in the response packet. The identifier is set using the original reserved bits in the response packet.

19. The multi-core processor system as described in claim 12, characterized in that, The processor core is used to send data access requests to the home agent, including: When it is determined that the target data at the target address is not stored in the cache of the processor core, a data access request corresponding to the target address is sent to the home agent.

20. A chip, characterized in that, Includes the multi-core processor system according to any one of claims 12-19.

21. An electronic device, characterized in that, Includes the chip as described in claim 20.

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