Integrated circuit for memory access, processing method, electronic device and medium

Abstract

Embodiments of the present disclosure disclose an integrated circuit, a processing method, an electronic device and a medium for memory access, wherein the integrated circuit comprises: a first bit width conversion module configured to convert a first write access signal of a processor into a second write access signal comprising two copies of original to-be-written data; a first memory control module configured to convert target to-be-written data in the second write access signal into at least one set of first to-be-written data satisfying a first protocol supported by a memory physical layer interface, and determine a corresponding set of third write access signals, each set of first to-be-written data comprising two identical first to-be-written data from the two copies of original to-be-written data; and a memory physical layer interface configured to convert each set of third write access signals into two fourth write access signals satisfying a memory protocol, and transmit each fourth write access signal to a corresponding memory module. The embodiments of the present disclosure can effectively meet the storage requirements of higher security level functions based on a lower security level memory.

Description

Technical Field

[0001] This disclosure relates to semiconductor technology, and in particular to an integrated circuit, processing method, electronic device, and medium for memory access. Background Technology

[0002] In the field of intelligent driving, the DDR (Double Data Rate SDRAM (Synchronous Dynamic Random Access Memory) of intelligent driving chips is mainly used for the perception and prediction functions of intelligent driving. The current functional safety level requirement for this function is ASILB (Automotive Safety Integrity Level B). However, with the evolution of the algorithms for control and decision-making functions with a safety level of ASILD (Automotive Safety Integrity Level D) in intelligent driving functions, the computing power and storage requirements of the control and decision-making function algorithms are increasing. There is a problem of insufficient storage when developing control and decision-making algorithms through processors (or processor cores) and RAM, resulting in insufficient storage for higher safety level functions. Summary of the Invention

[0003] To address the technical problems such as insufficient storage for higher security level functions, as described above, this disclosure is proposed. Embodiments of this disclosure provide an integrated circuit, a processing method, an electronic device, and a medium for memory access.

[0004] According to one aspect of the present disclosure, an integrated circuit for memory access is provided, comprising: a first bit-width conversion module, configured to convert original data to be written in a first write access signal of a processor into target data to be written, including two copies of the original data to be written, according to a first preset conversion method, and to determine a converted second write access signal based on the target data to be written; a first memory control module, connected to the first bit-width conversion module, configured to convert the target data to be written in the second write access signal into at least one set of first data to be written that satisfies a first protocol supported by a memory physical layer interface, and to determine a corresponding set of third write access signals based on each set of first data to be written, wherein each set of first data to be written includes two identical copies of first data to be written from the two copies of the original data to be written, and each set of third write access signals includes two third write access signals; and a memory physical layer interface, connected to the first memory control module, configured to convert each set of third write access signals into two fourth write access signals that satisfy a memory protocol, and to transmit each of the fourth write access signals to its corresponding memory module.

[0005] According to another aspect of the present disclosure, a processing method for memory access is provided, comprising: converting original data to be written in a first write access signal of a processor into target data to be written, including two copies of the original data to be written, according to a first preset conversion method; determining a converted second write access signal based on the target data to be written; converting the target data to be written in the second write access signal into at least one set of first data to be written that satisfies a first protocol supported by a memory physical layer interface; determining a corresponding set of third write access signals based on each set of first data to be written, wherein each set of first data to be written includes two identical copies of first data to be written from the two copies of the original data to be written, and each set of third write access signals includes two third write access signals; converting each set of third write access signals into two fourth write access signals that satisfy a memory protocol; and transmitting each fourth write access signal to its corresponding memory module.

[0006] According to another aspect of the present disclosure, a computer-readable storage medium is provided, the storage medium storing a computer program for executing the methods described in any of the above embodiments of the present disclosure; or, the storage medium is used to store data that needs to be stored in at least one hardware logic circuit of the integrated circuit described in any of the above embodiments of the present disclosure, so that the hardware logic circuit can perform corresponding functions when it is working.

[0007] According to another aspect of the present disclosure, an electronic device is provided, the electronic device comprising: a processor; a memory for storing executable instructions of the processor; the processor being configured to read the executable instructions from the memory and execute the instructions to implement the method described in any of the above embodiments of the present disclosure; or, the electronic device comprising an integrated circuit as described in any of the above embodiments; wherein at least one module in the integrated circuit is implemented by hardware logic circuitry.

[0008] Based on the integrated circuit, processing method, electronic device, and medium for memory access provided in the above embodiments of this disclosure, by performing bit-width conversion on the processor's first write access signal, the original data to be written is converted into target data to be written, which includes two copies of the original data to be written. Then, based on the target data to be written, a converted second write access signal is determined. The two copies of the original data to be written are written to two memory modules through the first memory control module and the memory physical layer interface, so that when reading data, the same data can be read from the two memory modules. By ensuring the consistency of the access results of the two memory modules, the functional safety of higher security level functions is guaranteed. This enables the memory controller to complete access operations of higher security level functions even when only lower security level scenarios are met. Thus, lower security level memory can be used for higher security level functions, allowing higher security level functions to access lower security level memory. While ensuring functional safety, this provides greater storage support for higher security level functions, effectively meeting the storage requirements of higher security level functions and solving problems such as insufficient storage for higher security level functions.

[0009] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0010] The above and other objects, features, and advantages of this disclosure will become more apparent from the more detailed description of the embodiments thereof in conjunction with the accompanying drawings. The drawings are provided to further illustrate the embodiments of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the disclosure and do not constitute a limitation thereof. In the drawings, the same reference numerals generally represent the same components or steps.

[0011] Figure 1 This is an exemplary application scenario of the integrated circuit for memory access provided in this disclosure;

[0012] Figure 2 This is a schematic diagram of the structure of an integrated circuit for memory access provided in an exemplary embodiment of this disclosure;

[0013] Figure 3 This is a schematic diagram of the structure of an integrated circuit for memory access provided in another exemplary embodiment of this disclosure;

[0014] Figure 4 This is a schematic diagram of the structure of the read data verification module 27 provided in an exemplary embodiment of this disclosure;

[0015] Figure 5 This is a schematic diagram of the structure of an integrated circuit for memory access provided in yet another exemplary embodiment of this disclosure;

[0016] Figure 6This is a schematic diagram of the structure of the memory physical layer interface 23 provided in an exemplary embodiment of this disclosure;

[0017] Figure 7 This is a schematic diagram of the structure of the memory physical layer interface 23 provided in another exemplary embodiment of this disclosure;

[0018] Figure 8 This is a schematic diagram illustrating the conversion principle from the original data to the target data to be written, provided in an exemplary embodiment of this disclosure.

[0019] Figure 9 This is a schematic diagram of the structure of an integrated circuit for memory access provided in yet another exemplary embodiment of this disclosure;

[0020] Figure 10 This is a schematic diagram of the structure of an integrated circuit for memory access provided in yet another exemplary embodiment of this disclosure;

[0021] Figure 11 This is a schematic diagram illustrating the principle of converting third data to fourth data according to an exemplary embodiment of this disclosure;

[0022] Figure 12 This is a flowchart illustrating a memory access processing method provided in an exemplary embodiment of this disclosure:

[0023] Figure 13 This is a flowchart illustrating a processing method for memory access provided in another exemplary embodiment of this disclosure;

[0024] Figure 14 This is a schematic diagram of the read data flow for memory access provided in an exemplary embodiment of this disclosure;

[0025] Figure 15 This is a flowchart illustrating a processing method for memory access provided in yet another exemplary embodiment of this disclosure;

[0026] Figure 16 This is a schematic diagram of another application embodiment of the electronic device disclosed herein. Detailed Implementation

[0027] Hereinafter, exemplary embodiments according to the present disclosure will be described in detail with reference to the accompanying drawings. Obviously, the described embodiments are merely some embodiments of the present disclosure, and not all embodiments of the present disclosure, and it should be understood that the present disclosure is not limited to the exemplary embodiments described herein.

[0028] It should be noted that, unless otherwise specifically stated, the relative arrangement, numerical expressions, and values ​​of the components and steps set forth in these embodiments do not limit the scope of this disclosure.

[0029] Those skilled in the art will understand that the terms "first," "second," etc., in the embodiments of this disclosure are only used to distinguish different steps, devices, or modules, and do not represent any specific technical meaning, nor do they indicate a necessary logical order between them.

[0030] It should also be understood that in the embodiments disclosed herein, "a plurality of" may refer to two or more, and "at least one" may refer to one, two or more.

[0031] It should also be understood that any component, data or structure mentioned in the embodiments of this disclosure can generally be understood as one or more unless expressly defined or given to the contrary in the context.

[0032] Furthermore, the term "and / or" in this disclosure is merely a description of the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A existing alone, A and B existing simultaneously, or B existing alone. Additionally, the character " / " in this disclosure generally indicates that the preceding and following related objects have an "or" relationship.

[0033] It should also be understood that the description of the various embodiments in this disclosure emphasizes the differences between the various embodiments, and the similarities or similarities can be referred to each other. For the sake of brevity, they will not be described in detail.

[0034] At the same time, it should be understood that, for ease of description, the dimensions of the various parts shown in the accompanying drawings are not drawn according to actual scale.

[0035] The following description of at least one exemplary embodiment is merely illustrative and is in no way intended to limit this disclosure or its application or use.

[0036] Techniques, methods, and equipment known to those skilled in the art may not be discussed in detail, but where appropriate, such techniques, methods, and equipment should be considered part of the specification.

[0037] It should be noted that similar labels and letters in the following figures indicate similar items; therefore, once an item is defined in one figure, it does not need to be discussed further in subsequent figures.

[0038] The embodiments disclosed herein can be applied to electronic devices such as terminal devices, computer systems, and servers, and can operate together with a wide range of other general-purpose or special-purpose computing system environments or configurations. Examples of well-known terminal devices, computing systems, environments, and / or configurations suitable for use with electronic devices such as terminal devices, computer systems, and servers include, but are not limited to: personal computer systems, server computer systems, thin clients, thick clients, handheld or laptop devices, microprocessor-based systems, set-top boxes, programmable consumer electronics, network PCs, minicomputer systems, mainframe computer systems, and distributed cloud computing environments including any of the above systems, etc.

[0039] Electronic devices such as terminal devices, computer systems, and servers can be described in the general context of computer system executable instructions (such as program modules) executed by a computer system. Typically, program modules can include routines, programs, object programs, components, logic, data structures, etc., which perform specific tasks or implement specific abstract data types. Computer systems / servers can be implemented in distributed cloud computing environments, where tasks are executed by remote processing devices linked through communication networks. In distributed cloud computing environments, program modules can reside on local or remote computing system storage media, including storage devices.

[0040] SUMMARY

[0041] In the process of realizing this disclosure, the inventors discovered that in the field of intelligent driving, the DDR (Double Data Rate SDRAM (Synchronous Dynamic Random Access Memory) of intelligent driving chips is mainly used for the perception and prediction functions of intelligent driving. The current functional safety level requirement for this function is ASILB (Automotive Safety Integrity Level B). However, with the evolution of the algorithms for control and decision-making functions with a safety level of ASILD (Automotive Safety Integrity Level D) in intelligent driving functions, the computing power and storage requirements of the control and decision-making function algorithms are increasing. There is a problem of insufficient storage when developing control and decision-making algorithms through processors (or processor cores) and RAM, resulting in insufficient storage for higher safety level functions.

[0042] EXEMPLARY OVERVIEW

[0043] Figure 1This is an exemplary application scenario of the integrated circuit for memory access provided in this disclosure.

[0044] In functional scenarios of intelligent driving, such as control and decision-making at preset safety levels (ASILD levels), the integrated circuit for memory access disclosed herein allows the processor responsible for executing the corresponding control and decision-making algorithms to access DDR while ensuring its functional safety level (ASILD). This provides more powerful storage capabilities based on DDR to meet its increasing storage demands. The processor can be any possible processor or processor core within the intelligent driving chip, such as a central processing unit (CPU), graphics processing unit (GPU), brain processor (BPU), artificial intelligence processor (NPU), deep learning processor (DPU), etc., without specific limitations. Specifically, the integrated circuit for memory access disclosed herein may include a first wide-width conversion module, a first memory control module, and a memory physical layer interface. The first wide conversion module is used to convert the original data to be written in the processor's first write access signal into target data to be written, which includes two original data to be written, according to a first preset conversion method, and to determine the converted second write access signal based on the target data to be written; the first memory control module is connected to the first wide conversion module and is used to convert the target data to be written in the second write access signal into at least one set of first data to be written that meets the first protocol supported by the memory physical layer interface, and to determine a corresponding set of third write access signals based on each set of first data to be written. Each set of first data to be written includes two identical first data to be written from the two original data to be written, and each set of third write access signals includes two third write access signals; the memory physical layer interface is connected to the first memory control module and is used to convert each set of third write access signals into two fourth write access signals that meet the memory protocol, and to transmit each fourth write access signal to its corresponding memory module. Therefore, for memory access, two memory modules can be accessed simultaneously. By ensuring the consistency of the access results of the two memory modules, a higher level of memory access security can be achieved. This enables memory devices with larger storage capacity based on lower-level (e.g., ASILB level) memory devices to provide storage capacity for higher-level (e.g., ASILD level) functional scenarios, effectively solving the problem of insufficient storage for higher-level functional scenarios in existing technologies.

[0045] It should be noted that the integrated circuit disclosed herein is not limited to the control and decision-making scenarios of the aforementioned intelligent driving, and can be applied to any scenario requiring a high level of safety, depending on actual needs, without any specific limitations.

[0046] Exemplary Apparatus

[0047] Figure 2This is a schematic diagram of the structure of an integrated circuit for memory access provided in an exemplary embodiment of this disclosure. This embodiment can be applied to electronic devices, specifically, for example, in-vehicle computing platforms, such as... Figure 2 As shown, the integrated circuit (hereinafter referred to as integrated circuit) 20 for memory access includes: a first wide conversion module 21, a first memory control module 22, and a memory physical layer interface 23.

[0048] The first wide conversion module 21 is used to convert the original data to be written in the processor's first write access signal into target data to be written, which includes two original data to be written, according to a first preset conversion method, and to determine the converted second write access signal based on the target data to be written.

[0049] The first memory control module 22, connected to the first width conversion module 21, is used to convert the target data to be written in the second write access signal into at least one set of first data to be written that satisfies the first protocol supported by the memory physical layer interface, and to determine a corresponding set of third write access signals based on each set of first data to be written. Each set of first data to be written includes two identical sets of first data to be written from two original sets of data to be written, and each set of third write access signals includes two third write access signals.

[0050] The memory physical layer interface 23 is connected to the first memory control module 22 and is used to convert each group of third write access signals into two fourth write access signals that meet the memory protocol, and transmit each fourth write access signal to its corresponding memory module.

[0051] The processor can be any possible processor or processor core within the intelligent driving chip, such as a central processing unit (CPU), graphics processing unit (GPU), artificial intelligence (AI) processor (or AI processor core), etc., without specific limitations. The first write access signal can include data signals (including the original data to be written), control signals, and address signals. The first preset conversion method can be set according to actual needs. The first preset conversion method is used to copy the original data to be written into two copies, and combine the two copies of the original data to be written into the target data to be written according to a preset format, which serves as the data signal for the second write access signal.

[0052] The first memory control module 22 is a control module connecting the first width conversion module 21 and the memory physical layer interface 23. It is used to convert the second write access signal converted by the first width conversion module 21 into a write access signal that satisfies the memory physical layer interface protocol. In order to write two original copies of data to be written to two memory modules respectively, the first memory control module 22 converts the target data to be written, which includes two original copies of data to be written, into at least one set of first data to be written when performing protocol conversion. Each set includes two identical sets of first data to be written. The two sets of first data to be written in each set come from two original copies of data to be written in the target data to be written. For example, if the original data to be written is 128 bits and the first data to be written is 16 bits, then 8 sets of first data to be written can be converted. The two sets of first data to be written in the first set both include bits 0-15 of the original data to be written, the two sets of first data to be written in the second set both include bits 16-31 of the original data to be written, ..., and the two sets of first data to be written in the eighth set both include bits 112-127 of the original data to be written. Each piece of first data to be written serves as a data signal for one third write access signal, thus at least one set of converted third write access signals can be obtained, each set including two third write access signals.

[0053] In practical applications, the specific bit widths of the original data to be written and the first data to be written can be set according to actual needs.

[0054] The memory physical layer interface 23 serves as a bridge connecting the first memory control module 22 and the memory. It converts the two sets of third write access signals from each group, as processed by the first memory control module 22, into two sets of fourth write access signals that satisfy the memory protocol. These fourth write access signals are then transmitted to their corresponding memory modules; for example, one fourth write access signal is transmitted to the first memory module, and the other to the second memory module. This allows the two sets of data to be written to the two memory modules in multiple groups.

[0055] In one optional embodiment, in the various conversion processes of the write access signal, in addition to the conversion of the data to be written, the control signal may also be transformed. For example, in the process of converting the first write access signal to the second write access signal, in addition to converting the original data to be written to the target data to be written, the signal representing the data length in the control signal also needs to be converted. For another example, when the first memory control module converts the second write access signal to each group of third write access signals, in addition to converting the target data to be written to the first data to be written, the data length also needs to be transformed. The specific settings can be configured according to actual needs.

[0056] In an optional embodiment, the conversion of each module can also be represented as the conversion of access signals. The conversion of the data portion needs to follow the aforementioned conversion method. For example, the first-width conversion module 21 is used to convert the first write access signal into a second write access signal. The target data to be written in the second write access signal is obtained by converting the original data to be written in the first write access signal according to a first preset conversion method. The target data to be written includes two copies of the original data to be written. The conversion of the first write access signal into the second write access signal also includes the conversion of control signals, which can be specifically set according to actual needs.

[0057] In an alternative embodiment, the first memory control module 22 may be a DDR controller.

[0058] In an optional embodiment, the memory physical layer interface 23 can be a DDR PHY (DDR Physical Interface), the corresponding first protocol can be the DFI (DDR PHY Interface) protocol, and the memory protocol can be the DDR protocol. The DDRPHY includes two independent transmission channels, which can be used to transmit two fourth write access signals for each group.

[0059] In an optional embodiment, the specific structure of the first wide conversion module 21, the first memory control module 22, and the memory physical layer interface 23 can be set according to actual needs.

[0060] In an optional embodiment, each fourth write access signal corresponds to one memory module. The two third write access signals in each group can be converted into two fourth write access signals, thus corresponding to two memory modules, which can be referred to as the first memory module and the second memory module, respectively. These two memory modules can be any two memory devices connected within the intelligent driving chip or two memory regions within the same memory device, such as two memory regions with the same address in the DDR within the intelligent driving chip. The specific configuration can be set according to actual needs.

[0061] Optionally, the integrated circuit disclosed herein can be connected to the processor via any implementable bus, such as AXI, AHB, APB, CHI, etc., thereby enabling the processor to access the first memory module and the second memory module via the bus.

[0062] The integrated circuit for memory access provided in this embodiment converts the original data to be written into target data to be written, which includes two copies of the original data, by performing bit-width conversion on the processor's first write access signal. Then, based on the target data to be written, a converted second write access signal is determined. The two copies of the original data to be written are written to two memory modules through the first memory control module and the memory physical layer interface. This allows the same data to be read from the two memory modules during data reading. By ensuring the consistency of the access results of the two memory modules, the functional safety of higher security level functions is guaranteed. This enables the memory controller to complete access operations of higher security level functions even when only lower security level scenarios are met. As a result, lower security level memory can be used for higher security level functions, allowing higher security level functions to access lower security level memory. This provides greater storage support for higher security level functions while ensuring functional safety, effectively meeting the storage requirements of higher security level functions and solving problems such as insufficient storage for higher security level functions.

[0063] Figure 3 This is a schematic diagram of the structure of an integrated circuit for memory access provided in another exemplary embodiment of this disclosure.

[0064] In an optional embodiment, the integrated circuit disclosed herein further includes: a second memory control module 24 and a first comparison module 25.

[0065] The second memory control module 24 is connected to the first wide conversion module 21 and is used to convert the target data to be written in the second write access signal into at least one set of second data to be written that satisfies the first protocol supported by the memory physical layer interface 23. Based on each set of second data to be written, a corresponding set of fifth write access signals is determined. Each set of second data to be written includes two identical sets of second data to be written from two original sets of data to be written. Each set of fifth write access signals includes two fifth write access signals.

[0066] The first comparison module 25 is connected to the first memory control module 22 and the second memory control module 24 respectively, and is used to compare the third write access signals of each group with the fifth write access signals of each group. In response to the inconsistency of the comparison results, an error signal is output.

[0067] The conversion principle of the second memory control module 24 is the same as that of the first memory control module 22. The difference is that the fifth write access signals obtained by the second memory control module 24 do not need to be transmitted to the memory physical layer interface 23, but are instead transmitted to the first comparison module 25. Similarly, the third write access signals obtained by the first memory control module 22 also need to be transmitted to the first comparison module 25. The first comparison module 25 compares the third write access signals with the fifth write access signals to determine whether the processing results of the first memory control module 22 and the second memory control module 24 are consistent. If the comparison results are inconsistent, an error signal is output to take timely measures, thereby ensuring the functional safety of the first memory control module 22 and preventing dangerous situations caused by errors in the first memory control module 22.

[0068] In an optional embodiment, in addition to comparing the third write access signals and the fifth write access signals of each group, the first comparison module 25 can also compare other output signals during the operation of the first memory control module 22 and the second memory control module 24, so as to realize mutual verification of all functions of the first memory control module 22 and the second memory control module 24, so as to further ensure the functional security of the first memory control module 22.

[0069] This embodiment sets up a second memory control module with the same function as the first memory control module to verify the processing results of the first memory control module. This can effectively ensure the correctness and validity of the processing results of the first memory control module, thereby ensuring the security of written data. Errors in the first memory control module can be detected in time, so that write access to memory can meet a high level of security.

[0070] In an optional embodiment, the integrated circuit of this disclosure further includes: a second bit-width conversion module 26 and a read data verification module 27.

[0071] The memory physical layer interface 23 is also used to obtain at least one set of first data from the first memory module and the second memory module respectively, convert each set of first data in the at least one set of first data into a set of second data that satisfies the first protocol, and transmit each set of second data to the first memory control module 22. Each set of first data includes first read data and second read data, and each set of second data includes third read data corresponding to the first read data and fourth read data corresponding to the second read data.

[0072] The first memory control module 22 is also used to convert each group of second data into third data that meets the second protocol supported by the second bit width conversion module 26, and transmit the third data to the second bit width conversion module 26.

[0073] The second bit-width conversion module 26 is used to perform bit-width conversion on the third data according to the second preset conversion method to obtain the fourth data and the fifth data, and to transmit the fourth data to the processor.

[0074] The data verification module 27 is used to compare the fourth and fifth data, and outputs an error signal in response to the inconsistency of the comparison result.

[0075] The second preset conversion method is the opposite of the first preset conversion method. After writing the same data to the first memory module and the second memory module, when it is necessary to read this data, it is also necessary to read a set (including two copies) of the same data written in parallel from the first memory module and the second memory module in parallel. For distinction, the data read from the first memory module can be called the first read data, and the data read from the second memory module can be called the second read data. The first read data and the second read data are considered as a set of first data. The memory physical layer interface 23 converts the first read data and the second read data in each set of first data into third read data and fourth read data that meet the first protocol. The third read data and the fourth read data are considered as a set of second data. Each set of second data is transmitted to the first memory control module 22. For example, the memory physical layer interface can transmit the third read data and the fourth read data in parallel to the first memory control module 22 through two independent channels. The first memory control module 22 is used to convert each set of second data into third data that meets the second protocol supported by the second bit width conversion module 26. This conversion process is the opposite of the conversion process from the target data to be written to the first data to be written. It is necessary to combine at least one set of second data into third data according to a certain format. The second bit-width conversion module 26 performs bit-width conversion on the third data according to the second preset conversion method to obtain the fourth and fifth data. If no error occurs during data reading, the fourth and fifth data should be the same. The second bit-width conversion module 26 transmits the obtained fourth or fifth data to the processor and transmits the obtained fourth and fifth data to the read data verification module 27 for verification. The read data verification module 27 compares the fourth and fifth data. If the comparison result is inconsistent, an error signal is output. Since the read data reads the data written earlier, the fourth and fifth data in the read data process have the same bit width as the two original data to be written in the write data process. The third data in the read data process has the same bit width as the target data to be written in the write data process. The first read data and the second read data in the read data process have the same bit width as the data to be written in the fourth write access signal of the write data process. The third read data and the fourth read data in the read data process have the same bit width as the first data to be written in the write data process.

[0076] In one alternative embodiment, the representation of the error signal can be set according to actual needs, such as an output of 1 indicating an error has occurred, without any specific limitation.

[0077] In an optional example, the memory physical layer interface 23 converts a set of 16-bit first data (including first read data and second read data) read from the first memory module and the second memory module into a set of 16-bit second data (third read data and fourth read data) that meets the first protocol, and transmits it to the first memory control module 22. The first memory control module 22 needs to convert the 8 sets of second data transmitted by the memory physical layer interface 23 into 256-bit third data and transmit it to the second bit-width conversion module 26. The second bit-width conversion module 26 converts the third data into 128-bit fourth data and fifth data according to the second preset conversion method, wherein the fourth data comes from the first memory module and the fifth data comes from the second memory module.

[0078] In one optional embodiment, the error signal of this disclosure can be output to the error handling module in the intelligent driving chip, or it can be output to the processor, so as to handle the error in a timely manner, such as resetting the integrated circuit or issuing an alarm message to the user, etc. The specific settings can be set according to actual needs, and this disclosure does not limit them.

[0079] This embodiment compares the fourth and fifth data obtained by the second bit-width conversion module from the two memory modules respectively when reading data. When the comparison results are inconsistent, an error signal is output to handle the error in a timely manner, which effectively ensures the security of read data and enables memory read access to meet a high security level.

[0080] Figure 4 This is a schematic diagram of the structure of the read data verification module 27 provided in an exemplary embodiment of this disclosure.

[0081] In an optional embodiment, the read data verification module 27 includes: a preset number of XOR circuits 271 and OR circuits 272.

[0082] The two inputs of the nth XOR circuit 271 are the value of the nth bit of the fourth data and the value of the nth bit of the fifth data, respectively. Each XOR circuit 271 is used to output 1 when the two input values ​​are different and to output 0 when the two input values ​​are the same. The preset number is the same as the bit width of the fourth data.

[0083] The input terminal of the OR circuit 272 is connected to the output terminal of each XOR circuit 271 respectively, and the OR circuit 272 is used to output an error signal in response to the output of any XOR circuit 271 being 1.

[0084] The preset number can be set according to the bit width of the fourth data. For example, if the bit width of the fourth data is 128 bits, then 128 XOR circuits 271 can be set. The specific number is not limited.

[0085] In an alternative embodiment, the specific structure of the OR circuit 272 can be set according to actual needs. For example, the number of inputs to the OR circuit 272 can be set according to the number of XOR circuits 271, and the internal structure of the OR circuit 272 can be implemented by multiple OR logic devices.

[0086] This embodiment uses a preset number of XOR circuits and an OR circuit to perform bitwise comparison of the fourth and fifth data, and can output an error signal that the comparison result of any bit is inconsistent through a single output, which can effectively reduce the number of connection lines with other modules.

[0087] In an optional embodiment, the preset number can also be the same as the bit width of the first read data. In this case, the fourth and fifth data can be compared in groups. For example, if the bit width of the first read data is 16 bits, the read data verification module 27 can include 16 XOR circuits 271 and one OR circuit 272. Each 16 bits of the fourth data and the corresponding 16 bits of the fifth data are used as inputs to the read data verification module 27 for verification.

[0088] In an optional embodiment, the read data verification module 27 can also be implemented through a serial register and an XOR circuit or comparator. For example, the fourth data and the fifth data are stored in two serial registers respectively, and the two input terminals of the XOR circuit or comparator are connected to the two serial registers respectively. By controlling the two serial registers to serially input each bit to the XOR circuit, the nth bit of the fourth data and the nth bit of the fifth data are input to the XOR circuit for comparison. When the two are inconsistent, an error signal is output.

[0089] Figure 5 This is a schematic diagram of the structure of an integrated circuit for memory access provided in yet another exemplary embodiment of this disclosure.

[0090] In an optional embodiment, the integrated circuit disclosed herein further includes: a first delay module 28 and a second delay module 29.

[0091] The first delay module 28 is connected to the first memory control module 22 and the first comparison module 25 respectively, and is used to transmit each group of third write access signals output by the first memory control module 22 to the first comparison module 25 after a first time delay.

[0092] The second delay module 29 is connected to the first wide conversion module 21 and the second memory control module 24 respectively, and is used to delay the second write access signal output by the first wide conversion module 21 for a first time before transmitting it to the second memory control module 24.

[0093] The specific structures of the first delay module 28 and the second delay module 29 can be set according to actual needs, as long as the signal delay can be achieved, and there is no specific limitation. For example, the transmission time of the received signal can be controlled by a timer. The first time can be set according to actual needs, such as 1 clock cycle or 2 clock cycles, and there is no specific limitation. For the first memory control module 22, the first delay module 28 delays the time when the output result of the first memory control module 22 arrives at the first comparison module 25 after the first memory control module 22 has completed processing. For the second memory control module 24, the time when the second write access signal arrives at the second memory control module 24 is delayed before the second memory control module 24 processes, thereby realizing the time when the processing result of the second memory control module 24 arrives at the first comparison module 25. This ensures that the processing results of the two memory control modules can arrive at the first comparison module 25 at the same time, and ensures that the first memory control module 22 and the second memory control module 24 switch the same second write access signal at different times, avoiding the situation where the same error occurs when the two memory control modules work at the same time, which may lead to the error going undetected. For example, if the two memory control modules encounter the same error during processing, such as being simultaneously affected by some factors (e.g., electromagnetic interference), resulting in the obtained third write access signals of each group containing errors still being consistent with the fifth write access signals of each group, then the error cannot be detected after comparison by the first comparison module 25.

[0094] It should be noted that, in addition to delaying the transmission of each group of third write access signals output by the first memory control module 22 to the first comparison module 25 by a first time, the first delay module 28 can also delay any other signal output by the first memory control module 22 to the first comparison module 25 by a first time. Correspondingly, in addition to delaying the transmission of the second write access signal output by the first bit width conversion module 21 to the second memory control module 24 by a first time, the second delay module 29 can also delay any other signal that needs to be input to the second memory control module 24 by a first time. The specific delay can be set according to actual needs.

[0095] This embodiment effectively avoids the situation where the two memory control modules simultaneously experience the same error, thus preventing the error from going undetected, by delaying the signal of the first memory control module 22 and the second memory control module 24 at different stages, thereby further improving the security of memory access.

[0096] Figure 6 This is a schematic diagram of the structure of the memory physical layer interface 23 provided in an exemplary embodiment of this disclosure.

[0097] In an alternative embodiment, the memory physical layer interface 23 includes: a first channel 231, a second channel 232, a control unit 233, and a monitor 234.

[0098] The first channel 231 is used to transmit a fourth write access signal corresponding to each group of third write access signals to the first memory module corresponding to the first channel 231.

[0099] The second channel 232 is used to transmit another fourth write access signal corresponding to each group of third write access signals to the second memory module corresponding to the second channel 232.

[0100] The control unit 233 is connected to the first channel 231 and the second channel 232 respectively, and is used to generate the working clock and reset signal of the first channel 231 and the second channel 232.

[0101] Monitor 234, connected to control unit 233, is used to monitor the operating clock and / or reset signal, and outputs an alarm signal based on the monitoring results.

[0102] The first channel 231 and the second channel 232 are respectively connected to the first memory control module 22. The first channel 231 is also connected to the first memory module, and the second channel 232 is also connected to the second memory module. The first channel 231 converts one of the third write access signals in each group of third write access signals into a fourth write access signal that satisfies the memory protocol, and transmits the fourth write access signal to the first memory module. Similarly, the second channel 232 converts another third write access signal in each group of third write access signals into another fourth write access signal that satisfies the memory protocol, and transmits it to the second memory module. The operating clock is used to drive the first channel 231 and the second channel 232 to start working, and the reset signal is used to control the first channel 231 and the second channel 232 to reset the memory and the memory physical layer interface 23. The control unit 233 can be controlled by other modules of the intelligent driving chip, such as the processor and reset management module. The specific configuration can be tailored to actual needs. For example, when a fault occurs, the processor needs to reset the integrated circuit of this disclosure to handle the fault. It can send a reset command to the reset management module or directly to the control unit 233. The control unit 233 controls the first channel 231 and the second channel 232 to perform memory reset. The specific operating clock and reset control can be configured according to actual needs, and this disclosure does not impose any limitations. The monitor 234 can monitor the operating clock and / or reset signal of the control unit 233 in real time or periodically. When an error is detected in the operating clock and / or reset signal, or when preset conditions are not met, an alarm signal can be output to promptly detect problems and ensure the functional safety of the memory physical layer interface 23. For example, it can check whether the count value of the generated operating clock is within the expected range; if it is not within the expected range, an alarm signal is output. Alternatively, it can monitor whether an error has occurred in the reset signal; if the reset signal is triggered when the memory is working normally (e.g., pulled low to indicate a reset operation), an alarm signal is output.

[0103] In this embodiment, the memory physical layer interface uses two independent channels to convert and transmit two third write access signals of the same group. It stores the data from the two original sets of data to be written into two memory modules, thus storing the two identical sets of original data to be written into two memory modules respectively. This facilitates verification when reading data and ensures that memory access meets a high level of security.

[0104] In an optional embodiment, the first channel 231 is further configured to convert the first read data read from the first memory module into third read data that satisfies the first protocol and transmit it to the first memory control module 22. The second channel 232 is further configured to convert the second read data read from the second memory module into fourth read data that satisfies the first protocol and transmit it to the first memory control module 22. The first memory control module 22 is further configured to convert each third read data transmitted by the first channel 231 and each fourth read data transmitted by the second channel 232 into third data that satisfies the second protocol supported by the second bit-width conversion module 26, and transmit the third data to the second bit-width conversion module 26. The second bit-width conversion module 26 can perform bit-width conversion on the third data according to a second preset conversion method to obtain fourth data and fifth data, and transmit the fourth data to the processor. It also transmits the fourth data and fifth data to the read data verification module 27. The read data verification module 27 is configured to compare the fourth data and the fifth data, and output an error signal in response to the comparison result being inconsistent.

[0105] In one optional example, Figure 7 This is a schematic diagram of the structure of the memory physical layer interface 23 provided in another exemplary embodiment of this disclosure. In this diagram, monitor represents a monitor 234, clock represents the operating clock, reset represents the reset signal, MASTER represents a control unit 233, DDR channel A and DDR channel B represent two channels of dual-channel memory (e.g., dual-channel SDRAM). The first channel 231 and the second channel 232 have the same structure, both including three channels: DQ, DQ, and AC. DQ represents the data channel, used for transmitting data, and AC represents the address / command channel, used for transmitting addresses and commands.

[0106] In an optional embodiment, the first width conversion module 21 is specifically used for:

[0107] The original data to be written, included in the first write access signal, is divided into two identical copies, each corresponding to a portion of the original data, with the first bit width as the granularity. These two identical copies are then used as two consecutive target data portions with the first bit width being the same as the data bit width supported by the first protocol. The target data corresponding to each portion of the original data is then determined according to the order of the original data portions in the original data to be written. The control signal in the first write access signal, which represents the length of the original data to be written, is converted into a signal representing the length of the target data to be written, thus obtaining the target control signal. Based on the target data to be written and the target control signal, the second write access signal is determined.

[0108] In one optional example, Figure 8 This is a schematic diagram illustrating the conversion principle from original data to target data to be written, provided in an exemplary embodiment of this disclosure. Here, Byte represents a byte, 1 Byte = 8 bits, and bit represents a bit position; for example, Byte0 includes 8 bits from bit0 to bit7. In this example, the first bit width is 16 bits. For the original data to be written in the first write access signal, with a granularity of 16 bits, the original data corresponding to each first bit width (e.g., Byte0 and Byte1) is copied into two identical copies. These two identical copies are used as the target data for two consecutive first bit widths. Then, the target data corresponding to each of the original data portions (a total of 8 original data portions) is combined according to the order of the original data portions in the original data to be written to obtain the target data to be written.

[0109] In one optional example, Figure 9 This is a schematic diagram of an integrated circuit for memory access provided in yet another exemplary embodiment of this disclosure. The specific working principles of each part are described above and will not be repeated here.

[0110] In an optional embodiment, since the conversion function of the first bit width conversion module 21 and the conversion function of the second bit width conversion module 24 are opposite conversions, they can be implemented using a single bit width conversion module in practical applications. For example, Figure 10This is a schematic diagram of an integrated circuit for memory access provided in another exemplary embodiment of this disclosure. In this example, the bit width of the original data to be written is 128 bits. The bit width conversion module can realize the functions of the first bit width conversion module 21 and the second bit width conversion module 24 mentioned above. When writing data, the bit width conversion module converts the first write access signal of the 128-bit original data to be written into target data to be written, including two copies of the original data to be written, with a bit width of 256 bits, through the conversion of the AXI (Advanced Dextensible Interface) protocol. When reading data, the bit width conversion module converts the 256-bit third data transmitted by the first memory control module 22 into 128-bit fourth and fifth data through the conversion of the AXI protocol, and transmits one of them to the processor. In this case, the read data verification module 27 can also be set in the bit width conversion module to verify the converted fourth and fifth data. The AXI protocol is a bus protocol in which the address / control (or command) and data phases are separated, and it supports unaligned data transmission. The specific principle will not be elaborated here.

[0111] In one optional example, Figure 11 This is a schematic diagram illustrating the conversion principle from third data to fourth data provided in an exemplary embodiment of this disclosure. In this example, the third data width is 256 bits, and the 256-bit third data is converted to 128 bits. In the third data, the remaining bytes besides those constituting the fourth data form the fifth data. The principle of the fifth data is the same as that of the fourth data, and will not be repeated here.

[0112] Any module or unit in this example can be implemented using hardware or software. To ensure real-time performance, hardware logic circuits can be used.

[0113] In an optional example, in order to ensure the real-time performance of the device, all the modules, units under each module and sub-units under each unit of the device disclosed herein are implemented using hardware logic circuits, thereby effectively reducing hardware overhead and power consumption while ensuring real-time performance.

[0114] The various embodiments and optional examples disclosed herein can be implemented individually or in any combination without conflict, and can be set according to actual needs.

[0115] Exemplary Method

[0116] Figure 12 This is a schematic flowchart illustrating a memory access processing method provided in an exemplary embodiment of this disclosure. This method can be implemented using any of the memory access integrated circuits described above. Figure 12 As shown, the method disclosed herein may include the following steps:

[0117] Step 301: Convert the original data to be written in the processor's first write access signal into target data to be written, which includes two original data to be written, according to the first preset conversion method, and determine the converted second write access signal based on the target data to be written.

[0118] Step 302: Convert the target data to be written in the second write access signal into at least one set of first data to be written that satisfies the first protocol supported by the memory physical layer interface. Determine a corresponding set of third write access signals based on each set of first data to be written. Each set of first data to be written includes two identical sets of first data to be written from two original sets of data to be written. Each set of third write access signals includes two third write access signals.

[0119] Step 303: Convert each group of third write access signals into two fourth write access signals that satisfy the memory protocol, and transmit each fourth write access signal to its corresponding memory module.

[0120] The specific operations of each step of the method disclosed herein have been described in detail in the foregoing integrated circuit embodiments, and will not be repeated here.

[0121] Figure 13 This is a flowchart illustrating a processing method for memory access provided in another exemplary embodiment of this disclosure.

[0122] In an optional embodiment, the method of this disclosure further includes:

[0123] Step 401: Convert the target data to be written in the second write access signal into at least one set of second data to be written that satisfies the first protocol supported by the memory physical layer interface. Determine a corresponding set of fifth write access signals based on each set of second data to be written. Each set of second data to be written includes two identical sets of second data to be written from two original sets of data to be written. Each set of fifth write access signals includes two fifth write access signals.

[0124] Step 402: Compare the third write access signal of each group with the fifth write access signal of each group. If the comparison result is inconsistent, output an error signal.

[0125] Figure 14 This is a schematic diagram of the read data process for memory access provided in an exemplary embodiment of this disclosure.

[0126] In an optional embodiment, the method of this disclosure further includes:

[0127] Step 501: Obtain at least one set of first data from the first memory module and the second memory module respectively, and convert each set of first data in the at least one set of first data into a set of second data that satisfies the first protocol. Each set of first data includes first read data and second read data, and each set of second data includes third read data corresponding to the first read data and fourth read data corresponding to the second read data.

[0128] Step 502: Convert each group of second data into third data that satisfies the second protocol.

[0129] Step 503: Perform bit-width conversion on the third data according to the second preset conversion method to obtain the fourth data and the fifth data, and transfer the fourth data to the processor.

[0130] Step 504: Compare the fourth data and the fifth data. If the comparison result is inconsistent, output an error signal.

[0131] In an optional embodiment, step 504 includes: comparing the value of the nth bit of the fourth data with the value of the nth bit of the fifth data, and outputting an error signal in response to a difference in the comparison result of either bit.

[0132] Figure 15 This is a flowchart illustrating a processing method for memory access provided in yet another exemplary embodiment of this disclosure.

[0133] In an optional embodiment, the method of this disclosure further includes:

[0134] Step 610: Delay the third write access signal of each group for a certain period of time before proceeding to the next step.

[0135] Step 620: Delay the second write access signal for a certain period of time before proceeding to the next step.

[0136] In an optional embodiment, step 303 includes:

[0137] Transmit one fourth write access signal corresponding to each group of third write access signals to the first memory module; transmit another fourth write access signal corresponding to each group of third write access signals to the second memory module.

[0138] In an optional embodiment, step 303 includes:

[0139] A working clock is generated to trigger the execution of the steps of transmitting a fourth write access signal corresponding to each group of third write access signals to the first memory module, and transmitting another fourth write access signal corresponding to each group of third write access signals to the second memory module.

[0140] In an optional embodiment, step 303 further includes:

[0141] When a reset is required for the first memory module and / or the second memory module, a reset signal is generated and transmitted to the first memory module and / or the second memory module.

[0142] In an optional embodiment, step 303 further includes:

[0143] Monitor the operating clock and / or reset signal, and output an alarm signal based on the monitoring results.

[0144] In an optional embodiment, step 301 is specifically used for:

[0145] The original data to be written, including the first write access signal, is divided into two identical copies of the original data corresponding to each first bit width, with the first bit width as the granularity. These two identical copies are used as the target data of two consecutive first bit widths, with the first bit width being the same as the data bit width supported by the first protocol. The target data corresponding to each part of the original data is determined according to the order of each part of the original data in the original data to be written.

[0146] The control signal in the first write access signal, which represents the length of the original data to be written, is converted into a signal representing the length of the target data to be written, to obtain the target control signal; based on the target data to be written and the target control signal, the second write access signal is determined.

[0147] Any of the memory access processing methods provided in this disclosure can be executed by any suitable device with data processing capabilities, including but not limited to: terminal devices and servers. Alternatively, any of the memory access processing methods provided in this disclosure can be executed by a processor, such as by a processor executing any of the memory access processing methods mentioned in this disclosure by calling corresponding instructions stored in memory. Alternatively, any of the methods provided in this disclosure can be executed by a hardware logic circuit device. Further details will not be elaborated below.

[0148] Exemplary Electronic Device

[0149] This disclosure also provides an electronic device, including: a memory for storing computer programs;

[0150] A processor is configured to execute a computer program stored in the memory, wherein, when the computer program is executed, it implements the method described in any of the above embodiments of the present disclosure.

[0151] Alternatively, the electronic device may include means (i.e., an integrated circuit for memory access) as provided in any of the above embodiments to implement the methods described in any of the above embodiments of this disclosure.

[0152] In this device, at least one module is implemented by hardware logic circuitry; or, at least one unit in at least one module is implemented by hardware logic circuitry.

[0153] To improve real-time performance, each module, each unit under each module, and each sub-unit under each unit in the device are implemented through hardware logic circuits, meaning the entire device is a hardware logic circuit.

[0154] Figure 16 This is a schematic diagram of an application embodiment of the electronic device disclosed herein. In this embodiment, the electronic device 10 includes one or more processors 11 and a memory 12.

[0155] The processor 11 may be a central processing unit (CPU) or other form of processing unit with data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device 10 to perform desired functions.

[0156] The memory 12 may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory may include, for example, random access memory (RAM) and / or cache memory. The non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more computer program instructions may be stored on the computer-readable storage medium, and the processor 11 may execute the program instructions to implement the methods of the various embodiments of this disclosure described above and / or other desired functions. Various contents such as input signals, signal components, and noise components may also be stored in the computer-readable storage medium.

[0157] In one example, the electronic device 10 may also include an input device 13 and an output device 14, which are interconnected via a bus system and / or other forms of connection mechanism (not shown).

[0158] For example, the input device 13 can be the microphone or microphone array described above, used to capture the input signal of the sound source; the input device 13 can also be an image acquisition sensor, such as a camera, used to acquire image data.

[0159] In addition, the input device 13 may also include, for example, a keyboard, a mouse, etc.

[0160] The output device 14 can output various information to the outside, including determined distance information, direction information, etc. The output device 14 may include, for example, a display, a speaker, a printer, and a communication network and its connected remote output devices, etc.

[0161] Of course, for the sake of simplicity, Figure 16 Only some of the components of the electronic device 10 relevant to this disclosure are shown, omitting components such as buses, input / output interfaces, etc. In addition, the electronic device 10 may include any other suitable components depending on the specific application.

[0162] In an alternative embodiment, an electronic device may also be provided, comprising an integrated circuit for memory access as provided in any of the foregoing embodiments or examples, and may also include other related devices, which will not be described in detail here. At least one module in the integrated circuit is implemented via hardware logic circuitry; or, at least one unit in at least one module is implemented via hardware logic circuitry.

[0163] Exemplary Computer Program Product and Computer-Readable Storage Medium

[0164] In addition to the methods and apparatus described above, embodiments of this disclosure may also be computer program products comprising computer program instructions that, when executed by a processor, cause the processor to perform the steps of the methods according to various embodiments of this disclosure as described in the "Exemplary Methods" section above.

[0165] The computer program product can be written in any combination of one or more programming languages ​​to perform the operations of the embodiments of this disclosure. The programming languages ​​include object-oriented programming languages ​​such as Java and C++, as well as conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on a user's computing device, partially on a user's computing device, as a standalone software package, partially on a user's computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0166] Furthermore, embodiments of this disclosure may also be computer-readable storage media having computer program instructions stored thereon, which, when executed by a processor, cause the processor to perform the steps in the methods according to various embodiments of this disclosure described in the "Exemplary Methods" section above.

[0167] The storage medium disclosed herein may also store data that needs to be stored by at least one hardware logic circuit of the protection device for the image data processing module provided in the "Exemplary Device" section of this specification, so that the hardware logic circuit can perform the corresponding function during operation. For example, the storage medium may be a register of the hardware logic circuit, storing initialization configuration data, or storing data that needs to be stored during operation, without specific limitations. The at least one hardware logic circuit may be a hardware logic circuit of a module in the device, a hardware logic circuit of a unit under a module, or a hardware logic circuit of a sub-unit under a unit, without specific limitations.

[0168] The computer-readable storage medium may be any combination of one or more readable media. A readable medium may be a readable signal medium or a readable storage medium. A readable storage medium may, for example, include, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatuses, or devices, or any combination thereof. More specific examples of readable storage media (a non-exhaustive list) include: electrical connections having one or more wires, portable disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0169] The basic principles of this disclosure have been described above with reference to specific embodiments. However, it should be noted that the advantages, benefits, and effects mentioned in this disclosure are merely examples and not limitations, and should not be considered as essential features of each embodiment of this disclosure. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations. These details do not limit the scope of this disclosure to the necessity of employing the aforementioned specific details for implementation.

[0170] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For system embodiments, since they largely correspond to method embodiments, the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

[0171] The block diagrams of devices, apparatuses, devices, and systems disclosed herein are merely illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, devices, and systems can be connected, arranged, and configured in any manner. Words such as “comprising,” “including,” “having,” etc., are open-ended terms meaning “including but not limited to,” and are used interchangeably with them. The terms “or” and “and” as used herein refer to the terms “and / or,” and are used interchangeably with them unless the context clearly indicates otherwise. The term “such as” as used herein refers to the phrase “such as but not limited to,” and is used interchangeably with it.

[0172] The apparatus and methods of this disclosure may be implemented in many ways. For example, they may be implemented by software, hardware, firmware, or any combination of software, hardware, and firmware. The above-described order of steps for the methods is for illustrative purposes only, and the steps of the methods of this disclosure are not limited to the order specifically described above unless otherwise specifically stated. Furthermore, in some embodiments, this disclosure may also be implemented as a program recorded on a recording medium, the program including machine-readable instructions for implementing the methods according to this disclosure. Thus, this disclosure also covers recording media storing programs for performing the methods according to this disclosure.

[0173] It should also be noted that in the apparatus, devices, and methods of this disclosure, the components or steps can be disassembled and / or recombined. These disassemblies and / or recombinations should be considered as equivalent solutions to this disclosure.

[0174] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of this disclosure. Therefore, this disclosure is not intended to be limited to the aspects shown herein, but rather to be carried out within the widest scope consistent with the principles and novel features disclosed herein.

[0175] The above description has been given for purposes of illustration and description. Furthermore, this description is not intended to limit the embodiments of this disclosure to the forms disclosed herein. Although numerous exemplary aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations therein.

Claims

1. An integrated circuit for memory access, comprising: The first wide conversion module is used to copy the original data to be written in the processor's first write access signal into two copies according to the first preset conversion method, and to combine the two copies of the original data to be written into target data to be written according to the preset format, and to determine the converted second write access signal based on the target data to be written. The first memory control module, connected to the first bit-width conversion module, is used to convert the target data to be written in the second write access signal into at least one set of first data to be written that satisfies the first protocol supported by the memory physical layer interface, and to determine a corresponding set of third write access signals based on each set of first data to be written. Each set of first data to be written includes two identical sets of first data to be written from two sets of the original data to be written, and each set of third write access signals includes two third write access signals. The memory physical layer interface is connected to the first memory control module and is used to convert each group of the third write access signals into two fourth write access signals that satisfy the memory protocol, and to transmit each of the fourth write access signals to the memory module corresponding to each of the fourth write access signals.

2. The integrated circuit according to claim 1, further comprising: The second memory control module, connected to the first bit-width conversion module, is used to convert the target data to be written in the second write access signal into at least one set of second data to be written that satisfies the first protocol supported by the memory physical layer interface, and to determine a corresponding set of fifth write access signals based on each set of second data to be written. Each set of second data to be written includes two identical sets of second data to be written from two sets of the original data to be written, and each set of fifth write access signals includes two fifth write access signals. The first comparison module is connected to the first memory control module and the second memory control module respectively, and is used to compare the third write access signal of each group with the fifth write access signal of each group, and output an error signal in response to the inconsistency of the comparison result.

3. The integrated circuit according to claim 2, further comprising: The second bit-width conversion module and the read data verification module; The memory physical layer interface is further configured to obtain at least one set of first data from the first memory module and the second memory module respectively, convert each set of first data in the at least one set of first data into a set of second data that satisfies the first protocol, and transmit each set of second data to the first memory control module. Each set of first data includes first read data and second read data, and each set of second data includes third read data corresponding to the first read data and fourth read data corresponding to the second read data. The first memory control module is further configured to convert each group of the second data into third data that satisfies the second protocol supported by the second bit-width conversion module, and transmit the third data to the second bit-width conversion module; The second bit-width conversion module is used to perform bit-width conversion on the third data according to the second preset conversion method to obtain the fourth data and the fifth data, and to transmit the fourth data to the processor; The read data verification module is used to compare the fourth data and the fifth data, and output an error signal in response to the comparison result being inconsistent.

4. The integrated circuit according to claim 3, wherein, The read data verification module includes: A preset number of XOR circuits are provided. The two inputs of the nth XOR circuit are the value of the nth bit of the fourth data and the value of the nth bit of the fifth data, respectively. Each XOR circuit is used to output 1 when the two input values ​​are different and to output 0 when the two input values ​​are the same. The preset number is the same as the bit width of the fourth data. The input terminal of the OR circuit is connected to the output terminal of each of the XOR circuits. The OR circuit is used to output an error signal in response to the output of any XOR circuit being 1.

5. The integrated circuit according to claim 2, further comprising: The first delay module is connected to the first memory control module and the first comparison module respectively, and is used to transmit each group of the third write access signals output by the first memory control module to the first comparison module after a first time delay. The second delay module is connected to the first bit-width conversion module and the second memory control module respectively, and is used to transmit the second write access signal output by the first bit-width conversion module to the second memory control module after delaying it by the first time.

6. The integrated circuit according to claim 1, wherein, The memory physical layer interface includes: The first channel is used to transmit a fourth write access signal corresponding to each group of the third write access signals to the first memory module corresponding to the first channel. The second channel is used to transmit another fourth write access signal corresponding to each group of the third write access signals to the second memory module corresponding to the second channel. The control unit is connected to the first channel and the second channel respectively, and is used to generate the operating clock and reset signal for the first channel and the second channel. A monitor, connected to the control unit, is used to monitor the operating clock and / or reset signal, and outputs an alarm signal based on the monitoring results.

7. The integrated circuit according to claim 1, wherein, The first bit-width conversion module is specifically used for: The original data to be written, included in the first write access signal, is copied into two identical copies of the original data corresponding to each first bit width, with the first bit width as the granularity. These two identical copies are used as the target data of two consecutive first bit widths. The first bit width is the same as the fixed data bit width supported by the first protocol. The target data corresponding to each part of the original data is determined according to the order of each part of the original data in the original data to be written; The control signal in the first write access signal, which represents the length of the original data to be written, is converted into a signal representing the length of the target data to be written, to obtain the target control signal; Based on the target data to be written and the target control signal, the second write access signal is determined.

8. A method for processing memory access, comprising: According to the first preset conversion method, the original data to be written in the processor's first write access signal is copied into two copies, and the two copies of the original data to be written are combined into target data to be written according to a preset format. The converted second write access signal is determined based on the target data to be written. The target data to be written in the second write access signal is converted into at least one set of first data to be written that satisfies the first protocol supported by the memory physical layer interface. A corresponding set of third write access signals is determined based on each set of first data to be written. Each set of first data to be written includes two identical sets of first data to be written from two sets of the original data to be written. Each set of third write access signals includes two third write access signals. Each group of third write access signals is converted into two fourth write access signals that satisfy the memory protocol, and each fourth write access signal is transmitted to the memory module corresponding to each fourth write access signal.

9. A computer-readable storage medium storing a computer program for performing the memory access processing method of claim 8; or, The storage medium is used to store data that needs to be stored by at least one hardware logic circuit of the integrated circuit for memory access as described in any one of claims 1-7, so that the hardware logic circuit can perform the corresponding function when it is working.

10. An electronic device, the electronic device comprising: processor; Memory used to store the processor's executable instructions; The processor is configured to read the executable instructions from the memory and execute the instructions to implement the processing method for memory access as described in claim 8. or, The electronic device includes an integrated circuit for memory access as described in any one of claims 1-7; At least one module in the integrated circuit for memory access is implemented through hardware logic circuits.

Images