Method, device and related products for drawing pixel circuit layout

Abstract

The present application discloses a method, device and related products for drawing a pixel circuit layout, and the method includes: an index calculation step, which determines whether a first pixel circuit layout needs to be used as a target pixel circuit layout to be optimized; a parameter adjustment step, which adjusts the layout graphic input parameters according to the mapping relationship between the expected result index and the layout graphic input parameters, so as to adjust the optimized layout characteristics of the layout graphic parameter unit accordingly, so as to draw a layout on the basis of the target pixel circuit layout to be optimized to obtain a second pixel circuit layout, and determine whether the second pixel circuit layout needs to be used as a new target pixel circuit layout to be optimized; if so, draw a layout on the basis of the new target pixel circuit layout to obtain a new second pixel circuit layout, and execute the index calculation step to determine whether the new second pixel circuit layout needs to be optimized, until the result index of the new second pixel circuit layout meets the design index.

Description

Technical Field

[0001] The present application belongs to the field of circuit design technology, and in particular, relates to a method and device for drawing a pixel circuit layout and related products. Background Art

[0002] In the design of pixel circuit layout, it is necessary to perform multiple iterations to adjust the devices, connections, layout graphics, etc. in the pixel circuit layout to achieve all design goals. Since each iteration takes several hours to several days, the time-consuming cost of pixel circuit layout design is relatively high. Summary of the invention

[0003] The present application provides a method and device for drawing a pixel circuit layout and related products to overcome or alleviate the defects of the prior art.

[0004] A method for drawing a pixel circuit layout, comprising:

[0005] An index calculation step, which includes calculating the result index of the created first pixel circuit layout and comparing it with the design index to determine whether the first pixel circuit layout needs to be used as a target pixel circuit layout to be optimized;

[0006] A parameter adjustment step, comprising: in response to the need to re-optimize the target pixel circuit layout, adjusting the layout graphic input parameter accordingly according to the mapping relationship between the expected result index and the layout graphic input parameter, so as to correspondingly adjust the optimized layout feature of the layout graphic parameter unit, so as to perform layout drawing on the basis of the target pixel circuit layout to be optimized to obtain a second pixel circuit layout, wherein each layout graphic on the first pixel circuit layout is abstracted into one of the layout graphic parameter units;

[0007] Jump to the index calculation step to calculate the result index of the second pixel circuit layout, and compare it with the design index to determine whether the second pixel circuit layout needs to be used as a new target pixel circuit layout to be optimized;

[0008] If so, jump to the parameter adjustment step to perform layout drawing on the basis of the new target pixel circuit layout to obtain a new second pixel circuit layout, and execute the index calculation step to determine whether the new second pixel circuit layout needs to be optimized until the result index of the new second pixel circuit layout meets the design index;

[0009] If not, the optimization of the second pixel circuit layout is terminated.

[0010] A device for drawing a pixel circuit layout, comprising:

[0011] An index calculation unit, which is used to calculate the result index of the created first pixel circuit layout, and compare it with the design index to determine whether the first pixel circuit layout needs to be used as a target pixel circuit layout to be optimized;

[0012] A parameter adjustment unit, which is used to respond to the need to re-optimize the target pixel circuit layout, and adjust the layout graphic input parameters accordingly according to the mapping relationship between the expected result indicators and the layout graphic input parameters, so as to adjust the optimized layout characteristics of the layout graphic parameter unit accordingly, so as to perform layout drawing on the basis of the target pixel circuit layout to be optimized to obtain a second pixel circuit layout;

[0013] Calling the index calculation unit to calculate the result index of the second pixel circuit layout, and comparing it with the design index to determine whether the second pixel circuit layout needs to be used as a new target pixel circuit layout to be optimized;

[0014] If so, calling the parameter adjustment unit to perform layout drawing on the basis of the new target pixel circuit layout to obtain a new second pixel circuit layout, and executing the index calculation step to determine whether the new second pixel circuit layout needs to be optimized until the result index of the new second pixel circuit layout meets the design index;

[0015] If not, the optimization of the second pixel circuit layout is terminated.

[0016] 10. An electronic device, characterized in that the electronic device comprises a memory and a processor, the memory is used to store a computer executable program, and the processor is used to run the computer executable program to implement any one of the methods of claims 1-8.

[0017] In the technical solution provided by the present application, through the indicator calculation step, it includes calculating the result indicator of the first pixel circuit layout created, and comparing it with the design indicator to determine whether the first pixel circuit layout needs to be used as the target pixel circuit layout to be optimized; the parameter adjustment step includes responding to the need to re-optimize the target pixel circuit layout, according to the mapping relationship between the expected result indicator and the layout graphic input parameter, correspondingly adjusting the layout graphic input parameter, so as to correspondingly adjust the optimized layout characteristics of the layout graphic parameter unit, so as to draw the layout on the basis of the target pixel circuit layout to be optimized to obtain the second pixel circuit layout, and each layout graphic on the first pixel circuit layout is abstracted into a layout graphic parameter unit; jumping to the indicator calculation step to calculate the result indicator of the second pixel circuit layout, and comparing it with the design indicator to determine whether the second pixel circuit layout needs to be re-optimized.

[0018] The circuit layout is used as the new target pixel circuit layout to be optimized; if yes, jump to the parameter adjustment step to draw the layout on the basis of the new target pixel circuit layout to obtain a new second pixel circuit layout, and execute the

[0019] The index calculation step is performed to determine whether the new second pixel circuit layout needs to be optimized until the result index of the new second pixel circuit layout meets the design index; if not, the optimization of the second pixel circuit layout is terminated, thereby realizing the automated iterative design of the pixel circuit layout design and reducing the time-consuming cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 A schematic flow chart of a method for drawing a pixel circuit layout according to an embodiment of the present application.

[0021] Figure 2 A schematic diagram of the structure of a device for drawing a pixel circuit layout according to an embodiment of the present application.

[0022] Figure 3A FIG5 is a schematic diagram showing the result of applying the above technical solution of the embodiment of the present application to a first pixel circuit layout.

[0023] Figure 3B A partial schematic diagram of the result of applying the above technical solution of the embodiment of the present application to a first pixel circuit layout. DETAILED DESCRIPTION

[0024] The technical solutions in the embodiments of the present application will be described in detail below in conjunction with the accompanying drawings in the embodiments of the present application.

[0025] Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field are within the scope of protection of the present application.

[0026] The terms "first", "second" and the like in the specification and claims of this application are used to distinguish similar pairs.

[0027] It should be understood that the numerals used in this manner are interchangeable where appropriate, so that the embodiments of the present application can be implemented in sequences other than those illustrated or described herein, and that “first order” is used to represent the sequence of events, and “second order” is used to describe the sequence of events.

[0028] The objects distinguished by "first", "second", etc. are usually of one type, and the number of objects is not limited. For example, the first object can be one or more. In addition, "and / or" in the specification and claims means at least one of the connected objects, and the character " / " generally means that the related objects are in an "or" relationship.

[0029] Figure 1 FIG. 1 is a flow chart of a method for drawing a pixel circuit layout according to an embodiment of the present application. Figure 1 As shown, it includes:

[0030] S101, an index calculation step, which includes calculating the result index of the created first pixel circuit layout, and comparing it with the design index to determine whether the first pixel circuit layout needs to be used as a target pixel circuit layout to be optimized;

[0031] In this embodiment, the above index calculation step is implemented, for example, by an index calculator.

[0032] S102, a parameter adjustment step, comprising: in response to the need to re-optimize the target pixel circuit layout, adjusting the layout graphic input parameter accordingly according to the mapping relationship between the expected result index and the layout graphic input parameter, so as to correspondingly adjust the optimized layout feature of the layout graphic parameter unit, so as to perform layout drawing on the basis of the target pixel circuit layout to be optimized to obtain a second pixel circuit layout;

[0033] Jump to the index calculation step to calculate the result index of the second pixel circuit layout, and compare it with the design index to determine whether the second pixel circuit layout needs to be used as a new target pixel circuit layout to be optimized;

[0034] If so, jump to the parameter adjustment step to perform layout drawing on the basis of the new target pixel circuit layout to obtain a new second pixel circuit layout, and execute the index calculation step to determine whether the new second pixel circuit layout needs to be optimized until the result index of the new second pixel circuit layout meets the design index;

[0035] If not, the optimization of the second pixel circuit layout is terminated.

[0036] In this embodiment, the layout graphic input parameters may be adjusted through a parameter generator.

[0037] Optionally, the method further comprises:

[0038] The parsing step includes: parsing the created original pixel circuit layout to determine the layout pattern thereon;

[0039] The abstraction step includes: abstracting each of the layout graphics into a layout graphic parameterized unit, each of the layout graphic parameter units having a corresponding layout graphic input parameter.

[0040] In this embodiment, taking into account the influence of photo-simulation on the pixel circuit and the influence of process conditions on the device, all layout elements on the pixel circuit layout are regarded as layout graphics, so that each layout graphic is abstracted into a layout graphic parameterized unit, thereby meeting the high-precision requirements when designing the pixel circuit.

[0041] Exemplarily, each layout graphic may be abstracted into a layout graphic parameterized unit by performing parameterized programming on it.

[0042] The layout graphic input parameters include but are not limited to: device-related parameters, such as but not limited to device electrical parameters, device offset or offset angle relative to a reference, device position parameters, device shape parameters, and parameters of graphics contained in the device; wiring-related parameters, including but not limited to minimum line width, maximum line width, minimum spacing, maximum spacing, spacing between different metal layers, and nested boundary distance between graphics of different metal layers; graphic-related parameters, including but not limited to position parameters, shape parameters, angle parameters, chamfer parameters, offset and angle relative to a reference object, etc.

[0043] Optionally, the method further comprises:

[0044] The initial layout optimization step includes: adjusting the initial layout features of the layout graphic parameter unit on the first pixel circuit layout;

[0045] A parameter adjustment step includes responding to the need to re-optimize the target pixel circuit layout, adjusting the layout graphic input parameters accordingly based on the mapping relationship between the desired result indicators and the layout graphic input parameters, taking the initial layout features as a reference, and correspondingly adjusting the optimized layout features of the layout graphic parameter unit, so as to draw a layout based on the target pixel circuit layout to be optimized to obtain a second pixel circuit layout.

[0046] Optionally, in the parameter adjustment step, the initial layout feature is used as a reference to further determine the direction of parameter adjustment according to the initial layout feature, so as to adjust the layout graphic input parameter accordingly.

[0047] By adjusting the initialization layout features, when executing the solution of the embodiment of the present application, the initialization layout features are as close as possible to the optimized layout features, thereby shortening the processing time of layout optimization, quickly realizing layout optimization, and ensuring that the result indicators meet the requirements of the design goals.

[0048] For example, if a capacitor is stretched laterally to make it larger, the direction of parameter adjustment is: in the direction of larger capacitance value, larger lateral size of the capacitor, etc. Otherwise, the search for small capacitance value is reduced.

[0049] Optionally, in the parameter adjustment step, based on the artificial intelligence model, the layout graphic input parameters are adjusted accordingly according to the mapping relationship between the expected result indicators and the layout graphic input parameters.

[0050] Optionally, the method further comprises:

[0051] Generate model training samples in real time to perform real-time training on the artificial intelligence model based on the training samples, wherein the model training samples include: the result indicators calculated in the indicator calculation step and the layout graphic input parameters obtained in the parameter adjustment step.

[0052] In the generation of model training samples, the most difficult part is to manually specify the input parameters of the layout graphic parameter unit. However, since there are so many input parameters, often more than 100, the parameter search space is very large. Generally speaking, the layout graphic is determined by n input parameters. Each layout graphic input parameter has a value range located on a continuous domain. Assuming that when determining the layout graphic input parameter, m samples are taken within the value range, then the search space complexity generated by the layout graphic input parameter is m. n Even for a relatively small module, such as a simple trigger, the number of parameters can reach dozens or even hundreds. Assuming there are only 50 parameters, and the number of samples for each input parameter is 1000, then the search space also reaches 1000. 50 It is impossible and unnecessary to manually search one by one to find feasible solutions in such a huge space. Therefore, the method of generating model training samples in real time automatically optimizes the input parameters.

[0053] Exemplarily, a series of input parameters can also be automatically generated based on the model training sampler to form an automatically changing parameter value combination, which is added to the above training sample. Further, a value is randomly selected for each parameter each time to form an input parameter value list, corresponding to a result indicator list, which together form a training sample.

[0054] If the artificial intelligence model is not used, in order to adjust the layout design, each time the above parameters are manually modified, DRC, RC extraction, simulation, waveform drawing, and indicator extraction must be run, which takes an average of 15 minutes.

[0055] Exemplarily, the mapping relationship between the result index and the layout graphic input parameter can be obtained by collecting historical data and using these historical data as training sample data to train the artificial intelligence model, so that the artificial intelligence model has model parameters that meet the requirements, so that when executing the solution of this application, the layout graphic input parameter is input to quickly determine the result index. Or, based on the way in which the result index is closest to the design index, based on the determined result index, according to the mapping relationship, the corresponding layout graphic input parameter is determined.

[0056] Artificial intelligence models are generally implemented through a neural network, with input parameters as the input of the neural network and result indicators as the output, and a large number of weights in the network are trained. After training, the weights tend to be stable. At this time, the neural network reflects the functional relationship between the input parameters and result indicators reflected by countless samples.

[0057] The historical data collected here can be collected offline or online. When collecting online, that is, when executing the solution of the embodiment of the present application, the mapping relationship between the result indicators and the layout graphic input parameters is added to the training sample data as new historical data.

[0058] Optionally, the method further comprises: a layout feature saving step, comprising storing the optimized layout feature obtained by obtaining the second pixel circuit layout into a layout feature table;

[0059] In the index calculation step, the optimized layout feature is obtained from the layout feature table, so as to calculate the result index of the second pixel circuit layout according to the optimized layout feature.

[0060] Target indicators include compliance with design rules. Design rules include: process geometry rules, such as minimum line width and line spacing. Target indicators also include layout geometry and electrical performance indicators, such as the peak voltage of the output signal and the charging rate of key pixels in the driven pixel array.

[0061] A typical indicator calculation process includes using a geometry rule checking tool to calculate whether the pixel circuit layout violates the geometry rules, using a parasitic resistance and capacitance calculation tool to calculate the parasitic resistance and capacitance and generate a post-layout netlist with parasitic resistance and capacitance, using a simulation tool to simulate the post-layout netlist to generate the output signal waveform of the layout circuit, and using a waveform calculation tool to extract various feature data from the waveform to obtain indicators. Generally speaking, all result indicators must simultaneously meet their respective expected value ranges (i.e., the requirements of the target indicators) to prove that the pixel layout has achieved the design goal.

[0062] Optionally, the first pixel circuit layout and the second pixel circuit layout are both pixel circuit layouts, which can be specifically used in flat panel displays and the like.

[0063] Figure 2 FIG. 1 is a schematic diagram of a device for drawing a pixel circuit layout according to an embodiment of the present application. Figure 2 As shown, it includes:

[0064] An index calculation unit 201, which is used to calculate the result index of the created first pixel circuit layout, and compare it with the design index to determine whether the first pixel circuit layout needs to be used as a target pixel circuit layout to be optimized;

[0065] A parameter adjustment unit 202, which is used to respond to the need to re-optimize the target pixel circuit layout, and adjust the layout graphic input parameters accordingly according to the mapping relationship between the expected result indicators and the layout graphic input parameters, so as to adjust the optimized layout characteristics of the layout graphic parameter unit accordingly, so as to perform layout drawing on the basis of the target pixel circuit layout to be optimized to obtain a second pixel circuit layout;

[0066] Calling the index calculation unit to calculate the result index of the second pixel circuit layout, and comparing it with the design index to determine whether the second pixel circuit layout needs to be used as a new target pixel circuit layout to be optimized;

[0067] If so, calling the parameter adjustment unit to perform layout drawing on the basis of the new target pixel circuit layout to obtain a new second pixel circuit layout, and executing the index calculation step to determine whether the new second pixel circuit layout needs to be optimized until the result index of the new second pixel circuit layout meets the design index;

[0068] If not, the optimization of the second pixel circuit layout is terminated.

[0069] The embodiments of the present application also provide a computer storage medium, on which a computer executable program is stored, and the computer executable program is executed to implement any method described in the embodiments of the present application.

[0070] An embodiment of the present application further provides an electronic device, which includes a memory and a processor, wherein the memory is used to store a computer executable program, and the processor is used to run the computer executable program to implement any method described in the embodiment of the present application.

[0071] The embodiments of the present application also provide a computer program product having a computer executable program stored thereon, wherein the computer executable program is executed to implement any of the methods described in the embodiments of the present application.

[0072] Figure 3A FIG. 1 is a schematic diagram showing the result of applying the above technical solution of the embodiment of the present application to a first pixel circuit layout. Figure 3A As shown, the aspect ratio of the TFT transistor is 9.14.

[0073] Figure 3B FIG. 1 is a partial schematic diagram of the result of applying the above technical solution of the embodiment of the present application to a first pixel circuit layout. Figure 3B After dragging, the TFT aspect ratio is changed to 11.14.

[0074] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.

Claims

1. A method for drawing a pixel circuit layout, characterized in that: include: An index calculation step, which includes calculating the result index of the created first pixel circuit layout and comparing it with the design index to determine whether the first pixel circuit layout needs to be used as a target pixel circuit layout to be optimized; A parameter adjustment step, comprising: in response to the need to re-optimize the target pixel circuit layout, adjusting the layout graphic input parameter accordingly according to the mapping relationship between the expected result index and the layout graphic input parameter, so as to correspondingly adjust the optimized layout feature of the layout graphic parameter unit, so as to perform layout drawing on the basis of the target pixel circuit layout to be optimized to obtain a second pixel circuit layout, wherein each layout graphic on the first pixel circuit layout is abstracted into one of the layout graphic parameter units; Jump to the index calculation step to calculate the result index of the second pixel circuit layout, and compare it with the design index to determine whether the second pixel circuit layout needs to be used as a new target pixel circuit layout to be optimized; If so, jump to the parameter adjustment step to perform layout drawing on the basis of the new target pixel circuit layout to obtain a new second pixel circuit layout, and execute the index calculation step to determine whether the new second pixel circuit layout needs to be optimized until the result index of the new second pixel circuit layout meets the design index; If not, then the optimization of the second pixel circuit layout is terminated; Wherein, the method further comprises: The initial layout optimization step includes: adjusting the initial layout characteristics of the layout graphic parameter unit on the first pixel circuit layout; A parameter adjustment step, comprising: in response to the need to re-optimize the target pixel circuit layout, according to the mapping relationship between the desired result index and the layout graphic input parameter, taking the initial layout feature as a reference, correspondingly adjusting the layout graphic input parameter, so as to correspondingly adjust the optimized layout feature of the layout graphic parameter unit, so as to perform layout drawing on the basis of the target pixel circuit layout to be optimized to obtain a second pixel circuit layout; Wherein, in the parameter adjustment step, the direction of parameter adjustment is determined according to the initial layout characteristics, so as to adjust the layout graphic input parameters accordingly; Wherein, in the parameter adjustment step, based on the artificial intelligence model, the layout graphic input parameter is adjusted accordingly according to the mapping relationship between the expected result indicator and the layout graphic input parameter; Among them, it also includes: Generate model training samples in real time to perform real-time training on the artificial intelligence model based on the training samples, wherein the model training samples include: the result indicators calculated in the indicator calculation step and the layout graphic input parameters obtained in the parameter adjustment step.

2. The method according to claim 1, characterized in that The method further comprises: The parsing step includes: parsing the created original pixel circuit layout to determine the layout pattern thereon; The abstraction step includes: abstracting each of the layout graphics into a layout graphic parameterized unit, each of the layout graphic parameter units having a corresponding layout graphic input parameter.

3. The method according to claim 1, characterized in that The method further comprises: a layout feature saving step, which comprises storing the optimized layout feature obtained by obtaining the second pixel circuit layout into a layout feature table; In the index calculation step, the optimized layout feature is obtained from the layout feature table, so as to calculate the result index of the second pixel circuit layout according to the optimized layout feature.

4. The method according to claim 1, characterized in that: In the index calculation step, the result index of the second pixel circuit layout is calculated according to the generated layout netlist.

5. A device for drawing a pixel circuit layout using the drawing method according to claim 1, characterized in that: include: An index calculation unit, which is used to calculate the result index of the created first pixel circuit layout, and compare it with the design index to determine whether the first pixel circuit layout needs to be used as a target pixel circuit layout to be optimized; A parameter adjustment unit, which is used to respond to the need to re-optimize the target pixel circuit layout, and adjust the layout graphic input parameters accordingly according to the mapping relationship between the expected result indicators and the layout graphic input parameters, so as to adjust the optimized layout characteristics of the layout graphic parameter unit accordingly, so as to perform layout drawing on the basis of the target pixel circuit layout to be optimized to obtain a second pixel circuit layout; Calling the index calculation unit to calculate the result index of the second pixel circuit layout, and comparing it with the design index to determine whether the second pixel circuit layout needs to be used as a new target pixel circuit layout to be optimized; If so, calling the parameter adjustment unit to perform layout drawing on the basis of the new target pixel circuit layout to obtain a new second pixel circuit layout, and executing the index calculation step to determine whether the new second pixel circuit layout needs to be optimized until the result index of the new second pixel circuit layout meets the design index; If not, the optimization of the second pixel circuit layout is terminated.

6. An electronic device, characterized in that: The electronic device comprises a memory and a processor, wherein the memory is used to store a computer executable program, and the processor is used to run the computer executable program to implement any one of the methods of claims 1-3.

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