Graphical Design Method for a Wideband Doherty Power Amplifier

Abstract

The present invention relates to the field of information technology, and discloses a graphical design method for a broadband Doherty power amplifier. The two-way output matching network required for the operation of the Doherty power amplifier (which can also be called the load modulation network (LMN)) is divided into the equivalent package parasitic parameter network (EPN) of the transistor and a "black box". Among them, the EPN of the transistor is constructed by the de-embedding technology, that is, as long as the structural content of the "black box" is completed, the design of the Doherty power amplifier can be realized. This method observes the reflection coefficient locus through the Smith chart to perform circuit matching, and intuitively constructs the output matching network of the Doherty two-way power amplifier from the current source end face to the load end, avoiding a large number of theoretical analyses and formula derivations for solving circuit parameters when designing the Doherty power amplifier, reducing the design difficulty of the Doherty power amplifier, and improving the work efficiency.

Description

Technical Field

[0001] The present invention relates to the field of information technology, and particularly relates to a graphical design method for a broadband Doherty power amplifier. Background Art

[0002] Due to various factors such as the parasitic packaging parameters of transistors, the narrow operating bandwidth of quarter-wavelength lines, and the requirement that the output impedance of the peak path power amplifier is infinite, the traditional Doherty architecture greatly limits the operating bandwidth of the traditional Doherty power amplifier architecture. Therefore, many scholars have expanded the operating bandwidth of the traditional Doherty by changing the load modulation network of the traditional Doherty power amplifier, designing an impedance compensation network, using the complex impedance at the synthesis point, and other methods.

[0003] However, in the design process of these Doherty power amplifiers, there are inevitably a large number of theoretical analyses and problems such as deriving and solving circuit parameters using formulas. This makes the design of Doherty power amplifiers more difficult and increases the workload. Summary of the Invention

[0004] Based on the above problems, the present invention provides a graphical design method for a broadband Doherty power amplifier. By observing the reflection coefficient locus on the Smith chart to select a suitable microstrip line for circuit matching, and intuitively constructing the output matching network of the Doherty two-way power amplifier from the current source end face to the load end, it avoids a large number of theoretical analyses and problems such as deriving and solving circuit parameters using formulas when designing a Doherty power amplifier, and reduces the design difficulty of the Doherty power amplifier.

[0005] To solve the above technical problems, the technical solution adopted by the present invention is:

[0006] A graphical design method for a broadband Doherty power amplifier, comprising the following steps:

[0007] Take a first transistor, obtain the locus of the reflection coefficient at the load end on the Smith chart, move the reflection coefficient locus to the real axis of the Smith chart, and match the back-off state impedance under the operating conditions when the Doherty power amplifier is in the saturated operating state to obtain the load modulation network of the carrier power amplifier;

[0008] Take a second transistor identical to the first transistor, obtain the locus of the reflection coefficient at the load end on the Smith chart, move the reflection coefficient locus to the real axis of the Smith chart, and adjust the output impedance of the peak power amplifier to make the reflection coefficient locus at the output port converge to the center frequency point to obtain the load modulation network of the peak power amplifier;

[0009] Design a broadband post-matching network to connect the load modulation networks of the carrier power amplifier and the peak power amplifier to the post-matching network, forming the entire output network of the broadband Doherty.

[0010] Furthermore, the construction of the load modulation network of the carrier power amplifier includes:

[0011] Step S1: Calculate the optimal impedance Ropt of a given first transistor, and obtain the equivalent package parameter EPN of the first transistor; cascade the optimal impedance Ropt of the first transistor with the obtained equivalent package parameter EPN to construct the network structure in the saturated operating state of the Doherty power amplifier, and obtain the locus of the reflection coefficient at the load end on the Smith chart.

[0012] Step S2: Connect a microstrip line TL1 after the EPN network to move the reflection coefficient locus to the real axis of the Smith chart, and obtain the port input impedance Zin at the load end.

[0013] Step S3: Set the load impedance RL according to the input impedance Zin to achieve the matching from the optimal impedance Ropt to 2*RL at the center frequency.

[0014] Step S4: Add a microstrip line TL2 with a characteristic impedance of 2*RL after TL1 to make the phase of the load modulation network of the carrier power amplifier reach 90°, and obtain the load modulation network of the carrier power amplifier.

[0015] Furthermore, the construction of the load modulation network of the peak power amplifier includes:

[0016] Step SA: Take a second transistor identical to the first transistor in Step S1, calculate the optimal impedance Ropt of the second transistor, and obtain the equivalent package parameter EPN of the second transistor; cascade the optimal impedance Ropt of the second transistor with the obtained equivalent package parameter EPN to construct the network structure in the saturated operating state of the Doherty power amplifier, and obtain the locus of the reflection coefficient at the load end on the Smith chart.

[0017] Step SB: Connect a microstrip line TL1 after the EPN network to move the reflection coefficient locus to the real axis of the Smith chart, and obtain the port input impedance Zin at the load end.

[0018] Step SC: Set the load impedance RL according to the input impedance Zin to achieve the matching from the optimal impedance Ropt to 2*RL at the center frequency.

[0019] Step SD: Move the reflection coefficient locus of the output port to the center of the Smith chart. Add a microstrip line TL2 with a characteristic impedance of 2*RL after TL1, and adjust the output impedance of the peak power amplifier to make the reflection coefficient locus of the output port converge to the center frequency, and obtain the load modulation network of the peak power amplifier.

[0020] Further, the microstrip line TL1 in step S2 is determined by the position of the reflection coefficient locus on the Smith chart after cascading the optimal impedance Ropt and the equivalent package parameter EPN; when the reflection coefficient locus is above the Smith chart, the capacitive microstrip line is selected for TL1, and when the reflection coefficient locus is below the Smith chart, the inductive microstrip line is selected for TL1.

[0021] Further, in step S3, the load impedance RL is set to half of the input impedance Zin.

[0022] Further, the microstrip line TL1 in step SB is determined by the position of the reflection coefficient locus on the Smith chart after cascading the optimal impedance Ropt and the equivalent package parameter EPN; when the reflection coefficient locus is above the Smith chart, the capacitive microstrip line is selected for TL1, and when the reflection coefficient locus is below the Smith chart, the inductive microstrip line is selected for TL1.

[0023] Further, in step SC, the load impedance RL is set to half of the input impedance Zin.

[0024] Further, the input ends of the carrier power amplifier and the peak power amplifier are connected by an equal-power Wilkinson power divider.

[0025] Compared with the prior art, the beneficial effects of the present invention are as follows: by calculating the optimal impedance Ropt of the transistor, and then solving the equivalent package parasitic parameters (EPN) of the transistor through the de-embedding technology, cascading the obtained Ropt and the transistor equivalent package parasitic parameter EPN structure constructed by the de-embedding technology, observing the reflection coefficient locus through the Smith chart to select a suitable microstrip line for circuit matching, and intuitively constructing the output matching network of the Doherty two-way power amplifier from the current source end to the load end, avoiding problems such as a large amount of theoretical analysis and formula derivation for solving circuit parameters when designing the Doherty power amplifier, and reducing the design difficulty of the Doherty power amplifier. Description of the Drawings

[0026] Figure 1 It is the EPN structure diagram of the transistor in Embodiment 2;

[0027] Figure 2 In (a), the EPN constructed by the de-embedding technology in Embodiment 2 is cascaded with the optimal impedance Ropt, and in (b), the reflection coefficient locus of port Port2 in the structure of (a) is presented on the Smith chart;

[0028] Figure 3(a) is the schematic diagram of the structure after cascading EPN and Ropt and adopting a parallel inductive microstrip line TL1 in Embodiment 2, and (b) is the corresponding Figure 3 Reflection coefficient Γ of port Port2 in the (a) structure 2 The locus lies on the real axis of the Smith chart;

[0029] Figure 4 (a) is that after cascading a microstrip line with a characteristic impedance of 2·R in Embodiment 2, the locus of Γ2 moves to the center position of the Smith chart, and (b) is L The phase within the frequency band of the (a) structure Figure 3 (a) is the load modulation network structure diagram of the carrier power amplifier in Embodiment 2, and (b) is the reflection coefficient locus of port Port2;

[0030] Figure 5

[0031] Figure 6 (a) is the impedance matching network of the peak power amplifier constructed in Embodiment 2, and (b) is the output impedance Zop of the peak power amplifier;

[0032] Figure 7 (a) is the schematic diagram of the Doherty power amplifier composed of the carrier power amplifier and the peak power amplifier in Embodiment 2, (b) is the reflection coefficient locus of port Port2 when the peak power amplifier output impedance Zop is added and not added, and (c) is the reflection coefficient locus of port Port1 when the peak power amplifier output impedance Zop is added and not added;

[0033] Figure 8 Is the schematic diagram of the final constructed Doherty power amplifier in Embodiment 2;

[0034] Figure 9 (a) is the simulation result diagram of the Doherty power amplifier constructed in Embodiment 2 from 1.9 GHz to 2.2 GHz; (b) is the simulation result diagram from 2.3 GHz to 2.6 GHz;

[0035] Figure 10 (a) is the actual test result diagram of the physical Doherty power amplifier processed in Embodiment 2;

[0036] Figure 11 (a) is the result comparison diagram of simulation and actual measurement in Embodiment 2;

[0037] Figure 12 (a) is the design method flow chart of the Doherty power amplifier in Embodiment 1 or 2. Detailed implementation manner

[0038] ​To make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to embodiments and drawings. The illustrative embodiments and descriptions of the present invention are only used to explain the present invention and shall not be construed as limiting the present invention.

[0039] In the description of the present invention, it should be noted that the terms "first" and "second" are only used for descriptive purposes and shall not be construed as indicating or implying relative importance.

[0040] The technical idea of the present invention is as follows: Take the first transistor to obtain the locus of the reflection coefficient at the load end on the Smith chart, move the reflection coefficient locus to the real axis of the Smith chart, and match the back-off state impedance under the working conditions of the Doherty power amplifier in the saturated working state to obtain the load modulation network of the carrier power amplifier; Take the second transistor identical to the first transistor to obtain the locus of the reflection coefficient at the load end on the Smith chart, move the reflection coefficient locus to the real axis of the Smith chart, and adjust the output impedance of the peak power amplifier to make the reflection coefficient locus at the output port converge to the center frequency point to obtain the load modulation network of the peak power amplifier; Design a broadband post-matching network, connect the load modulation networks of the carrier power amplifier and the peak power amplifier to the post-matching network to form the entire output network of the broadband Doherty. The present invention effectively constructs and matches the load modulation networks of the carrier power amplifier and the peak power amplifier in a graphical manner, reducing the design difficulty of the Doherty power amplifier.

[0041] Embodiment 1:

[0042] See Figure 12 , a graphical design method for a broadband Doherty power amplifier, comprising the following steps:

[0043] Construction of the load modulation network of the carrier power amplifier, including:

[0044] Step S1: Cascade the optimal impedance Ropt of the first transistor obtained by solution with the equivalent package parasitic parameter EPN structure of the first transistor constructed by the de-embedding technique; The position of the reflection coefficient on the Smith chart at the center frequency point can be obtained.

[0045] In this embodiment, a network structure diagram for the Doherty power amplifier in the saturated working state is constructed, that is, impedance matching from 2*RL to Ropt is achieved through EPN + "black box". Ropt is the optimal impedance at the current source end face when the power amplifier at the left end of EPN works. The value of Ropt can be calculated theoretically. EPN can be constructed through de-embedding technology. RL is the load impedance value at the load end of the right end of the black box. First, consider the "black box" as a short-circuit state. At this time, the locus of the reflection coefficient at the load end on the Smith chart can be obtained. The distribution of the locus has two cases, in the upper half or the lower half of the Smith chart. The reference impedance of the Smith chart is 2RL, and RL can now be any positive real number.

[0046] Step S2: Connect a microstrip line TL1 in parallel or in cascade between the cascade structure and the output port to move the reflection coefficient locus to the real axis of the Smith chart and obtain the port input impedance Zin at the load end. TL1 is the first part of the "black box".

[0047] In this embodiment, according to the position of the locus obtained in S1 on the Smith chart, the first step of constructing the "black box" structure is started. The purpose of the construction is to move the reflection coefficient locus at the load end to the real axis of the Smith chart at the center frequency point and obtain the port input impedance Zin at the load end at this time. At this time, there are two cases. If the reflection coefficient locus is above the Smith chart, capacitive elements can be connected in parallel or in series to move the locus down to the real axis of the Smith chart at the center frequency point. If the reflection coefficient locus is below the Smith chart, inductive elements can be connected in parallel or in series to move the locus up to the real axis of the Smith chart at the center frequency point. The specific parallel or series method needs to be considered comprehensively in terms of the circuit structure and the dimensions of the microstrip transmission line, etc.

[0048] Step S3: Set the load impedance RL according to the input impedance Zin to achieve the matching from the optimal impedance Ropt to 2*RL at the center frequency point.

[0049] In this embodiment, after the reflection coefficient locus is moved to the real axis of the Smith chart, the impedance matching of LMN in saturation needs to be completed next. So, the value of the load RL is set to 1 / 2*Zin, so as to achieve the matching from the impedance Ropt to 2*RL at the center frequency point and meet the working conditions of the Doherty carrier power amplifier in the saturated state.

[0050] Step S4: Add a microstrip line TL2 with a characteristic impedance of 2*RL to make the phase of the load modulation network of the carrier power amplifier reach 90°, and obtain the load modulation network of the carrier power amplifier, that is, TL1 and TL2 constitute the complete "black box" of the carrier power amplifier.

[0051] In this embodiment, on the basis of meeting the working conditions of the saturation state of the Doherty power amplifier in S3, the structure of the "black box" is further constructed. The main purpose of this step is to achieve impedance matching of the Doherty power amplifier in the back-off state without destroying the impedance matching of the Doherty power amplifier in the saturation working state. Therefore, a microstrip line with a characteristic impedance of 2*RL is connected in series, and the phase of the LMN is adjusted to 90°, so as to automatically meet the impedance matching in the back-off state without destroying the impedance matching in the saturation state.

[0052] The construction of the load modulation network of the peak power amplifier includes:

[0053] Take the same second transistor as in step S1, and according to the methods of steps S1 - S3, move the reflection coefficient locus of the output port to the center of the Smith chart. Finally, the function of the microstrip line TL2 with a characteristic impedance of 2*RL connected in series is no longer to make the phase of the LMN reach 90°, but to adjust the output impedance of the peak power amplifier to the required impedance value, so that the reflection coefficient locus of the output port converges to the center frequency point, thereby realizing the bandwidth expansion of the Doherty power amplifier and effectively improving the working bandwidth. In this embodiment, TL1 and TL2 constitute the "black box" of the peak power amplifier output network.

[0054] The construction of the broadband Doherty output network includes:

[0055] Design a broadband post-matching network, connect the output matching networks of the carrier power amplifier and the peak power amplifier with the post-matching network to form the entire output network of the broadband Doherty. This post-matching network can flexibly introduce the output impedance of the peak power amplifier into the working state of the carrier power amplifier, without affecting the performance of the carrier power amplifier, and can effectively improve the overall working bandwidth of the Doherty.

[0056] In this embodiment, for the given transistors (including the first transistor and the second transistor), by calculating the optimal impedance Ropt of the transistors, and then solving the equivalent package parasitic parameter EPN structure of the transistors through the de-embedding technology, cascade the obtained Ropt and the transistor equivalent package parasitic parameter EPN structure constructed by the de-embedding technology, and observe the reflection coefficient locus through the Smith chart to perform circuit matching, and intuitively construct the output matching network of the Doherty two-way power amplifier from the current source end to the load end, avoiding a large number of theoretical analyses and formula derivations for solving circuit parameters and other problems when designing the Doherty power amplifier, and reducing the design difficulty of the Doherty power amplifier.

[0057] Embodiment 2:

[0058] See Figure 1-12, A graphical design method for a broadband Doherty power amplifier, including the design of a carrier power amplifier and a peak power amplifier. The carrier power amplifier and the peak power amplifier both use the same transistors, and the output matching networks of the two power amplifiers only need to be composed of two sections of microstrip lines. Finally, the input ends of the carrier power amplifier and the peak power amplifier are connected through a post-matching network.

[0059] In this embodiment, the detailed steps are described by taking the design of a broadband Doherty power amplifier with a working frequency band of 1.9 GHz - 2.6 GHz as an example.

[0060] 1. The transistors (including the first transistor and the second transistor) of the carrier power amplifier and the peak power amplifier in this embodiment both use the commercial GaN high electron mobility transistor CGH40045F. After calculation, the optimal impedance Ropt of the transistor is obtained as 8 Ω, and the EPN structure of the transistor constructed by the de-embedding technology is as Figure 1 .

[0061] 2. Cascading the obtained optimal impedance Ropt and the parasitic parameters of the equivalent package of the transistor EPN structure constructed by the de-embedding technology, the network as shown in Figure 2 (a) and the reflection coefficient locus as shown in Figure 2 (b) are obtained. At this time, the value of the load RL is set to 5 Ω, and the reference impedance of the Smith chart in the simulation software is 10 Ω. Thus, the position of the reflection coefficient Γ 1 on the Smith chart at the center frequency point is obtained, and then the design starts from the load modulation network of the carrier power amplifier.

[0062] 3. From the reflection coefficient locus in Figure 2 (b), it can be seen that paralleling or cascading a capacitive microstrip line can move the reflection coefficient locus to the real axis of the Smith chart. In this embodiment, cascading a microstrip line in the constructed cascaded structure may cause the phase of the load modulation network of the carrier power amplifier to exceed 90°, thus affecting the circuit design. Therefore, the microstrip line TL1 is selected as a parallel capacitive open circuit to move the reflection coefficient locus; the parallel capacitive open circuit here can also form a low-pass structure, which is beneficial to the suppression of harmonics. As Figure 3 , at this moment, the reflection coefficient locus falls on the real axis position at the center frequency point.

[0063] 4. In order to move the reflection coefficient locus to the center position of the Smith chart, the value of R L is set to Figure 4 half of the input impedance Zin of port Port2 in Figure 4This is the result of RL = 4Ω. At this time, the phase of the constructed network is 55° at the center frequency point.

[0064] 5. In the previous steps, the impedance matching at saturation has been achieved for the load modulation network of the carrier power amplifier. To achieve impedance matching at the back-off level, a microstrip line needs to be added to make the phase of the load modulation network reach 90°. And to not affect the impedance matching at saturation, the characteristic impedance of the added microstrip line TL2 should be 2·RL = 8Ω. Thus, the load modulation network of the carrier power amplifier is completed, as shown in Figure 5 (a), and the reflection coefficient of port Port2 is as shown in Figure 5 (b).

[0065] 6. Use the same method to construct the impedance matching network of the peak power amplifier. Since the peak power amplifier and the carrier power amplifier use the same transistor, the first microstrip line that can be added can use the same transmission line TL1 as in the carrier power amplifier. The function of the second microstrip line is to adjust the output impedance of the peak power amplifier for bandwidth expansion when Doherty is at back-off. From Figure 5 (b), it can be obtained that the reflection coefficient of port Port2 is relatively divergent within the frequency band. So when we make the output impedance of the peak power amplifier present capacitive reactance at high frequency points and inductive reactance at low frequency points. Then the Figure 5 reflection coefficient locus in (b) can converge towards the center frequency point. Finally, the output matching network of the peak power amplifier and its output impedance are as shown in Figure 6 shown.

[0066] 7. Connect the output matching networks of the carrier power amplifier and the peak power amplifier to the post-matching network through a broadband post-matching network. As shown in Figure 7 , with the help of the output impedance Zop of the peak power amplifier, the reflection coefficients of port Port2 and port Port1 become more convergent within the frequency band. Thus, the bandwidth characteristics are effectively improved.

[0067] The microstrip line circuit parameters of the two-way power amplifier in this embodiment are as follows:

[0068]

[0069] In this embodiment, the inputs of the carrier power amplifier and the peak power amplifier are connected through an equal-power Wilkinson power divider. The schematic diagram of the finally constructed Doherty power amplifier is as shown in Figure 8 . The input matching circuits of the two-way power amplifiers are designed to ensure that the input RF signals can reach the gates of the transistors as losslessly as possible. The gate bias voltages of the two-way power amplifiers are -2.8V and -7V respectively. The drain supply voltage is 28V. The simulation results are as shown in Figure 9In the frequency band of 1.9 to 2.6 GHz, the peak output power is 47.5-48.9 dBm and the saturated gain is 6.5-7.9 dB. The saturated drain efficiency is 63%-71.6%. The drain efficiency at 6 dB back-off is 48%-54%. This is a good illustration of the effectiveness of this graphical design method.

[0070] The gate bias voltages of the carrier power amplifier and peak power amplifier added to the processed object are -2.7V and -7.5V respectively. The drain bias voltage is 28V. The final actual test results are as follows Figure 10 .

[0071] Due to the error between the simulation model of the transistor and the actual production, the final simulation and measured results are compared. Figure 11 The final measured results show high performance at 1.75GHz-2.45GHz. The Doherty peak output power is 48.9-49.8dBm, and the saturated gain is 5.1-6dB. The saturated drain efficiency is 64%-73%, and the drain efficiency at 6dB back-off is 48%-56%.

[0072] The above is an embodiment of the present invention. The above embodiments and the specific parameters in the embodiments are only for the purpose of clearly describing the invention verification process, and are not intended to limit the patent protection scope of the present invention. The patent protection scope of the present invention is still subject to its claims. Any equivalent structural changes made by using the contents of the description and drawings of the present invention should be included in the protection scope of the present invention.

Claims

1. A graphical design method for a broadband Doherty power amplifier, characterized in that, it includes the following steps: Take a first transistor, obtain the locus of the reflection coefficient at the load end on the Smith chart, move the reflection coefficient locus to the real axis of the Smith chart, and match the back-off state impedance under the operating conditions when the Doherty power amplifier is in the saturated operating state, to obtain the load modulation network of the carrier power amplifier; Take a second transistor identical to the first transistor, obtain the locus of the reflection coefficient at the load end on the Smith chart, move the reflection coefficient locus to the real axis of the Smith chart, adjust the output impedance of the peak power amplifier, and make the reflection coefficient locus at the output port converge to the center frequency point, to obtain the load modulation network of the peak power amplifier; Design a broadband post-matching network, connect the load modulation networks of the carrier power amplifier and the peak power amplifier to the post-matching network, to form the entire output network of the broadband Doherty; The construction of the load modulation network of the carrier power amplifier includes: Step S1: Calculate the optimal impedance Ropt of the given first transistor, and obtain the equivalent package parameter EPN of the first transistor; cascade the optimal impedance Ropt of the first transistor with the obtained equivalent package parameter EPN, construct the network structure when the Doherty power amplifier is in the saturated operating state, and obtain the locus of the reflection coefficient at the load end on the Smith chart; Step S2: Connect a microstrip line TL1 after the EPN network to move the reflection coefficient locus to the real axis of the Smith chart, and obtain the port input impedance Zin at the load end; Step S3: Set the load impedance RL according to the input impedance Zin, so as to satisfy the matching from the optimal impedance Ropt to 2*RL at the center frequency point; Step S4: Add a microstrip line TL2 with a characteristic impedance of 2*RL to TL1, so that the phase of the load modulation network of the carrier power amplifier reaches 90°, to obtain the load modulation network of the carrier power amplifier; The construction of the load modulation network of the peak power amplifier includes: Step SA: Take a second transistor identical to the first transistor in Step S1, calculate the optimal impedance Ropt of the second transistor, and obtain the equivalent package parameter EPN of the second transistor; cascade the optimal impedance Ropt of the second transistor with the obtained equivalent package parameter EPN, construct the network structure when the Doherty power amplifier is in the saturated operating state, and obtain the locus of the reflection coefficient at the load end on the Smith chart; Step SB: Connect a microstrip line TL1 after the EPN network to move the reflection coefficient locus to the real axis of the Smith chart, and obtain the port input impedance Zin at the load end; Step SC: Set the load impedance RL according to the input impedance Zin, so as to satisfy the matching from the optimal impedance Ropt to 2*RL at the center frequency point; Step SD: Move the reflection coefficient locus at the output port to the center of the Smith chart, add a microstrip line TL2 with a characteristic impedance of 2*RL after TL1, adjust the output impedance of the peak power amplifier, and make the reflection coefficient locus at the output port converge to the center frequency point, to obtain the load modulation network of the peak power amplifier.

2. The graphical design method for a broadband Doherty power amplifier according to claim 1, It is characterized in that: The microstrip line TL1 in step S2 is determined by the position of the reflection coefficient locus on the Smith chart after cascading the optimal impedance Ropt and the equivalent package parameter EPN; when the reflection coefficient locus is above the Smith chart, the capacitive microstrip line is selected for TL1, and when the reflection coefficient locus is below the Smith chart, the inductive microstrip line is selected for TL1.

3. The graphical design method of the broadband Doherty power amplifier according to claim 1, It is characterized in that, In step S3, the load impedance RL is set to half of the input impedance Zin.

4. The graphical design method of the broadband Doherty power amplifier according to claim 1, It is characterized in that: The microstrip line TL1 in step SB is determined by the position of the reflection coefficient locus on the Smith chart after cascading the optimal impedance Ropt and the equivalent package parameter EPN; when the reflection coefficient locus is above the Smith chart, the capacitive microstrip line is selected for TL1, and when the reflection coefficient locus is below the Smith chart, the inductive microstrip line is selected for TL1.

5. The graphical design method of the broadband Doherty power amplifier according to claim 1, It is characterized in that, In step SC, the load impedance RL is set to half of the input impedance Zin.

6. The graphical design method of the broadband Doherty power amplifier according to claim 1, It is characterized in that: The input ends of the carrier power amplifier and the peak power amplifier are connected by an equal-power Wilkinson power divider.

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