Graphics processors, chips, and electronic devices

Abstract

The application provides a graphics processor, a chip and an electronic device. The graphics processor comprises at least two data and command distributors and at least two graphics processor cores, each of the data and command distributors is connected with at least one of the graphics processor cores, and a group of data and command transmission lines are connected between one of the data and command distributors and one of the graphics processor cores. The graphics processor is configured to provide at least one virtual graphics processor, each of the virtual graphics processors comprises one of the data and command distributors and part or all of the graphics processor cores connected with the data and command distributor. The graphics processor can provide at least one virtual graphics processor, and the graphics processor can be commonly used by multiple users through graphics processor virtualization.

Description

Technical Field

[0001] This application belongs to the field of processor technology, and relates to a graphics processor, and more particularly to a graphics processor, chip and electronic device. Background Technology

[0002] A graphics processing unit (GPU), also known as a display core, visual processor, or display chip, is a microprocessor specifically designed for performing image and graphics-related calculations in personal computers, workstations, game consoles, and some mobile devices (such as tablets and smartphones). GPUs reduce the reliance of graphics cards on the central processing unit (CPU) and perform some of the tasks that were originally handled by the CPU.

[0003] Electronic devices typically have a limited number of graphics processing units (GPUs). To more efficiently utilize these limited GPU resources and better meet user needs, GPU virtualization technology has emerged. GPU virtualization requires virtualizing a single physical GPU into multiple virtual GPUs to accommodate multiple users simultaneously. Each user uses one virtual GPU, and each virtual GPU can use one or more GPU cores. However, in existing GPU virtualization technologies, the GPU cores used by each virtual GPU are often fixed, making it difficult to flexibly configure them according to actual needs. Summary of the Invention

[0004] This application provides a graphics processor, a chip, and an electronic device, wherein the graphics processor cores included in each virtual graphics processor can be configured according to actual needs.

[0005] In a first aspect, embodiments of this application provide a graphics processor, the graphics processor including at least two data and command dispatchers and at least two graphics processor cores, each of the data and command dispatchers being connected to at least one of the graphics processor cores, wherein one of the data and command dispatchers and one of the graphics processor cores are connected via a set of data and command transmission lines; the graphics processor is configured to provide at least one virtual graphics processor, each of the virtual graphics processors including one of the data and command dispatchers and some or all of the graphics processor cores connected thereto.

[0006] In one implementation of the first aspect, the graphics processor is configured, according to received instructions, to provide n virtual graphics processors, where n is any positive integer less than or equal to N, and N is the number of graphics processor cores.

[0007] In one implementation of the first aspect, the i-th data and command dispatcher of the graphics processor is... The graphics processor cores are connected together, where i and ni are both positive integers less than or equal to N, and floor is a floor function.

[0008] In one implementation of the first aspect, the graphics processor includes N data and command dispatchers, one of which is connected to N graphics processor cores, and mj-mj+1 of the data and command dispatchers are connected to... The graphics processor cores are connected together, and mj and mj+1 are adjacent positive integers that are divisible by N, where 1≤mj+1<mj≤N.

[0009] In one implementation of the first aspect, the graphics processor further includes a data selector, and the graphics processor core, which connects to at least two of the data and command dispatchers, is connected to the data and command dispatchers via the data selector.

[0010] In one implementation of the first aspect, the number of data and command dispatchers and the number of graphics processor cores are both eight, and the connection methods between the data and command dispatchers and the graphics processor cores include one one-to-eight connection, one one-to-four connection, two one-to-two connections, and four one-to-one connections.

[0011] In one implementation of the first aspect, the number of physical layers of the graphics processor is configured according to the number of data and command transmission lines.

[0012] In one implementation of the first aspect, the data and command dispatcher is fully connected to the graphics processor core.

[0013] Secondly, embodiments of this application provide a chip, the chip including a graphics processor and input / output pins as described in any implementation of the first aspect of this application.

[0014] Secondly, embodiments of this application provide an electronic device, which includes a graphics processor and a memory as described in any implementation of the first aspect of this application.

[0015] The graphics processor provided in this application embodiment can provide at least one virtual graphics processor. The graphics processor cores included in each virtual graphics processor can be configured according to actual needs. Therefore, in specific applications, the graphics processor cores included in the virtual graphics processor can be flexibly configured according to actual needs.

[0016] In some embodiments of this application, by optimizing the interconnection between the data and command dispatcher and the graphics processor core, the number of interconnections between them can be reduced, avoiding congestion problems during the place and route (P&R) phase and thus reducing chip area. Furthermore, in some embodiments, the number of physical layers of the graphics processor is configured based on the number of data and command transmission lines. In these embodiments, by optimizing the interconnection between the data and command dispatcher and the graphics processor core, the number of physical layers of the graphics processor can be reduced. Attached Figure Description

[0017] Figure 1 The diagram shows the structure of an electronic device.

[0018] Figure 2 The diagram shows the structure of a graphics processor.

[0019] Figure 3A The diagram shown is a schematic representation of the structure of a graphics processor provided in an embodiment of this application.

[0020] Figure 3B The diagram shows the connection relationship between the data and command dispatcher and the graphics processor core in one embodiment of this application.

[0021] Figure 4 The diagram shown is a schematic representation of the structure of a graphics processor provided in an embodiment of this application.

[0022] Figure 5A and Figure 5B The diagram shown is a schematic representation of the structure of a graphics processor provided in an embodiment of this application.

[0023] Figure 5C The diagram shown is a schematic representation of the structure of a graphics processor provided in an embodiment of this application.

[0024] Figure 6 The diagram shown is a schematic representation of the structure of a graphics processor provided in an embodiment of this application.

[0025] Figure 7 The diagram shown is a schematic diagram of the structure of a chip provided in an embodiment of this application.

[0026] Component designation explanation

[0027] 100 Electronic devices

[0028] 110 System Processor

[0029] 120 graphics processor

[0030] 121-1~121-k Graphics Processor Core

[0031] 122 Configuration Command Processor

[0032] 123 Crossbar Switch Bus

[0033] 124-1~124-k L2 cache

[0034] 130 Memory

[0035] 140 display screen

[0036] 300 graphics processor

[0037] 310-1~310-M Data and Command Distributor

[0038] 330-1 to 330-N graphics processor cores

[0039] 500 graphics processor

[0040] 510-1 to 510-8 Data and Command Distributors

[0041] 520-2~520-8 Data Selector

[0042] 530-1 to 530-8 graphics processor cores Detailed Implementation

[0043] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, unless otherwise specified, the following embodiments and features in the embodiments can be combined with each other.

[0044] In this application, unless otherwise expressly specified and limited, the terms "installation," "connection," "linking," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0045] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this application. Therefore, the drawings only show the components related to this application and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0046] The following embodiments of this application provide a graphics processor whose application scenarios include, but are not limited to, electronic devices. These electronic devices can be various types of electronic devices such as mobile phones, tablets, personal computers (PCs), personal digital assistants (PDAs), smartwatches, netbooks, wearable electronic devices, augmented reality (AR) devices, virtual reality (VR) devices, in-vehicle devices, smart cars, smart speakers, robots, smart glasses, and so on.

[0047] Please see Figure 1 The image shown is a schematic diagram of the structure of an electronic device 100 according to an embodiment of this application. The electronic device 100 includes a system processor 110 (e.g., a CPU), a graphics processor 120, a memory 130, and a display screen 140.

[0048] In specific operation, the system processor 110 can boot into an operating system (OS) to provide various operations for the user system, including user applications, data processing services, communication services, storage services, game services, or other operations. The graphics processor 120 can provide the system processor 110 with graphics processing, rendering services, and enhancement operations. For details, please refer to... Figure 2 The graphics processor 120 provides operations involving components including graphics processor cores (e.g., 121-1, 121-2, ..., 121-k), a configuration command processor 122, and a crossbar bus 123, where k is a positive integer. It is understood that graphics processing, rendering services, and enhancement operations can be performed by one or more functional modules of the graphics processor core 120; for example, one functional module of the graphics processor core 120 can perform one operation. In this context... Figure 1 The graphics processor 120 may be a separate component connected to the system processor 110 via communication line 150, but it should be understood that in other examples the graphics processor 120 may also be integrated into the system processor 110.

[0049] Memory 130 may include random access memory (RAM), cache memory devices, or other volatile memory elements used by system processor 110 or graphics processor 120. Other volatile memory elements used by graphics processor 120 include caches that can be integrated into graphics processor 120, for example... Figure 2 The secondary (L2) cache 124-1, 124-2, ..., 124-k is included. Memory 130 may also include non-volatile memory elements, such as hard disk drives (HDDs), flash memory devices, solid-state drives (SSDs), or other memory devices that store the operating system, applications, or other software or firmware for electronic device 100.

[0050] Electronic devices 100 can communicate with each other via one or more communication links (such as one or more network links). For example, communication links can use metal, glass, optics, air, space, or other materials as transmission media. Example communication links can use various communication interfaces and protocols, such as Internet Protocol (IP), Ethernet, Universal Serial Bus (USB), Bluetooth, WiFi, or other communication signaling or communication formats, including combinations, modifications, or variations thereof. Communication links can be direct links, or they can include intermediate networks, systems, or devices, and can include logical network links that transmit data through multiple physical links.

[0051] Electronic device 100 may include software such as operating systems, logs, databases, utilities, drivers, networking software, user applications, data processing applications, game applications, and other software stored on computer-readable media. The software of electronic device 100 may include one or more platforms controlled by a distributed computing system or cloud computing service. The software of electronic device 100 may include logical interface elements such as software-defined interfaces and application programming interfaces (APIs).

[0052] The software of the electronic device 100 can be used to generate data to be rendered by the graphics processor 120 and control the operation of the graphics processor 120 to render graphics for output to one or more displays 140 for display.

[0053] System processor 110, graphics processor 120, memory 130, and display screen 140 can communicate via coupled communication line 150. Example communication line 150 can use metal, glass, optics, air, space, or some other material as the transmission medium. Communication line 150 can use various communication protocols and signaling, such as computer buses, including combinations or variations thereof. Communication line 150 can be a direct link, or it can include intermediate networks, systems, or devices, and can include logical network links transmitted through multiple physical links.

[0054] Figure 2 This is shown as an example of a graphics processor 120 in an embodiment of this application. Figure 2 As shown, the graphics processor 120 specifically includes multiple graphics processor cores 121-1, 121-2...121-k, a configuration command processor 122, a crossbar switch bus 123, and multiple L2 caches 124-1, 124-2, 124-3...124-k. The crossbar switch bus 123 connects the graphics processor cores and the L2 caches, providing a channel for the graphics processor cores to access the L2 caches and for the L2 caches to return data to the graphics processor cores. Furthermore, the L2 caches are also connected to external memory 130 via a memory interface (MIF).

[0055] In the architecture provided in this application embodiment, the system processor 110 prepares the tasks and data for the graphics processor 120 to run, and sends them to the graphics processor kernel in the form of command configuration. Specifically, the configuration command processor 122 receives the command issued by the system processor 110, parses the task, and directly sends it to the graphics processor kernel, which then begins to execute the task. Alternatively, the task can be sent by the configuration command processor 122 to the memory 130 via the crossbar switch bus 123, where the graphics processor kernel reads it from the memory 130 and processes it.

[0056] The specific process of a graphics processing unit (GPU) core executing a task includes: the GPU core reading task-related external data from memory 130, processing the data, and writing the data. Since the GPU core is multi-threaded, meaning one instruction processes a batch of data, to reduce data fetching and storing latency and improve processing efficiency, a typical design places an L2 cache between the GPU core and memory 130. This L2 cache prefetches and caches large amounts of data, reducing the GPU core's waiting time.

[0057] The technical solutions in the embodiments of this application will be described in detail below with reference to the accompanying drawings.

[0058] Figure 3A The diagram shown is a structural schematic of a graphics processor 300 according to one embodiment of this application. Figure 3A As shown, the graphics processing unit 300 includes M data and command dispatchers 310-1 to 310-M and N graphics processing unit clusters 330-1 to 330-N, where M and N are both positive integers greater than or equal to 2. Each graphics processing unit cluster contains a set of graphics processing pipelines. In some implementations, the values ​​of M and N can be the same; in other implementations, the values ​​of M and N can be different. Each data and command dispatcher can be connected to at least one graphics processing unit cluster and at most N graphics processing unit clusters. The connection method between the data and command dispatchers and the graphics processing unit clusters includes, but is not limited to, direct connection between the data and command dispatchers and the graphics processing unit clusters, or indirect connection between the data and command dispatchers and the graphics processing unit clusters through data selectors, etc. A data and command dispatcher is connected to a graphics processing unit cluster through a set of data and command transmission lines, each set of data and command transmission lines being, for example, a set of 1000 to 2000 data and command transmission lines.

[0059] In this embodiment of the application, the graphics processor 300 is used to provide at least one virtual graphics processor, each virtual graphics processor including a data and command dispatcher and some or all of the graphics processor cores connected to the data and command dispatcher. For example, Figure 3A The data and command dispatcher 310-1 and the associated graphics processor cores 330-1 and 330-N in the graphics processor 300 shown can provide a virtual graphics processor, and the data and command dispatcher 310-2 and the associated graphics processor core 330-2 can provide another virtual graphics processor.

[0060] In some implementations, a graphics processor can provide multiple virtual graphics processors (GPUs) at any given time. Each virtual GPU can contain multiple GPU cores, and each GPU core is contained within only one virtual GPU. Each user can use one virtual GPU, and each GPU core can only be used by one user at a time.

[0061] Optionally, Figure 3BThis diagram illustrates the connection between the data and command dispatcher and the graphics processor core in this embodiment. Taking the data and command dispatcher 310-1 as an example, it connects to the double data rate synchronous dynamic random access memory (DDR) via the Advanced Extensible Interface (AXI) protocol and the Advanced High Performance Bus (AHB) host interface (HI) 0. The AXI is a bus protocol corresponding to a high-performance, high-bandwidth, low-latency on-chip bus. The AXI enables a system-on-chip (SoC) to achieve superior performance with a smaller area and lower power consumption. The AHB is a high-performance bus primarily used for connections between high-performance modules, and its main features include single-clock-edge operation, non-tri-state implementation, and support for burst transmissions. The Graphics Processing Unit (GPU) Core 330-1 includes a shader module, a transform feedback (TFB) module, a position primitive assembly (PPA) module, a final primitive assembly (FPA) module, a pixel engine (PE) module, and other modules. The final primitive assembly module is used to write intermediate results to memory. The position primitive assembly is used to perform culling operations such as back face culling and zero area culling. The FPA module is used to perform viewport frustum transformations, and the pixel engine module is used to perform operations such as alpha blending on pixels.

[0062] As can be seen from the above description, the graphics processor provided in this application embodiment can provide users with at least one virtual graphics processor, and the graphics processor can be shared by multiple users through graphics processor virtualization.

[0063] According to one embodiment of this application, the graphics processor is configured to provide n virtual graphics processors according to received instructions, where n is any positive integer less than or equal to N, and N is the number of graphics processor cores, such as 4, 8, 16, etc. Optionally, the n virtual graphics processors include all N graphics processor cores, but this application is not limited thereto.

[0064] In one embodiment of this application, the i-th data and command dispatcher of the graphics processor and The graphics processing unit cores are connected, where i and n i All are positive integers less than or equal to N, and floor is the floor function. Please refer to [link / reference]. Figure 4 Taking N=4 as an example, the first data and command dispatcher 410-1 of the graphics processor 400 is connected to one graphics processor core 430-1 (n1=3), the second data and command dispatcher 410-2 is connected to four graphics processor cores 430-1 to 430-4 (n2=1), the third data and command dispatcher 410-3 is connected to two graphics processor cores 430-1 and 430-3 (n3=2), and the fourth data and command dispatcher 410-4 is connected to two graphics processor cores 430-2 and 430-4 (n4=2). In the embodiments of this application, the connection method between the data and command dispatcher and the graphics processor core includes, but is not limited to, the data and command dispatcher being directly connected to the graphics processor core, or the data and command dispatcher being indirectly connected to the graphics processor core through a data selector, etc.

[0065] Figure 4 The graphics processor 400 shown can be configured to provide 1 to 4 virtual graphics processors according to received instructions. When the graphics processor is configured to provide 1 virtual graphics processor, the user can use 4 graphics processor cores 430-1 to 430-4 through the data and command distributor 410-2. When the graphics processor is configured to provide two virtual graphics processors, the first user can use graphics processor cores 430-1 and 430-3 through the data and command distributor 410-2, and the second user can use graphics processor cores 430-2 and 430-4 through the data and command distributor 410-4. When the graphics processor is configured to provide 3 virtual graphics processors, the first user can use graphics processor core 430-1 through the data and command distributor 410-1, the second user can use graphics processor cores 430-2 and 430-4 through the data and command distributor 410-2, and the third user can use graphics processor core 430-3 through the data and command distributor 410-3. When the graphics processor is configured to provide four virtual graphics processors, the first user can use graphics processor 430-1 through data and command distributor 410-1, the second user can use graphics processor 430-2 through data and command distributor 410-2, the third user can use graphics processor 430-3 through data and command distributor 410-3, and the fourth user can use graphics processor 430-4 through data and command distributor 410-4.

[0066] As described above, in this embodiment, the connection between the data and command dispatcher and the graphics processor core is simplified to one one-to-four connection (1×4 sets of connections), two one-to-two connections (2×2 sets of connections), and one one-to-one connection (1×1 set of connections). Therefore, in this embodiment, there are a total of 9 sets of connections between the data and command dispatcher and the graphics processor core. Compared to a fully connected approach between the data and command dispatcher and the graphics processor core, the connection method provided in this embodiment requires fewer connections, which helps avoid congestion during the P&R stage and reduces chip area.

[0067] It should be understood that, Figure 4 The connection method between the data and command dispatcher and the graphics processor core when N=4 is shown as only one feasible embodiment of this application, but this application is not limited thereto. In some implementations, the graphics processor core connected to the data and command dispatcher can be... Figure 4 Different implementations exist; for example, data and command dispatcher 410-1 may connect to 430-2 instead of 430-1, and data and command dispatcher 410-3 may connect to 430-2 and 430-4 instead of 430-1 and 430-3. In other implementations, the number of graphics processing unit cores connected to the data and command dispatcher can be [missing information]. Figure 4 Different, for example, the data and command distributor 410-1 can connect to 2, 3 or 4 graphics processor cores, while the data and command distributor 410-2 can connect to 1, 2 or 3 graphics processor cores.

[0068] It should be noted that, in order to improve kernel utilization efficiency, the above example uses all four graphics processor cores for all virtual graphics processors provided by the graphics processor at the same time, but this application is not limited to this. For example, when the graphics processor 400 is configured to provide only one virtual graphics processor, the user can use two graphics processor cores 430-1 and 430-3 through the data and command distributor 410-2, while the other two graphics processor cores 430-2 and 430-4 are idle. As another example, when the graphics processor 400 is configured to provide two virtual graphics processors, the first user can use one graphics processor core 430-1 through the data and command distributor 410-1, and the second user can use two graphics processor cores 430-2 and 430-4 through the data and command distributor 410-4, while the other graphics processor core 430-3 is idle.

[0069] In one embodiment of this application, the graphics processor includes N data and command dispatchers, one of which is connected to N graphics processor cores, wherein m j -m j+1A data and command dispatcher with Each graphics processing unit core is connected, m j and m j+1 Let m be adjacent positive integers that are divisible by N, 1 ≤ m j+1 <m j ≤N. For example, when N=4, m j and m j+1 The value includes two types: m j+1 =1 and m j =2,m j+1 =2 and m j =4. Based on this, when the graphics processor provided in this embodiment includes 4 data and command dispatchers, one of the data and command dispatchers is connected to 4 graphics processor cores, and the other data and command dispatcher is connected to 2 graphics processor cores (m j+1 =1 and m j =2), where the other two data and command dispatchers are each connected to one graphics processor core (m j+1 =2 and m j =4). In the embodiments of this application, the connection method between the data and command distributor and the graphics processor core includes, but is not limited to, the data and command distributor being directly connected to the graphics processor core, or the data and command distributor being indirectly connected to the graphics processor core through a data selector, etc.

[0070] The following sections will provide a detailed explanation of the above connection schemes using N=8 and N=16 as examples. Please refer to [link / reference]. Figure 5A In one example, N=8, and the graphics processor 500 includes 8 data and command dispatchers. One of these data and command dispatchers, 510-1, is directly connected to graphics processor core 530-1 and indirectly connected to graphics processor cores 530-2 through 530-8 via data selectors. Another data and command dispatcher, 510-5, is indirectly connected to four graphics processor cores 530-5 through 530-8 via data selectors (m... j+1 =1,m j =2). For the two data and command dispatchers 510-3 and 510-7, data and command dispatcher 510-3 is indirectly connected to the two graphics processor cores 530-3 and 530-4 via a data selector, and data and command dispatcher 510-7 is indirectly connected to the two graphics processor cores 530-7 and 530-8 via a data selector (m j+1 =2,m j =4). The four data and command dispatchers 510-2, 510-4, 510-6, and 510-8 are each indirectly connected to their corresponding graphics processor cores 530-2, 530-4, 530-6, and 530-8 via data selectors (mj+1 =4,m j =8).

[0071] Figure 5A The graphics processor 500 shown can be configured to provide 1 to 8 virtual graphics processors, supporting a minimum of 1 user (when the graphics processor 500 is configured to provide 1 virtual graphics processor) and a maximum of 8 users (when the graphics processor 500 is configured to provide 8 virtual graphics processors). The graphics processor cores of the graphics processor 500 have 22 possible allocation configurations, as shown in Table 1 below. For example, in configuration 10, the graphics processor 500 is configured to provide 3 virtual graphics processors for 3 users, with two users occupying 3 graphics processor cores and the other user occupying 2 graphics processor cores. Combined with... Figure 5A The graphics processor core allocation scheme can be as follows: the first user occupies graphics processor cores 530-1, 530-2, and 530-8; the second user occupies graphics processor cores 530-5, 530-6, and 530-7; and the third user occupies graphics processor cores 530-3 and 530-4.

[0072] It should be noted that the connection method between the data and command dispatcher and the graphics processor core in this application embodiment is not unique, and other connection methods may also be used in some other implementations. For example, Figure 5B This is shown as another connection scheme when N=8. This scheme is similar to... Figure 5A The connection scheme shown has the same effect.

[0073] Table 1. Core Count Allocation of the Graphics Processor 500

[0074]

[0075] In the above example, the connection between the data and command dispatcher and the graphics processing unit (GPU) core is simplified to one one-to-eight connection (1×8 sets of connections), one one-to-four connection (1×4 sets of connections), two one-to-two connections (2×2 sets of connections), and four one-to-one connections (4×1 sets of connections). Therefore, in this embodiment, there are a total of 20 sets of connections between the data and command dispatcher and the GPU core. Each set of connections is, for example, a set of 1000 to 2000 data and command connections. Compared to a fully connected approach between the data and command dispatcher and the GPU core, the connection method provided in this example requires fewer connections, which helps avoid congestion problems during the P&R stage and reduces chip area.

[0076] Please see Figure 5CIn another example, N=16, and the graphics processor contains 16 data and command dispatchers. The first data and command dispatcher is directly connected to the first graphics processor core and indirectly connected to the remaining 15 graphics processor cores via data selectors. The ninth data and command dispatcher is indirectly connected to 8 graphics processor cores via data selectors. The second data and command dispatcher is indirectly connected to 5 graphics processor cores via data selectors. The seventh data and command dispatcher is indirectly connected to 4 graphics processor cores via data selectors. The sixteenth data and command dispatcher is indirectly connected to 3 graphics processor cores via data selectors. The fourth, eleventh, and thirteenth data and command dispatchers are indirectly connected to 2 graphics processor cores via data selectors. The third, fifth, sixth, eighth, tenth, twelfth, fourteenth, and fifteenth data and command dispatchers are indirectly connected to 1 graphics processor core via a data selector. In this example, the connection between the data and command dispatcher and the graphics processing unit (GPU) core is simplified to one-to-sixteen connections (1×16 sets of connections), one-to-eight connections (1×8 sets of connections), one-to-five connections (1×5 sets of connections), one-to-four connections (1×4 sets of connections), one-to-three connections (1×3 sets of connections), three-to-two connections (3×2 sets of connections), and eight-to-one connections (8×1 sets of connections). Therefore, in this embodiment, there are a total of 50 sets of connections between the data and command dispatcher and the GPU core. Compared to a fully interconnected approach, this example requires fewer connections, which helps avoid congestion during the production and delivery (P&R) phase and reduces chip area.

[0077] In one embodiment of this application, the graphics processor may further include a data selector. A graphics processor core that connects to at least two data and command dispatchers is indirectly connected to the data and command dispatchers via the data selector. For example, Figure 5A The graphics processor 500 shown includes data selectors 520-2 to 520-8. For a graphics processor core that connects to at least two data and command dispatchers, such as graphics processor core 530-5, the data selector is indirectly connected to the corresponding data and command dispatcher. In this embodiment, the data selector can connect to at most one data and command dispatcher to the graphics processor core at any given time.

[0078] Alternatively, for a graphics processor core that only needs to connect to one data and command dispatcher, such as graphics processor core 530-1, it is not necessary to connect to the data and command dispatcher through a data selector.

[0079] It should be understood that the data selector described in the embodiments of this application includes all devices or circuits capable of selecting a specified signal from a set of input signals and outputting it, and is not limited to a specific device or circuit. In one embodiment of this application, the data and command distributor is fully connected to the graphics processing unit (GPU) core. Full connection means that each data and command distributor is connected to all GPU cores, and each GPU core is connected to all data and command distributors. The connection method between the data and command distributor and the GPU core includes, but is not limited to, direct connection between the data and command distributor and the GPU core, or indirect connection between the data and command distributor and the GPU core through a data selector, etc. Figure 6 The diagram shows an example of a data and command dispatcher fully connected to the graphics processor core when N=8. In this case, the graphics processor can be configured to provide 1 to 8 virtual graphics processors and can meet all the allocation scenarios of the processor core.

[0080] In one embodiment of this application, the number of physical layers of the graphics processor is configured based on the number of data and command transmission lines. Specifically, there is a maximum limit to the number of data and command transmission lines contained in each physical layer of the graphics processor; the fewer the number of data and command transmission lines, the fewer the number of physical layers of the graphics processor. Taking N=8 as an example, when the data and command dispatcher is fully connected to the graphics processor core, the number of data and command transmission lines is 64, and the number of physical layers of the graphics processor is configured as 8. When using... Figure 5A or Figure 5B With the connection method shown, the number of data and command transmission lines is 20, and the number of physical layers of the graphics processor can be configured to 4. At this time, using... Figure 5A or Figure 5B The wiring method shown can reduce the number of physical layers in the graphics processor.

[0081] This application also provides a chip. Figure 7 The diagram shown is a schematic representation of a chip in one embodiment of this application. The chip includes a graphics processor and input / output pins as described in any embodiment of this application.

[0082] This application also provides an electronic device, which includes a graphics processor as described in any embodiment of this application and a memory communicatively connected to the graphics processor.

[0083] In summary, the graphics processor provided in this application can provide at least one virtual graphics processor, enabling multiple users to share the graphics processor through virtualization. In some embodiments of this application, by optimizing the connection method between the data and command dispatcher and the graphics processor core, the number of connections between them can be reduced, avoiding congestion problems during chip placement and routing, and thus reducing chip area and the number of physical layers in the graphics processor. Therefore, this application effectively overcomes the various shortcomings of the prior art and has high industrial applicability.

[0084] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this application should still be covered by the claims of this application.

Claims

1. A graphics processor, characterized in that, The graphics processor includes at least two data and command dispatchers and at least two graphics processor cores, each of the data and command dispatchers being connected to at least one of the graphics processor cores, wherein one of the data and command dispatchers and one of the graphics processor cores are connected via a set of data and command transmission lines; The graphics processor is configured to provide at least one virtual graphics processor, each of the virtual graphics processors including one of the data and command dispatchers and some or all of the graphics processor cores connected thereto; The graphics processor is configured to provide according to the received instructions. The virtual graphics processor, wherein Less than or equal to any positive integer, The number of graphics processor cores; The graphics processor includes One of the data and command distributors, wherein one of the data and command distributors is with The graphics processor cores are connected, and in them The data and command distributor mentioned above and The graphics processor cores are connected together. and For adjacent ones that can be Divisible positive integers, .

2. The graphics processor according to claim 1, characterized in that, The graphics processor's first The data and command distributor mentioned above and The graphics processor cores are connected together, wherein and All are less than or equal to positive integers, This is the floor function.

3. The graphics processor according to claim 2, characterized in that, The graphics processor also includes a data selector, through which the graphics processor core, which connects to at least two of the data and command distributors, is connected to the data and command distributors.

4. The graphics processor according to claim 2, characterized in that, The number of data and command distributors and the number of graphics processor cores are both 8. The connection methods between the data and command distributors and the graphics processor cores include one-to-eight connection, one-to-four connection, two-to-two connection, and four-to-one connection.

5. The graphics processor according to claim 1, characterized in that, The number of physical layers of the graphics processor is configured according to the number of data and command transmission lines.

6. The graphics processor according to claim 1, characterized in that, The data and command distributor is fully connected to the graphics processor core.

7. A chip, characterized in that, The chip includes a graphics processor as described in any one of claims 1 to 6 and input / output pins.

8. An electronic device, characterized in that, The electronic device includes a graphics processor and a memory as described in any one of claims 1 to 6.

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