Semiconductor-on-insulator structure and method of manufacturing the same

Abstract

The application relates to a semiconductor-on-insulator structure and a manufacturing method thereof, the manufacturing method comprising: obtaining a wafer; the wafer comprising a substrate and an insulating layer on the substrate; performing a patterning treatment on the insulating layer to form a groove array which is mutually connected and exposes the substrate, the groove array divides the insulating layer into a plurality of block structures; forming an epitaxial layer on the substrate and the insulating layer, the epitaxial layer covers the substrate and the semiconductor layer. The application divides the insulating layer into a plurality of block structures through the groove array, so that the stress of the insulating layer on the substrate can be reduced. Moreover, the epitaxial layer is connected with the substrate, so that the stress of the wafer can be further reduced, and the substrate potential can be led out from the wafer upper surface.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor manufacturing, and in particular to a semiconductor-on-insulator structure and a method for manufacturing a semiconductor-on-insulator structure. BACKGROUND

[0002] SOI (Silicon on Insulator) refers to a silicon-on-insulator technology. The SOI process technology is a full dielectric isolation technology, which makes devices on a top silicon film, and a layer of oxide between the top silicon film and the substrate as an isolation. This technology completely eliminates the latch-up effect of the traditional bulk silicon process, has small parasitic capacitance, and has the advantages of high speed, low power consumption, high integration, and high reliability. Therefore, the SOI substrate is more and more widely used in integrated circuit technology, and the existence of the body buried oxide layer (BOX) greatly improves the process reliability.

[0003] However, as the voltage resistance of integrated devices increases, the thickness of the buried oxide layer and the thickness of the top silicon layer on the buried oxide layer need to be increased accordingly, which will cause stress damage to the buried oxide layer, the top silicon layer, and the top silicon layer in the deep trench etching process. SUMMARY

[0004] Therefore, it is necessary to provide a method for manufacturing a semiconductor-on-insulator structure with less stress of a wafer.

[0005] A method for manufacturing a semiconductor-on-insulator structure, comprising: obtaining a wafer; the wafer comprising a substrate and an insulating layer on the substrate; performing a patterning process on the insulating layer to form a groove array that is in communication with each other and exposes the substrate, the groove array divides the insulating layer into a plurality of block structures; forming an epitaxial layer on the substrate and the insulating layer, the epitaxial layer covers the substrate and the semiconductor layer.

[0006] The above-mentioned method for manufacturing a semiconductor-on-insulator structure divides the insulating layer into a plurality of block structures through the groove array, which can reduce the stress of the insulating layer on the substrate. And the epitaxial layer is connected together with the substrate through the groove array (instead of being completely isolated by the insulating layer), which can further reduce the stress of the wafer.

[0007] In one embodiment, the obtained wafer further comprises a semiconductor layer on the insulating layer; the step of performing a patterning process on the insulating layer comprises performing a patterning process on the insulating layer and the semiconductor layer, the groove array divides the semiconductor layer and the insulating layer into a plurality of block structures; the step of forming an epitaxial layer on the substrate and the insulating layer comprises epitaxially forming an epitaxial layer on the substrate and the semiconductor layer, the epitaxial layer directly connects the substrate and the semiconductor layer.

[0008] In one embodiment, the substrate, the semiconductor layer and the epitaxial layer are made of silicon.

[0009] In one embodiment, the semiconductor-on-insulator structure is a silicon-on-insulator structure.

[0010] In one embodiment, the insulating layer is an oxygen buried layer.

[0011] In one embodiment, the oxygen buried layer is made of silicon oxide.

[0012] In one embodiment, the step of patterning the insulating layer and the semiconductor layer includes photoetching on the semiconductor layer and etching the semiconductor layer and the insulating layer.

[0013] In one embodiment, after the step of epitaxially forming the epitaxial layer on the substrate and the semiconductor layer, a step of planarizing the upper surface of the epitaxial layer is further included.

[0014] In one embodiment, after the step of planarizing the upper surface of the epitaxial layer, a step of forming semiconductor components on the insulating layer of each block structure is further included.

[0015] It is also necessary to provide a semiconductor-on-insulator structure.

[0016] A semiconductor-on-insulator structure includes a substrate, a plurality of insulating blocks arranged on the substrate, and a semiconductor material layer arranged on each of the insulating blocks and directly connected to the substrate through the gaps between the insulating blocks, wherein each of the insulating blocks is used to form a semiconductor component.

[0017] The semiconductor-on-insulator structure described above, the insulating layer is a plurality of small blocks separated from each other, which can reduce the stress of the insulating layer on the substrate. Moreover, the semiconductor material layer is connected to the substrate, which can further reduce the stress of the wafer.

[0018] In one embodiment, the semiconductor material layer includes a semiconductor layer including a plurality of block structures arranged one-to-one on each of the insulating blocks, and an epitaxial layer arranged on each of the block structures of the semiconductor layer and directly connected to the substrate through the gaps between the insulating blocks.

[0019] In one embodiment, the substrate, the semiconductor layer and the epitaxial layer are made of silicon.

[0020] In one embodiment, the semiconductor-on-insulator structure is a silicon-on-insulator structure.

[0021] In one embodiment, the insulating layer is an oxygen buried layer.

[0022] In one embodiment, the buried oxide layer comprises silicon oxide.

[0023] In one embodiment, each of the insulating blocks has a thickness greater than 3 microns, and the total thickness of the semiconductor layer and the epitaxial layer is greater than 15 microns.

[0024] In one embodiment, each of the insulating blocks has a cross-sectional shape of a rectangle, a square, a trapezoid, an ellipse, or an irregular shape. BRIEF DESCRIPTION OF DRAWINGS

[0025] For a better understanding of those embodiments and / or examples of the application herein disclosed, reference can be made to the accompanying drawings. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed applications, presently described embodiments and / or examples, and the best mode presently contemplated of these applications.

[0026] Figure 1 is a flow chart of a method of manufacturing a semiconductor-on-insulator structure in one embodiment;

[0027] Figures 2a to 2d is a flow chart of a method of manufacturing a semiconductor-on-insulator structure in one embodiment; Figure 1 is a cross-sectional view of a semiconductor structure during the manufacture of a semiconductor-on-insulator structure using the method shown in

[0028] Figure 3 is a top view of an insulating layer being divided by an array of trenches in one embodiment;

[0029] Figure 4 is a perspective view of a semiconductor-on-insulator structure in one embodiment. DETAILED DESCRIPTION

[0030] For the purposes of this application, a more complete description of the application will be provided with reference to the associated drawings. The preferred embodiments of the application are illustrated in the drawings. However, the application can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and fully convey the scope of the application to those skilled in the art.

[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in the description of the application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0032] It will be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it can be directly on or connected to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on" or "directly connected to" another element or layer, there are no intervening elements or layers present. It will also be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application.

[0033] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0034] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0035] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of ideal embodiments (and intermediate structures). Thus, variations in the shape shown can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing processes. For example, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of the regions of the device and are not intended to limit the scope of the invention.

[0036] The semiconductor terminology used in this article is the technical terminology commonly used by those skilled in the art. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents heavily doped P-type, P type represents moderately doped P-type, P- type represents lightly doped P-type, N+ type represents heavily doped N-type, N type represents moderately doped N-type, and N- type represents lightly doped N-type.

[0037] The SOI structure also has corresponding disadvantages due to the presence of the buried oxide layer, including: 1. The silicon layers above and below the buried oxide layer are separated by the buried oxide layer. Since the heat dissipation capacity of silicon dioxide is extremely poor, far inferior to that of silicon, heat dissipation is poor, and heat easily accumulates in the silicon film, resulting in the SOI self-heating effect; 2. The silicon layers above and below the buried oxide layer cannot be directly shorted to ground; 3. As the withstand voltage of integrated devices increases, the thickness of the buried oxide layer and the top silicon layer on the buried oxide layer need to be increased accordingly. This will lead to stress damage to the buried oxide layer, the top silicon layer, and the top silicon layer during deep trench etching. For example, for thick-top silicon SOI wafers, the SOI epitaxial growth process and subsequent integrated circuit processing steps (such as furnace tube process, deep trench isolation DTI etching, filling, etc.) can bring great stress to the wafer, causing wafer warping and causing problems with the in-line flow of the wafer during the manufacturing process, such as photolithography alignment. Excessive stress can also reduce the quality of the film layer and bring many defects, such as gate oxide often failing GOI (gate oxide integrity) / TDDB (time-delayed insulation breakdown).

[0038] The technical solution of this application can obtain a thick-top silicon-on-insulator (SOI) wafer while avoiding wafer warpage. This application provides a method for manufacturing a semiconductor-on-insulator structure, comprising the following steps:

[0039] Obtaining a wafer; the wafer includes a substrate and an insulating layer on the substrate;

[0040] patterning the insulating layer to form a trench array that exposes the substrate and that is in communication with the trench array, the trench array dividing the insulating layer into a plurality of block structures;

[0041] forming an epitaxial layer on the substrate and the insulating layer, the epitaxial layer covering the substrate and the semiconductor layer.

[0042] Figure 1 is a flowchart of a method of fabricating a semiconductor-on-insulator structure in an embodiment, including the following steps:

[0043] S110, obtaining a wafer.

[0044] Referring to Figure 2a In an embodiment of the present application, the wafer includes, from bottom to top, a substrate 10, an insulating layer 12, and a semiconductor layer 14.

[0045] In an embodiment of the present application, the substrate 10 and the semiconductor layer 14 can include the same or different semiconductor materials. The semiconductor materials can be, for example, any of Si, Ge, SiGe, SiC, SiGeC, and III / V compound semiconductors. In an embodiment of the present application, the substrate 10 and the semiconductor layer 14 are both composed of silicon. In other embodiments of the present application, the substrate 10 and the semiconductor layer 14 can also be composed of silicon germanium. In an embodiment of the present application, the semiconductor layer 14 is an undoped semiconductor material, while the substrate 10 can include a doped or undoped semiconductor material. In an embodiment of the present application, the substrate 10 is a non-semiconductor material including, for example, a dielectric material and / or a conductive material.

[0046] In embodiments in which the substrate 10 and the semiconductor layer 14 include semiconductor materials, the substrate 10 and the semiconductor layer 14 can have the same or different crystal orientations. For example, the substrate 10 and / or the semiconductor layer 14 can have a crystal orientation of {100}, {110}, or {111}. Other crystal orientations can also be used in the present application, in addition to the specifically mentioned crystal orientations. The substrate 10 and / or the semiconductor layer 14 can be a single-crystal semiconductor material, a polycrystalline material, or an amorphous material. In an embodiment of the present application, at least the semiconductor layer 14 is a single-crystal semiconductor material, such as single-crystal silicon. In certain embodiments, the semiconductor layer 14 can be processed to include semiconductor regions having different crystal orientations.

[0047] The insulating layer 12 can be a crystalline or amorphous oxide or nitride. In an embodiment of the present application, the insulating layer 12 is an oxide, such as silicon dioxide. In an embodiment of the present application, the insulating layer 12 is a buried oxide layer.

[0048] In an embodiment of the present application, Figure 2aThe structure shown can be formed using a process known as SIMOX (oxygen ion implantation isolation). In another embodiment, Figure 2a The structure shown can be formed by a layer transfer process that bonds two semiconductor wafers together, one of which includes an insulating layer 12, i.e., an oxide layer. In yet another embodiment, Figure 2a The structure shown can be formed by depositing an insulating material and a semiconductor material on the substrate 10. In any of the processes described above, an optional thinning step can be used to thin the semiconductor layer 14 to a desired and predetermined thickness value. This optional thinning step may include, for example, planarization or etching.

[0049] S120 involves patterning the insulating and semiconductor layers to form an interconnected trench array that exposes the substrate.

[0050] Figure 2b This is a cross-sectional schematic diagram of a semiconductor structure in which a trench array 13 is formed according to an embodiment of this application. Figure 3 In one embodiment of this application, the insulating layer 12 is covered by the trench array 13 ( Figure 3 A top view (not shown in the image) showing the segmentation, in which the trench array 13 is... Figure 3 The trench array 13 is cross-shaped. Within the entire wafer, the trench array 13 divides the semiconductor layer 14 and the insulating layer 12 into multiple block-like structures. On the plane, the horizontal and vertical trenches in the trench array 13 are interconnected, resembling a chessboard shape. Figure 3 In the illustrated embodiment, the block structure segmented by the trench array 13 is rectangular; in other embodiments, the trench array 13 may also be other patterns, for example, some or all of the trenches may not be straight, and the block structure of the insulating layer 12 and the semiconductor layer 14 may also be other shapes, such as trapezoidal, elliptical or irregular shapes.

[0051] In one embodiment of this application, photoresist can be coated on the semiconductor layer 14, and then exposed and developed using a corresponding photomask. The semiconductor layer 14 and the insulating layer 12 are then etched to obtain the trench array 13. The photoresist, which serves as an etching barrier layer during the etching process, is then removed. Within the capabilities of the etching process and the ability of the subsequent step S130 to fill the trench array 13, this application does not limit the thickness of the semiconductor layer 14 or the width of each trench in the trench array 13.

[0052] S130, an epitaxial layer is formed on the substrate and the semiconductor layer, and the epitaxial layer directly connects the substrate and the semiconductor layer.

[0053] Reference Figure 2cAn epitaxial layer 16 is formed on the substrate 10 and the semiconductor layer 14 using an epitaxial process. The semiconductor layer 14 is directly connected to the substrate 10 through the epitaxial layer 16. The substrate 10, the insulating layer 12, the semiconductor layer 14, and the epitaxial layer 16 can be collectively referred to as a semiconductor-on-insulator structure in this application.

[0054] In one embodiment of this application, after step S130, the upper surface of the epitaxial layer 16 can be planarized to obtain the following: Figure 2d The structure is shown. In one embodiment of this application, the planarization process can be performed using chemical mechanical polishing (CMP). Figure 4 This is a three-dimensional schematic diagram of the semiconductor-on-insulator structure after planarization in one embodiment. To better illustrate this structure, [the diagram is shown here]. Figure 4 Some parts of the structure have been made transparent.

[0055] The above-described method for manufacturing a semiconductor-on-insulator structure reduces the stress on the substrate 10 caused by dividing the insulating layer 12 into multiple block structures using the trench array 13. Furthermore, the epitaxial layer 16 is connected to the substrate 10 (rather than being completely isolated by the insulating layer 12), further reducing wafer stress. Because the epitaxial layer 16 is connected to the substrate 10, the substrate potential can be extracted from the upper surface of the wafer.

[0056] Because the stress on the wafer is reduced, the above-described method for manufacturing semiconductor-on-insulator structures can be used to manufacture thick top silicon layer SOI wafers, and the resulting wafers can avoid wafer warping caused by excessively thick top silicon layer and buried oxide layer.

[0057] In one embodiment of this application, the following is obtained: Figure 2d Following the structure shown, semiconductor devices, such as various metal-oxide-semiconductor (MOS) structures or transistors, can be formed on the insulating layer 12 of each block structure.

[0058] This application correspondingly provides a semiconductor-on-insulator structure, which can be manufactured using the manufacturing method of the semiconductor-on-insulator structure described in any of the foregoing embodiments. See also Figure 4 In one embodiment of this application, the semiconductor-on-insulator structure includes a substrate 10, a plurality of insulating blocks 12 on the substrate 10, and a semiconductor material layer disposed on each insulating block 12 and directly connected to the underlying substrate 10 through gaps between the insulating blocks 12. Figure 4In the illustrated embodiment, the semiconductor material layer includes a semiconductor layer 14 and an epitaxial layer 16. The semiconductor layer 14 includes a plurality of block structures disposed one-to-one on each of the insulating blocks 12 (i.e., one block structure of the semiconductor layer 14 is disposed on each of the insulating blocks 12, and the cross-section of the block structure of the semiconductor layer 14 is the same as the cross-section of the corresponding insulating block 12). The epitaxial layer 16 is disposed on each of the semiconductor layers 14 and is directly connected to the underlying substrate 10 through the gaps between the insulating blocks 12. Each of the insulating blocks 12 is used to form semiconductor devices, such as various MOS structures or transistors, etc.

[0059] The above semiconductor-on-insulator structure, in which the insulating layer 12 is divided into a plurality of small blocks, can reduce the stress of the insulating layer 12 on the substrate 10. Moreover, the semiconductor material layer is connected to the substrate 10 (rather than being completely isolated by the insulating layer 12), which can further reduce the stress of the wafer and can lead the substrate potential out of the top surface of the wafer.

[0060] Because the stress of the wafer is reduced, the above semiconductor-on-insulator structure is particularly suitable for thick top silicon SOI wafers, and the wafer using the above semiconductor-on-insulator structure can avoid wafer warping caused by a too thick top silicon layer and a too thick buried oxide layer. Specifically, for an SOI wafer in which the thickness of the buried oxide layer is greater than 3 microns and the thickness of the top silicon layer on the buried oxide layer is greater than 15 microns, wafer warping is likely to occur. It can be understood that the present application is also applicable to SOI structures in which the top silicon layer and the buried oxide layer have any thickness.

[0061] In one embodiment of the present application, the block structures of the insulating layer 12 and the semiconductor layer 14 can also have shapes other than rectangular, such as trapezoidal, elliptical, irregular, etc.

[0062] In one embodiment of the present application, the substrate 10 and the semiconductor layer 14 can include the same or different semiconductor materials. The semiconductor material can be, for example, any of Si, Ge, SiGe, SiC, SiGeC, and III / V compound semiconductors. In one embodiment of the present application, the substrate 10 and the semiconductor layer 14 are both composed of silicon. In other embodiments of the present application, the substrate 10 and the semiconductor layer 14 can also be composed of silicon germanium. In one embodiment of the present application, the semiconductor layer 14 is an undoped semiconductor material, while the substrate 10 can include a doped or undoped semiconductor material. In one embodiment of the present application, the substrate 10 is a non-semiconductor material including, for example, a dielectric material and / or a conductive material.

[0063] In embodiments where the substrate 10 and the semiconductor layer 14 comprise a semiconductor material, the substrate 10 and the semiconductor layer 14 can have the same or different crystal orientations. For example, the substrate 10 and / or the semiconductor layer 14 can have a crystal orientation of {100}, {110}, or {111}. Other crystal orientations can also be used in the present application, unless specifically mentioned. The substrate 10 and / or the semiconductor layer 14 can be a single crystalline semiconductor material, a polycrystalline material, or an amorphous material. In one embodiment of the present application, at least the semiconductor layer 14 is a single crystalline semiconductor material, such as single crystalline silicon. In some embodiments, the semiconductor layer 14 can be processed to include semiconductor regions having different crystal orientations.

[0064] The insulating layer 12 can be a crystalline or amorphous oxide or nitride. In one embodiment of the present application, the insulating layer 12 is an oxide, such as silicon dioxide. In one embodiment of the present application, the insulating layer 12 is an oxygen buried layer.

[0065] The substrate 10, the insulating layer 12, the semiconductor layer 14, and the epitaxial layer 16 can be collectively referred to as a semiconductor-on-insulator structure in the present application.

[0066] It should be understood that although the steps in the flowcharts of the present application are shown in a sequence as indicated by arrows, the steps are not necessarily executed in the order as indicated by the arrows. Unless specifically mentioned herein, the steps are not necessarily limited in the order of execution, and the steps can be executed in other orders. Moreover, at least some of the steps in the flowcharts of the present application can include multiple steps or stages, which are not necessarily executed at the same time, but can be executed at different times. The steps or stages are not necessarily executed in sequence, but can be executed in rotation or alternation with at least some of the steps or stages in other steps or stages.

[0067] In the description of the present specification, the description of the terms "some embodiments", "other embodiments", "ideal embodiments", and the like means that the specific features, structures, materials, or characteristics described in connection with the embodiments or examples are included in at least one embodiment or example of the present application. The illustrative description of the above terms in the present specification does not necessarily mean the same embodiment or example.

[0068] The technical features of the above-described embodiments can be combined in any manner. In order to make the description brief, all possible combinations of the technical features in the above-described embodiments are not described, but it should be considered that any combination of the technical features is within the scope of the present specification, as long as the combination does not cause contradiction.

[0069] The above embodiments only express several implementation manners of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the scope of the patent. It should be noted that for ordinary skilled persons in the art, without departing from the concept of the present application, several modifications and improvements can be made, which are within the scope of protection of the present application. Therefore, the protection scope of the patent of the present application should be subject to the appended claims.

Claims

1. A method for manufacturing a semiconductor-on-insulator structure, comprising: obtaining a wafer; the wafer comprising a substrate, an insulating layer on the substrate, and a semiconductor layer on the insulating layer; performing a patterning process on the insulating layer and the semiconductor layer to form an array of trenches that are in communication with each other and expose the substrate, the array of trenches dividing the semiconductor layer and the insulating layer into a plurality of block structures; forming an epitaxial layer on the substrate and the insulating layer, including epitaxially forming the epitaxial layer on the substrate and the semiconductor layer, the epitaxial layer covering the substrate and the semiconductor layer, and the epitaxial layer directly connecting the substrate and the semiconductor layer; the insulating layer is a buried oxide layer, the substrate, the semiconductor layer, and the epitaxial layer all comprise silicon, the substrate and the semiconductor layer are both composed of silicon, the semiconductor-on-insulator structure is a silicon-on-insulator structure, and the semiconductor layer and the epitaxial layer are top silicon layers on the buried oxide layer.

2. The method of manufacturing a semiconductor-on-insulator structure according to claim 1, characterized in that, after the step of epitaxially forming the epitaxial layer on the substrate and the semiconductor layer, further comprising a step of performing a planarization process on an upper surface of the epitaxial layer.

3. The method of manufacturing a semiconductor-on-insulator structure according to claim 2, wherein after the step of performing the planarization process on the upper surface of the epitaxial layer, further comprising a step of forming a semiconductor component on the insulating layer of each of the block structures.

4. A semiconductor-on-insulator structure, characterized in that a semiconductor-on-insulator structure manufactured by the method for manufacturing a semiconductor-on-insulator structure according to any one of claims 1-3, comprising: a substrate; a plurality of insulating blocks arranged on the substrate; a semiconductor material layer arranged on each of the insulating blocks and directly connecting the substrate through gaps between the insulating blocks; wherein each of the insulating blocks is used to form a semiconductor component, and the semiconductor material layer comprises: a semiconductor layer comprising a block structure arranged on each of the insulating blocks in a one-to-one correspondence; an epitaxial layer arranged on each of the block structures of the semiconductor layer and directly connecting the substrate through the gaps between the insulating blocks.

5. The semiconductor-on-insulator structure of claim 4, wherein the semiconductor layer is a silicon layer. a thickness of each of the insulating blocks is greater than 3 microns, and a total thickness of the semiconductor layer and the epitaxial layer is greater than 15 microns.

6. The semiconductor-on-insulator structure of claim 4, wherein the semiconductor layer has a thickness of about 50 nm to about 200 nm. a cross-sectional shape of each of the insulating blocks is rectangular, square, trapezoidal, elliptical, or irregular.

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