Chip high-density interconnection packaging structure and manufacturing method thereof

Abstract

The application provides a chip high-density interconnection packaging structure, which comprises a glass carrier plate with a groove and a glass frame surrounding the groove, a first through-hole column penetrating through the glass frame, a second through-hole column penetrating through the groove, a first circuit layer and a second circuit layer formed on the upper and lower surfaces of the glass frame and electrically connected through the first through-hole column, a third circuit layer and a fourth circuit layer formed on the upper and lower surfaces of the groove and electrically connected through the second through-hole column, a chip connecting bridge mounted on the third circuit layer in the groove, a fifth circuit layer formed on the first circuit layer, and at least two chips mounted on the second circuit layer and the fourth circuit layer; wherein the chip connecting bridge has a first pad and the first pad is connected with the third circuit layer, the pins of the two chips are respectively connected with the fourth circuit layer and / or the second circuit layer, and the fifth circuit layer is connected with the first circuit layer. A manufacturing method of the chip high-density interconnection packaging structure is also provided.

Description

Technical Field

[0001] This application relates to the field of semiconductor packaging technology, and in particular to a high-density interconnect packaging structure for chips and its fabrication method. Background Technology

[0002] With the rapid development of electronic technology, the performance requirements of electronic products are becoming increasingly demanding, leading to more complex circuitry in electronic devices and circuit boards. Simultaneously, the size requirements for electronic products are shrinking and thinning, making high-density integration, miniaturization, and multi-functionality of chips and other electronic components, packaging substrates, and packaging structures an inevitable trend. As chip linewidths and spacing continue to shrink, further miniaturization becomes increasingly difficult. Furthermore, to achieve high-density integration, miniaturization, and multi-functionality, the wiring on packaging substrates is becoming increasingly complex, demanding more layers and finer wiring. To meet higher performance requirements for electronic products, multiple chips can be integrated into a single package. To achieve miniaturization of multi-chip integrated packages, interconnecting these chips has become a growing trend.

[0003] In related technologies, there are many ways to achieve multi-chip interconnection. One typical method is 2.5D packaging, which sets a TSV interposer between the carrier board and the chip, and uses the TSV interposer to achieve interconnection between chips and between chips and the packaging carrier board.

[0004] However, in related technologies, on the one hand, the TSV interposer significantly increases the cost of chip interconnection. Furthermore, the thicker TSV interposer increases the size of the package module, making it impossible to truly achieve a small and thin package module. On the other hand, the TSV interposer offers limited design freedom for multi-chip interconnection, and in 2.5D package structures, chips are mounted on the surface of the TSV interposer, with the interposer and package substrate soldered together for interconnection, resulting in relatively low integration. Summary of the Invention

[0005] In view of this, the purpose of this application is to propose a high-density interconnect packaging structure for chips and a method for fabricating the same.

[0006] In a first aspect, this application provides a high-density interconnect package structure for chips, including a glass substrate having a groove and a glass frame surrounding the groove, a first through-hole post penetrating the glass frame, a second through-hole post penetrating the groove, a first circuit layer and a second circuit layer formed on the upper and lower surfaces of the glass frame and electrically connected through the first through-hole post, a third circuit layer and a fourth circuit layer formed on the upper and lower surfaces of the groove and electrically connected through the second through-hole post, a chip connection bridge mounted on the third circuit layer within the groove, a fifth circuit layer formed on the first circuit layer, and at least two chips mounted on the second circuit layer and the fourth circuit layer; wherein the chip connection bridge has a first pad and the first pad is connected to the third circuit layer, the pins of the two chips are each connected to the fourth circuit layer and / or the second circuit layer, and the fifth circuit layer is connected to the first circuit layer.

[0007] Secondly, this application provides a method for fabricating a high-density interconnect packaging structure for a chip, comprising:

[0008] A glass substrate is partially etched to form a groove and a glass frame surrounding the groove, and a first through hole and a second through hole are formed in the glass frame and the groove along the height direction;

[0009] The glass carrier plate is metallized, a first circuit layer and a second circuit layer are formed on the upper and lower surfaces of the glass frame, a third circuit layer and a fourth circuit layer are formed on the upper and lower surfaces of the groove, and the first through hole is filled to form a first through hole post, and the second through hole is filled to form a second through hole post, such that the first through hole post is conductively connected to the first circuit layer and the second circuit layer, and the second through hole post is conductively connected to the third circuit layer and the fourth circuit layer.

[0010] A chip connection bridge is mounted in the groove, such that the first pad of the chip connection bridge is connected to the third circuit layer;

[0011] A lamination encapsulation layer is applied so that the encapsulation layer covers the first circuit layer and the chip connection bridge;

[0012] A fifth circuit layer is formed on the encapsulation layer, such that the first circuit layer is connected to the fifth circuit layer;

[0013] An insulating layer is formed on the fifth circuit layer, and a sixth circuit layer is formed on the insulating layer, such that the fifth circuit layer and the sixth circuit layer are connected.

[0014] At least two chips are flip-chip mounted on the second circuit layer and the fourth circuit layer. The at least two chips include a first chip and a second chip. The pins of the first chip and the second chip are respectively connected to a portion of the second circuit layer and a portion of the fourth circuit layer, so that the chip connection bridge serves to connect the first chip and the second chip.

[0015] The high-density interconnect packaging structure and its fabrication method provided in this application have the following beneficial effects:

[0016] Multi-chip interconnection is achieved by using chip bridges embedded in a glass substrate, significantly reducing the overall package size compared to a TSV interposer. First and second via pillars allow for flexible connection of chips to the chip bridges and solder balls, offering high design freedom. The glass material used as the substrate has a thermal expansion coefficient close to that of a silicon wafer, resulting in high reliability for multi-chip packaging. Simultaneously, the glass substrate's ability to form tiny, high-density vias meets the high-density I / O requirements of the chip bridges. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in this application or related technologies, the drawings used in the description of the embodiments or related technologies will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a schematic diagram of the high-density interconnect packaging structure of the chip in an embodiment of this application;

[0019] Figures 2a-2h This is a cross-sectional schematic diagram of the intermediate structures in each step of a method for fabricating a high-density interconnect package structure for a chip according to an embodiment of this application. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with specific embodiments and the accompanying drawings.

[0021] It should be noted that, unless otherwise defined, the technical or scientific terms used in the embodiments of this application should have the ordinary meaning understood by one of ordinary skill in the art to which this application pertains. The terms "first," "second," and similar terms used in the embodiments of this application do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Terms such as "comprising" or "including" mean that the element or object preceding the word encompasses the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Terms such as "connected" or "linked" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. Terms such as "upper," "lower," "left," and "right" are only used to indicate relative positional relationships; when the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0022] Reference Figure 1 This paper illustrates a high-density interconnect packaging structure for chips, including a glass substrate with a thermal expansion coefficient close to that of a silicon wafer. Chip packaging on the substrate can achieve higher reliability. At the same time, the glass substrate has the ability to form high-density fine vias, which can well meet the needs of high-density I / O.

[0023] In one embodiment, the encapsulation structure includes a glass carrier plate, the glass carrier plate including a groove 103 and a glass frame 100 surrounding the groove, a first through-hole post 201 penetrating the glass frame 100, and a second through-hole post 202 penetrating the groove 103.

[0024] The packaging structure also includes a first circuit layer 3011 and a second circuit layer 3021 formed on the upper and lower surfaces of the glass frame 100 and electrically connected through a first through-hole post 201; a third circuit layer 3012 and a fourth circuit layer 3022 formed on the upper and lower surfaces of the recess 103 and electrically connected through a second through-hole post 202; and a fifth circuit layer 702 formed on the first circuit layer 3011. A sixth circuit layer 803 can be formed on the fifth circuit layer 702, and then a solder mask layer can be formed on the sixth circuit layer 803 and solder balls can be formed. Alternatively, a new circuit layer can be formed on the sixth circuit layer 803, and then solder balls can be formed on the new circuit layer. The solder balls allow the packaging structure to be soldered together as a whole. Since multiple circuit layers can be stacked on the fifth circuit layer 702, the design freedom of the packaging structure can be significantly improved.

[0025] A chip bridge 500 is embedded in the third circuit layer 3012 within the recess 103. The chip bridge 500 may have a first pad 501, and the first pad 501 is connected to the third circuit layer 3012. At least two chips 901 may be mounted on the second circuit layer 3021 and the fourth circuit layer 3022. The pins of the at least two chips 901 may be connected to the second circuit layer 3021 and / or the fourth circuit layer 3022, respectively. For example, the pins of the at least two chips 901 may be connected to a portion of the fourth circuit layer 3022 and a portion of the second circuit layer 3021, respectively, so that the chip bridge serves to interconnect the at least two chips 901. It should be noted that this embodiment provides the case of two chips 901 interconnected. In practice, the number of chips can be set as needed to achieve multi-chip interconnection of more than two chips.

[0026] The encapsulation structure includes an encapsulation layer 601 covering the first circuit layer 3011 and the connecting bridge 500, thereby encapsulating and fixing the connecting bridge 500 within the groove 103 of the glass substrate. The encapsulation layer 601 can be made of a thermosetting resin or a photosensitive resin. A fifth circuit layer 702 is provided on the encapsulation layer 601, and the fifth circuit layer 702 can be connected to the first circuit layer 3011 through a first blind via 602 formed by opening a window in the encapsulation layer 601. When the connecting bridge 500 has double-sided pads, for example, when a second pad 502 is located on the opposite side of the first pad 501, the fifth circuit layer 702 can also be connected to the second pad 502 through the first blind via 602.

[0027] In one embodiment, the spacing of the second through-hole post 202 can be configured to be smaller than the spacing of the first through-hole post 201, and the diameter of the second through-hole post 202 can also be configured to be smaller than the diameter of the first through-hole post 201, in order to accommodate the more dense and smaller pads of the connector bridge 500 and meet the high-density wiring requirements of the high-density I / O of the connector bridge 500 for the package structure.

[0028] In one embodiment, the connector bridge 500 includes a first pad 501 and an opposing second pad 502. The first pad 501 is connected to a third circuit layer 3012 via conductive adhesive 401, and the second pad 502 is connected to a fifth circuit layer 702. The double-sided connector bridge 500 can achieve more complex chip interconnect functions. When mounting the connector bridge 500, the conductive adhesive 401 can both fix the connector bridge 500 and provide electrical connection between the first pad 501 and the third circuit layer 3012.

[0029] It should be noted that in practice, the connecting bridge 500 may only have a single-sided first pad 501, without a second pad 502.

[0030] In one embodiment, the second circuit layer 3021 and the fourth circuit layer 3022 are on the same plane; the first circuit layer 3011 and the second pad 502 are on the same plane. The fact that the second circuit layer 3021 and the fourth circuit layer 3022 are on the same plane facilitates the later flip-chip 901; the fact that the first circuit layer 3011 and the second pad 502 are on the same plane facilitates the encapsulation of the connecting bridge 500 and the first circuit layer 3011.

[0031] On the other hand, refer to Figures 2a-2h This diagram shows a cross-sectional view of the intermediate structure of each step in the fabrication method of a high-density interconnect package structure for a chip 901.

[0032] The production method includes the following steps: Figure 2a As shown, a glass substrate is provided, on which a groove 103 and a glass frame 100 surrounding the groove 103 are etched. A first through-hole 101 and a second through-hole 102 are formed along the height direction on the glass frame 100 and the groove 103, respectively. Then, the positions of the predetermined first through-hole 101 and second through-hole 102 can be modified by laser etching to form the first through-hole 101 and the second through-hole 102, respectively. It should be noted that, to meet the high-density wiring requirements of the high-density I / O on the subsequent mounting connector 500, the spacing and diameter of the second through-hole 102 can be smaller than the spacing and diameter of the first through-hole 101.

[0033] Next, as Figure 2b As shown, a first circuit layer 3011, a second circuit layer 3021, a third circuit layer 3012, and a fourth circuit layer 3022 are fabricated. Typically, a first through-hole pillar 201 and a second through-hole pillar 202 are first formed by electroplating within the first and second through-holes. Then, metal seed layers are prepared on the upper and lower surfaces of the glass substrate. A third metal seed layer is covered with photoresist, and photolithography is performed on the photoresist. The first circuit layer 3011, the second circuit layer 3021, the third circuit layer 3012, and the fourth circuit layer 3022 are electroplated at the corresponding positions in the photolithographic areas. Afterward, the photoresist is removed, and the exposed metal seed layers are etched, so that the first circuit layer 3011 and the second circuit layer 3021 are connected through the first through-hole pillar 201, and the third circuit layer 3012 and the fourth circuit layer 3022 are connected through the second through-hole pillar 202.

[0034] Next, conductive adhesive 401 is applied inside the groove 103, such as... Figure 2c As shown, conductive adhesive 401 contains conductive particles 402, and conductive adhesive 401 needs to cover the third circuit layer 3012.

[0035] Next, the connecting bridge 500 is attached to the groove 103 using conductive adhesive 401, as follows: Figure 2dAs shown, the first pad 501 and the third circuit layer 3012 are fixed to each other by conductive adhesive 401 to achieve the connection between the bridge 500 and the third circuit layer 3012. Depending on the actual needs, the bridge 500 can be a thin film circuit layer, a silicon interposer, a glass interposer, or even a chip, as long as it has multi-chip interconnect functionality. The bridge 500 can have only a single-sided pad, such as the first pad 501, or it can have double-sided pads, such as the first pad 501 and the opposing second pad 502 in this embodiment.

[0036] Next, the encapsulation layer 601 is laminated, as follows: Figure 2d As shown. After the encapsulation layer 601 is pressed together, the encapsulation of the first circuit layer 3011 and the connecting bridge 500 is completed. At the same time, during the process of pressing the encapsulation layer 601, the conductive particles 402 in the conductive adhesive 401 are pressed together by the first pad 501 of the connecting bridge 500 and the third circuit layer 3012, realizing the electrical connection between the connecting bridge 500 and the third circuit layer 3012.

[0037] The encapsulation layer 601 can be a thermosetting resin material or a photosensitive resin material. While encapsulating the first circuit layer 3011 and the connecting bridge 500, it also fills and encapsulates the gap between the connecting bridge 500 and the groove 103.

[0038] Next, a window is made in the encapsulation layer 601 to form the first blind via 602, as shown below. Figure 2e As shown, the encapsulation layer 601 can be windowed using laser engraving or exposure and development. The first blind via 602 exposes the first circuit layer 3011 and the second pad 502 of the connecting bridge 500.

[0039] Next, a fifth circuit layer 702 is formed on the encapsulation layer 601, such as... Figure 2f As shown, a first metal seed layer 701 is first prepared on the upper surface of the encapsulation layer 601 and in the first blind via 602. Then, a circuit pattern of the fifth circuit layer 702 is formed on the first metal seed layer 701. After that, the fifth circuit layer 702 is formed by electroplating on the circuit pattern. The exposed first metal seed layer 701 is etched away, and the connection between the fifth circuit layer 702 and the first circuit layer 3011 and the second pad 502 of the connecting bridge 500 is completed.

[0040] Next, an insulating layer 801 is laminated on the fifth circuit layer 702, and a sixth circuit layer 803 is formed on the insulating layer 801, as follows. Figure 2gAs shown. Specifically, an insulating layer 801 can be laminated over the fifth circuit layer 702, and a window can be made in the insulating layer 801 to form a second blind via 802. Then, a second metal seed layer 804 is prepared on the upper surface of the insulating layer 801 and in the second blind via 802. Then, a circuit pattern of a sixth circuit layer 803 is formed on the second metal seed layer 804. Then, the sixth circuit layer 803 is formed by electroplating on the circuit pattern, and the exposed second metal seed layer 804 is etched away, so that the sixth circuit layer 803 is electrically connected to the fifth circuit layer 702.

[0041] It should be noted that, depending on actual needs, additional insulating layers and circuit layers can be stacked and prepared using the aforementioned method to form the required multi-layer packaging structure.

[0042] Next, the 901 chip is installed, such as... Figure 2h As shown. After processing the solder mask layer and performing metal surface treatment on both sides of the above-mentioned package structure to form solder mask windows, solder balls 902 are prepared on the second circuit layer 3021 and the fourth circuit layer 3022 by ball-planting. Then, the chip 901 is flip-chip mounted. The pins of one chip 901 can be connected to a portion of the second circuit layer 3021 and a portion of the fourth circuit layer 3022 through the solder balls 902, and the pins of the other chip 901 can be connected to a portion of the second circuit layer 3021 and a portion of the fourth circuit layer 3022 through the solder balls 902, thereby realizing the interconnection of the two chips 901. Alternatively, multiple chips 901 can be installed as needed, with their respective pins connected to a portion of the second circuit layer 3021 and a portion of the fourth circuit layer 3022 through the solder balls 902, to realize the interconnection between multiple chips 901.

[0043] Finally, solder balls can be placed on the solder mask openings of the sixth circuit layer 803 to form solder balls that connect the package structure to the outside world. This creates an integrated package where multiple chips are interconnected via bridges embedded within the glass substrate. This not only significantly reduces the overall package size but also increases the design freedom of the multi-chip package structure, while simultaneously improving the reliability of the multi-chip package and meeting the high-density I / O requirements of the chip bridges.

[0044] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of this application (including the claims) is limited to these examples; within the framework of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations of different aspects of the embodiments of this application as described above, which are not provided in the details for the sake of brevity.

[0045] Although this application has been described in conjunction with specific embodiments thereof, many substitutions, modifications and variations of these embodiments will be apparent to those skilled in the art from the foregoing description.

[0046] The embodiments of this application are intended to cover all such substitutions, modifications, and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the embodiments of this application should be included within the protection scope of this application.

Claims

1. A high-density interconnect packaging structure for chips, characterized in that, The device includes a glass substrate having a groove and a glass frame surrounding the groove, a first through-hole post penetrating the glass frame, a second through-hole post penetrating the groove, a first and a second circuit layer formed on the upper and lower surfaces of the glass frame and electrically connected via the first through-hole post, a third and a fourth circuit layer formed on the upper and lower surfaces of the groove and electrically connected via the second through-hole post, a chip connection bridge mounted on the third circuit layer within the groove, a fifth circuit layer formed on the first circuit layer, and at least two chips mounted on the second and fourth circuit layers; wherein the chip connection bridge has a first pad connected to the third circuit layer, the pins of the two chips are each connected to the fourth circuit layer and / or the second circuit layer, and the fifth circuit layer is connected to the first circuit layer; the spacing between the first through-hole posts is greater than the spacing between the second through-hole posts, and the diameter of the second through-hole posts is smaller than the diameter of the first through-hole posts.

2. The high-density interconnect packaging structure for chips according to claim 1, characterized in that, The chip bridge also has a second pad on the surface opposite to the first pad, wherein the second pad is connected to the fifth circuit layer.

3. The high-density interconnect packaging structure for chips according to claim 1, characterized in that, It also includes an encapsulation layer that covers the first line layer and the connecting bridge.

4. The high-density interconnect packaging structure for chips according to claim 1, characterized in that, It also includes an insulating layer on the fifth circuit layer and a sixth circuit layer on the insulating layer.

5. The high-density interconnect packaging structure for chips according to claim 1, characterized in that, The first pad of the connecting bridge is connected to the third circuit layer via conductive adhesive.

6. The high-density interconnect packaging structure for chips according to claim 2, characterized in that, The second circuit layer and the fourth circuit layer are on the same plane; the first circuit layer and the second pad are on the same plane.

7. The high-density interconnect packaging structure for chips according to claim 1, characterized in that, The at least two chips include a first chip and a second chip, wherein the pins of the first chip and the second chip are respectively connected to a portion of the second circuit layer and a portion of the fourth circuit layer, such that the chip connection bridge serves to connect the first chip and the second chip.

8. A method for fabricating a high-density interconnect packaging structure for a chip, characterized in that, include: A glass substrate is partially etched to form a groove and a glass frame surrounding the groove, and a first through hole and a second through hole are formed in the glass frame and the groove along the height direction; The glass carrier plate is metallized, a first circuit layer and a second circuit layer are formed on the upper and lower surfaces of the glass frame, a third circuit layer and a fourth circuit layer are formed on the upper and lower surfaces of the groove, and the first through hole is filled to form a first through hole post, and the second through hole is filled to form a second through hole post, such that the first through hole post is conductively connected to the first circuit layer and the second circuit layer, and the second through hole post is conductively connected to the third circuit layer and the fourth circuit layer. A chip connection bridge is mounted in the groove, such that the first pad of the chip connection bridge is connected to the third circuit layer; A lamination encapsulation layer is applied so that the encapsulation layer covers the first circuit layer and the chip connection bridge; A fifth circuit layer is formed on the encapsulation layer, such that the first circuit layer is connected to the fifth circuit layer; An insulating layer is formed on the fifth circuit layer, and a sixth circuit layer is formed on the insulating layer, such that the fifth circuit layer and the sixth circuit layer are connected. At least two chips are flip-chip mounted on the second circuit layer and the fourth circuit layer. The at least two chips include a first chip and a second chip. The pins of the first chip and the second chip are respectively connected to a portion of the second circuit layer and a portion of the fourth circuit layer, so that the chip connection bridge serves to connect the first chip and the second chip. The spacing between the first through-hole posts is greater than the spacing between the second through-hole posts, and the diameter of the second through-hole posts is smaller than the diameter of the first through-hole posts.

9. The method according to claim 8, characterized in that, The first pad of the chip connection bridge is connected and fixed to the third circuit layer by conductive adhesive.

10. The method according to claim 8, characterized in that, The chip bridge also has a second pad on the surface opposite to the first pad, wherein the second pad is connected to the fifth circuit layer.

11. The method according to claim 8, characterized in that, It also includes placing solder balls on the sixth circuit layer to form solder balls that conduct the at least two chips.

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