Array substrate with reduced parasitic capacitance and manufacturing method thereof

Abstract

The application relates to the technical field of display, and provides an array substrate capable of reducing the influence of a parasitic capacitor couple and a manufacturing method thereof.The array substrate comprises a glass substrate, a first metal layer, a gate, a first CK signal wire and a third CK signal wire which are distributed at intervals, a gate insulation layer plated on the upper surface of the glass substrate and the first metal layer, a pixel electrode, a first electrode block, a second electrode block, a third electrode block, an active layer, a second metal layer, a source, a drain and a first signal connecting wire which are distributed at intervals, a passivation layer plated on the upper surface of the gate insulation layer, the active layer, the second metal layer and the pixel electrode, a conductive layer plated on the upper surface of the passivation layer, and a light shielding metal layer plated on the upper surface of the passivation layer.The application has the advantages that the potential of the conductive layer is opposite to the potential of the gate, the coupling effect of the gate on the drain and the coupling effect of the conductive layer on the drain are counteracted, the influence of the parasitic capacitor couple is reduced, and the Feedthrough voltage is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of display technology, in particular to an array substrate for reducing the influence of parasitic capacitance couple and a manufacturing method thereof. BACKGROUND

[0002] For TFT-LCD display, the side of TFT connected with pixel electrode is called drain, and the capacitance formed between drain and gate metal is called parasitic capacitance C gd . The gate of TFT device is connected with horizontally distributed gate line, for controlling the opening and closing of TFT device; the source of TFT device is connected with vertically distributed data line, for writing data voltage which is wanted to be displayed into TFT device; when TFT is opened, the source and drain are conducted, and data voltage enters into drain and then reaches liquid crystal capacitor Cst through pixel electrode, for adjusting the light transmittance of liquid crystal; when TFT is closed, the source and drain are cut off, and data voltage of source cannot enter into drain. The data voltage of source is periodically positive and negative, which is the positive and negative deflection voltage of liquid crystal.

[0003] In combination Figure 1 With Figure 2 , at the moment when TFT is closed, the gate voltage V g instantaneously drops from high level V high to low level V low . Due to the existence of parasitic capacitance C gd , the instantaneous change of V g will be coupled to drain, and due to the influence of parasitic capacitance couple, the voltage of drain drops, and because TFT device has been closed at this moment, the voltage difference between pixel electrode and drain will cause the voltage of pixel electrode to jump, and this jump ΔV is called Feedthrough voltage. In the waveform diagram of V Figure 2 , V g is gate voltage, V d is ideal drain voltage, is actual common electrode voltage, i.e. the center point of actual positive and negative deflection voltage, V p (t) is actual pixel electrode voltage, V com is ideal common electrode voltage which makes liquid crystal keep the same voltage at both ends in positive and negative polarity state, V offset is the deviation of ideal common electrode voltage from actual common electrode voltage, T f is the switching period of TFT device, V lc > V com is the region where pixel electrode voltage is greater than current ideal common electrode voltage, V lc < V comis a region where the pixel electrode voltage is less than the common electrode voltage in the ideal state.

[0004] As shown in Figure 2 Due to the existence of the Feedthrough voltage, the ideal state of the common electrode V com deviates from the center position of the actual provided positive and negative polarity deflection voltage, that is, the ideal state of the common electrode voltage changes, but the actual provided positive and negative polarity deflection voltage remains unchanged, which results in that the liquid crystal has different deflection angles in the positive and negative polarity states, and thus the light transmittance of the array substrate is different, causing flicker of the picture of the liquid crystal display. Therefore, reducing the Feedthrough voltage is a problem to be solved at present. SUMMARY

[0005] The technical problem to be solved by the present application is to provide an array substrate with reduced influence of parasitic capacitance couple and a manufacturing method thereof. By arranging a conductive layer above the drain electrode, the potential of the conductive layer is opposite to the potential of the gate electrode, the coupling effect of the gate electrode on the drain electrode and the coupling effect of the conductive layer on the drain electrode are mutually offset, the influence of the parasitic capacitance couple is reduced, and thus the Feedthrough voltage is reduced.

[0006] The present application is implemented as follows:

[0007] An array substrate with reduced influence of parasitic capacitance couple comprises:

[0008] a glass substrate;

[0009] a first metal layer plated on the upper surface of the glass substrate, forming spaced gate electrodes, first CK signal wires and third CK signal wires, the potential of the first CK signal wires being opposite to the potential of the third CK signal wires;

[0010] a gate insulating layer plated on the upper surface of the glass substrate and the first metal layer, the gate insulating layer being provided with first, second and third holes, the gate electrodes being exposed from the first holes, the first CK signal wires being exposed from the second holes, and the third CK signal wires being exposed from the third holes;

[0011] a pixel electrode plated on the upper surface of the gate insulating layer and located laterally to the gate electrodes;

[0012] a first electrode block plated in the first holes and connected to the gate electrodes;

[0013] a second electrode block plated in the second holes and connected to the first CK signal wires;

[0014] A third electrode block plated on the third hole and connected with the third CK signal wire;

[0015] The first electrode block, the second electrode block and the third electrode block are made of the same material as the pixel electrode.

[0016] An active layer plated on the upper surface of the gate insulation layer and located right above the gate electrode;

[0017] A second metal layer plated on the upper surface of the gate insulation layer and forming the source electrode, the drain electrode and the first signal connection wire, the source electrode connected with the left end of the active layer, the drain electrode connected with the right end of the active layer, the drain electrode connected with the pixel electrode, the right end of the first signal connection wire connected with the first electrode block, and the left end of the first signal connection wire connected with the second electrode block;

[0018] A passivation layer plated on the upper surfaces of the gate insulation layer, the active layer, the second metal layer and the pixel electrode, the passivation layer having a fourth hole, and the third electrode block exposed from the fourth hole;

[0019] A conductive layer plated on the upper surface of the passivation layer and located right above the drain electrode, the upper surface of the passivation layer further plated with a second signal connection wire, the conductive layer connected with the right end of the second signal connection wire, and the left end of the second signal connection wire connected with the third electrode block through the fourth hole;

[0020] A light-shielding metal layer plated on the upper surface of the passivation layer and located right above the channel of the active layer, the light-shielding metal layer spaced apart from the conductive layer and the second signal connection wire;

[0021] The light-shielding metal layer, the conductive layer and the second signal connection wire are made of the same material as the first metal layer.

[0022] Further, the display panel further comprises:

[0023] The second metal layer further forms the TP wire;

[0024] An outer insulation layer plated on the upper surfaces of the conductive layer, the light-shielding metal layer and the passivation layer, the outer insulation layer having a fifth hole penetrating the passivation layer, and the TP wire exposed from the fifth hole;

[0025] A common electrode plated on the upper surface of the outer insulation layer and connected with the TP wire through the fifth hole.

[0026] Further, the first metal layer, the second metal layer, the conductive layer, the second signal connection wire and the light-shielding metal layer are either a Ti / AL / Ti three-layer structure or a MO / AL / MO three-layer structure.

[0027] Further, the gate insulating layer is a single-layer structure of SiOx or a double-layer structure of SiNx / SiOx, the passivation layer is SiO2, and the outer insulating layer is SiOx, SiNO or SiNx.

[0028] Further, the active layer is IGZO, and the pixel electrode, the first electrode block, the second electrode block, the third electrode block and the common electrode are all ITO.

[0029] Further, the first metal layer further forms a second CK signal line and a fourth CK signal line which are distributed at intervals, and the second CK signal line has a potential which is opposite to that of the fourth CK signal line.

[0030] The first CK signal line is connected with the gate of the array substrate of the first row, the second CK signal line is connected with the gate of the array substrate of the second row, the third CK signal line is connected with the conductive layer of the array substrate of the first row, and the fourth CK signal line is connected with the conductive layer of the array substrate of the second row.

[0031] Further, the signal timing phase of the first CK signal line is earlier than that of the second CK signal line by a quarter of a period, and the signal timing phase of the third CK signal line is earlier than that of the fourth CK signal line by a quarter of a period.

[0032] A manufacturing method of an array substrate for reducing the influence of a parasitic capacitance couple, comprising the following steps:

[0033] S1, plating a first metal layer on the upper surface of a glass substrate to form a gate, a first CK signal line and a third CK signal line which are distributed at intervals, and the first CK signal line has a potential which is opposite to that of the third CK signal line;

[0034] S2, plating a gate insulating layer on the upper surface of the glass substrate and the first metal layer;

[0035] S3, opening a first hole, a second hole and a third hole in the gate insulating layer, the gate is exposed to the first hole, the first CK signal line is exposed to the second hole, and the third CK signal line is exposed to the third hole;

[0036] S4, plating a pixel electrode on the upper surface of the gate insulating layer, and the pixel electrode is also located at the side of the gate;

[0037] The first electrode block, the second electrode block and the third electrode block are plated in the first hole, the second hole and the third hole respectively, the first electrode block is connected with the gate electrode, the second electrode block is connected with the first CK signal wire, and the third electrode block is connected with the third CK signal wire;

[0038] The first electrode block, the second electrode block and the third electrode block are made of the same material as the pixel electrode;

[0039] S5, the active layer is plated on the upper surface of the gate insulating layer, and the active layer is located directly above the gate electrode;

[0040] S6, a second metal layer is plated on the upper surface of the gate insulating layer to form a source electrode, a drain electrode and a first signal connection wire which are distributed at intervals, the source electrode is connected with the left end of the active layer, the drain electrode is connected with the right end of the active layer, the drain electrode is also connected with the pixel electrode, the right end of the first signal connection wire is connected with the first electrode block, and the left end of the first signal connection wire is connected with the second electrode block;

[0041] S7, a passivation layer is plated on the upper surfaces of the gate insulating layer, the active layer, the second metal layer and the pixel electrode;

[0042] A fourth hole is formed in the passivation layer, and the third electrode block is exposed in the fourth hole;

[0043] S8, a conductive layer, a second signal connection wire and a light shielding metal layer are plated on the upper surface of the passivation layer, the conductive layer is also located directly above the drain electrode, the conductive layer is connected with the right end of the second signal connection wire, the left end of the second signal connection wire passes through the fourth hole and is connected with the third electrode block, the light shielding metal layer is also located directly above the channel of the active layer, and the light shielding metal layer is arranged at intervals with the conductive layer and the second signal connection wire;

[0044] The light shielding metal layer and the conductive layer are made of the same material as the first metal layer.

[0045] Further, it further comprises:

[0046] In the S6, the second metal layer also forms a TP wire which is distributed at intervals;

[0047] S9, an outer insulating layer is plated on the upper surfaces of the conductive layer, the light shielding metal layer and the passivation layer, a fifth hole is formed in the outer insulating layer, the fifth hole penetrates the passivation layer, and the TP wire is exposed in the fifth hole;

[0048] S10, a common electrode is plated on the upper surface of the outer insulating layer, and a lead wire of the common electrode passes through the fifth hole and is connected with the TP wire.

[0049] Further, the first metal layer, the second metal layer, the conductive layer, the second signal connecting line and the light shielding metal layer are all in a Ti / AL / Ti three-layer structure or a MO / AL / MO three-layer structure.

[0050] The present application has the following advantages: 1. The conductive layer is arranged above the drain electrode, a supplementary capacitor is formed between the conductive layer and the drain electrode, the signal of the gate electrode is provided by the first CK signal line, the signal of the conductive layer is provided by the third CK signal line, the potential of the conductive layer is opposite to that of the gate electrode, the coupling effect of the gate electrode on the drain electrode and the coupling effect of the conductive layer on the drain electrode are counteracted, the voltage difference between the pixel electrode and the drain electrode is reduced, the influence of the parasitic capacitor couple is reduced, the Feedthrough voltage is reduced, the picture flicker of the liquid crystal display is reduced, the Feedthrough voltage is eliminated when the size of the supplementary capacitor is equal to that of the parasitic capacitor, and the picture display stability of the liquid crystal display is improved; 2. The conductive layer is arranged at a position close to the contact between the drain electrode and the active layer, the field intensity at the position is larger, the Schottky barrier formed by the contact between the semiconductor of the active layer and the metal wire of the drain electrode can be reduced, the contact resistance can be reduced, and the on-state current is increased; 3. ITO has good conductivity and light transmittance, the pixel electrode, the first electrode block, the second electrode block and the third electrode block are all made of ITO, the pixel electrode, the first electrode block, the second electrode block and the third electrode block can be formed in the same process, the substrate structure is simplified, and the production capacity is improved; 4. The first hole, the second hole and the third hole are pre-formed in the gate insulating layer, and then the first electrode block, the second electrode block and the third electrode block are filled respectively, and the influence of the subsequent etching process on the metal of the first metal layer is avoided; 5. The conductive layer does not cover the channel of the active layer, but the light shielding metal layer is plated on the channel of the active layer, the light shielding effect is achieved, and the stability of the TFT device is improved. BRIEF DESCRIPTION OF DRAWINGS

[0051] The present application will be further described below with reference to the embodiments and the accompanying drawings.

[0052] Figure 1 is a schematic diagram of the parasitic capacitor between the gate electrode and the drain electrode of the TFT device in the background technology.

[0053] Figure 2 is a schematic diagram of the deviation of the ideal state of the common electrode V com from the point position due to the existence of the Feedthrough voltage in the background technology.

[0054] Figure 3 is a design diagram of the array substrate for reducing the influence of the parasitic capacitor couple according to the present application.

[0055] Figure 4 isFigure 3 Circuit schematic diagram of the first row of TFT devices of the array substrate.

[0056] Figure 5 Figure 3 Circuit schematic diagram of the second row of TFT devices of the array substrate.

[0057] Figure 6 Timing diagram of the first, second, third and fourth CK signal lines of the present application.

[0058] Figure 7 Top view schematic diagram of the array substrate of the present application for reducing the effect of the parasitic capacitance couple.

[0059] Figure 8 Manufacturing process of the array substrate of the present application for reducing the effect of the parasitic capacitance couple Figure 1 .

[0060] Figure 9 Manufacturing process of the array substrate of the present application for reducing the effect of the parasitic capacitance couple Figure 2 .

[0061] Figure 10 Manufacturing process of the array substrate of the present application for reducing the effect of the parasitic capacitance couple Figure 3 .

[0062] Figure 11 Manufacturing process of the array substrate of the present application for reducing the effect of the parasitic capacitance couple Figure 4 .

[0063] Figure 12 Manufacturing process of the array substrate of the present application for reducing the effect of the parasitic capacitance couple Figure 5 .

[0064] Figure 13 Manufacturing process of the array substrate of the present application for reducing the effect of the parasitic capacitance couple Figure 6 .

[0065] Figure 14 Manufacturing process of the array substrate of the present application for reducing the effect of the parasitic capacitance couple Figure 7 .

[0066] Figure 15 Manufacturing process of the array substrate of the present application for reducing the effect of the parasitic capacitance couple Figure 8 .

[0067] Figure 16 Manufacturing process of the array substrate of the present application for reducing the effect of the parasitic capacitance couple Figure 9 .​

[0068] Figure 17 Fabrication process of array substrate with reduced influence of parasitic capacitance couple Figure 10 .

[0069] Reference signs:

[0070] Glass substrate 1; pixel display area 11;

[0071] Gate 2;

[0072] First CK signal wire 31; second CK signal wire 32; third CK signal wire 33; fourth CK signal wire 34;

[0073] Gate insulation layer 4; first hole 41; second hole 42; third hole 43;

[0074] Pixel electrode 5; first electrode block 51; second electrode block 52; third electrode block 53;

[0075] Active layer 6;

[0076] Source 7;

[0077] Drain 8;

[0078] First signal connection line 91; right end 911 of first signal connection line; left end 912 of first signal connection line; second signal connection line 92;

[0079] Passivation layer 10; fourth hole 101;

[0080] Conductive layer 20;

[0081] Light shielding metal layer 30;

[0082] TP wire 40;

[0083] Outer insulation layer 50; fifth hole 501;

[0084] Common electrode 60. DETAILED DESCRIPTION

[0085] The embodiment of the present application provides an array substrate with reduced influence of parasitic capacitance couple and a fabrication method thereof, solves the problem of flickering of liquid crystal display picture caused by the existence of Feedthrough voltage due to the influence of parasitic capacitance couple in the background art, and realizes the technical effect of reducing the influence of parasitic capacitance couple and Feedthrough voltage and stable liquid crystal display picture.

[0086] The technical solution in the embodiment of the present application is as follows to solve the above-mentioned problem:

[0087] The main improvement of the present application is that after the passivation layer is plated, a conductive layer is plated above the drain electrode, and the conductive layer and the drain electrode form a complementary capacitor C 补充 Then the potential of the conductive layer is always opposite to the potential of the gate of the TFT array substrate at any time. There is a parasitic capacitor C gd between the drain electrode and the gate electrode. Thus the coupling effect of the gate electrode on the drain electrode and the coupling effect of the conductive layer on the drain electrode are counteracted, i.e. the Feedthrough voltage caused by the voltage difference between the pixel electrode and the drain electrode is reduced, the voltage jump of the pixel electrode is reduced, and the Feedthrough voltage is reduced. The signal of the gate electrode is provided by the first CK signal line, and the signal of the conductive layer is provided by the third CK signal line. When the complementary capacitor C 补充 is equal to the parasitic capacitor C gd , the Feedthrough voltage caused by the signal change of the gate electrode can be eliminated. The complementary capacitor C 补充 can be equal to the parasitic capacitor C gd by adjusting the area directly above the conductive layer and the drain electrode and the distance of the film layer.

[0088] The conductive layer does not cover the channel of the active layer, but a floating light shielding metal layer is plated above the channel of the active layer. The floating light shielding metal layer is spaced around the light shielding metal layer and does not contact the surrounding conductive layer and the second signal connection line. The light shielding metal layer plays a light shielding role and improves the stability of the TFT device.

[0089] In order to better understand the above technical solutions, the above technical solutions will be described in detail below in combination with the drawings in the specification and specific embodiments.

[0090] Reference is made to Figures 1 to 17 the preferred embodiments of the present application.

[0091] An array substrate for reducing the parasitic capacitor couple effect, comprising:

[0092] a glass substrate 1;

[0093] a first metal layer plated on the upper surface of the glass substrate 1, forming spaced gate electrodes 2, a first CK signal line 31 and a third CK signal line 33, the potential of the first CK signal line 31 being opposite to the potential of the third CK signal line 33;

[0094] A gate insulating layer 4 is plated on the upper surface of the glass substrate 1 and the first metal layer, and the gate insulating layer 4 is provided with a first hole 41, a second hole 42 and a third hole 43, the gate 2 is exposed from the first hole 41, the first CK signal wire 31 is exposed from the second hole 42, and the third CK signal wire 33 is exposed from the third hole 43;

[0095] A pixel electrode 5 is plated on the upper surface of the gate insulating layer 4 and is located beside the gate 2;

[0096] A first electrode block 51 is plated on the first hole 41 and is connected with the gate 2;

[0097] A second electrode block 52 is plated on the second hole 42 and is connected with the first CK signal wire 31;

[0098] A third electrode block 53 is plated on the third hole 43 and is connected with the third CK signal wire 33;

[0099] The first electrode block 51, the second electrode block 52 and the third electrode block 53 are made of the same material as the pixel electrode 5;

[0100] An active layer 6 is plated on the upper surface of the gate insulating layer 4 and is located directly above the gate 2;

[0101] A second metal layer is plated on the upper surface of the gate insulating layer 4 and forms a source electrode 7, a drain electrode 8 and a first signal connecting wire 91 which are distributed at intervals, the source electrode 7 is connected with the left end of the active layer 6, the drain electrode 8 is connected with the right end of the active layer 6, the drain electrode 8 is also connected with the pixel electrode 5, the right end 911 of the first signal connecting wire is connected with the first electrode block 51, and the left end 912 of the first signal connecting wire is connected with the second electrode block 52;

[0102] A passivation layer 10 is plated on the upper surface of the gate insulating layer 4, the active layer 6, the second metal layer and the pixel electrode 5, and the passivation layer 10 is provided with a fourth hole 101, and the third electrode block 53 is exposed from the fourth hole 101;

[0103] A conductive layer 20 is plated on the upper surface of the passivation layer 10 and is located directly above the drain electrode 8, and the upper surface of the passivation layer 10 is also plated with a second signal connecting wire 92, the conductive layer 20 is connected with the right end of the second signal connecting wire 92, and the left end of the second signal connecting wire 92 is connected with the third electrode block 53 through the fourth hole 101;

[0104] A light shielding metal layer 30 is plated on the upper surface of the passivation layer 10 and is located directly above the channel of the active layer 6, and the light shielding metal layer 30 is spaced apart from the conductive layer 20 and the second signal connection line 92.

[0105] The light shielding metal layer 30 and the conductive layer 20 are made of the same material as the first metal layer.

[0106] In the present application, the conductive layer 20 is arranged above the drain 8, a supplementary capacitor is formed between the conductive layer 20 and the drain 8, the signal of the gate 2 is provided by the first CK signal line 31, the signal of the conductive layer 20 is provided by the third CK signal line 33, the potential of the conductive layer 20 is opposite to the potential of the gate 2, the coupling effect of the gate 2 on the drain 8 and the coupling effect of the conductive layer 20 on the drain 8 are offset to each other, the parasitic capacitor couple is reduced, the voltage difference between the pixel electrode 5 and the drain 8 is reduced, the Feedthrough voltage is reduced, the picture flicker of the liquid crystal display is reduced, when the size of the supplementary capacitor is equal to the size of the parasitic capacitor, the Feedthrough voltage is eliminated, the picture display stability of the liquid crystal display is improved, and the V com The center position of the positive and negative polarity deflection voltage provided actually deviates from the ideal center position, the liquid crystal maintains the same voltage value at both ends in the positive and negative polarity state, the deflection angle of the liquid crystal in the positive and negative polarity state is the same, the light transmittance of the array substrate is the same, and the picture of the liquid crystal display is stable.

[0107] The conductive layer 20 is arranged at a position close to the contact between the drain 8 and the active layer 6, and the field strength at the position is larger, so that the Schottky barrier formed by the contact between the semiconductor of the active layer 6 and the metal wire of the drain 8 can be reduced, the contact resistance can be reduced, and the on-state current can be increased.

[0108] The first, second and third electrode blocks 51, 52 and 53 are filled in the first, second and third holes 41, 42 and 43 of the gate insulating layer 4 in advance, and then the first metal layer is etched in the subsequent process, so that the first, second and third electrode blocks 51, 52 and 53 are not affected. The first, second and third electrode blocks 51, 52 and 53 are made of the same material as the pixel electrode 5, so that the pixel electrode 5, the first, second and third electrode blocks 51, 52 and 53 can be formed in the same process, the substrate structure is simplified, the production capacity is improved, and the cost is reduced. When the passivation layer 10 is etched to form the fourth hole 101, the etching is stopped when the third electrode block 53 is exposed in the fourth hole 101, so that the third CK signal line 33 is not etched, and the outermost metal of the third CK signal line 33 in the first metal layer is not damaged.

[0109] The conductive layer 20 does not cover the channel of the active layer 6, but a floating light shielding metal layer 30 is plated on the channel of the active layer 6, the floating light shielding metal layer is spaced around the light shielding metal layer, and the light shielding metal layer 30 plays a role of light shielding and improves the stability of the TFT device.

[0110] Further comprising: the second metal layer also forms the TP trace 40 which is spaced;

[0111] An outer insulating layer 50 is plated on the upper surface of the conductive layer 20, the light shielding metal layer 30 and the passivation layer 10, the outer insulating layer 50 is provided with a fifth hole 501, the fifth hole 501 penetrates the passivation layer 10, and the TP trace 40 is exposed to the fifth hole 501;

[0112] A common electrode 60 is plated on the upper surface of the outer insulating layer 50, and the common electrode 60 is connected with the TP trace 40 through the fifth hole 501. One end of the liquid crystal Cst of the liquid crystal display is connected with the pixel electrode 5, and the other end is connected with the common electrode 60. The full name of the TP trace is Touch Panel Senser Line; the TP trace provides a voltage signal for the common electrode.

[0113] The first metal layer, the second metal layer, the conductive layer 20, the second signal connecting line 92 and the light shielding metal layer 30 are all Ti / AL / Ti three-layer structures or MO / AL / MO three-layer structures.

[0114] The gate insulating layer 4 is a single-layer structure of SiOx or a double-layer structure of SiNx / SiOx, the passivation layer 10 is SiO2, and the outer insulating layer 50 is SiOx or SiNO or SiNx.

[0115] The active layer 6 is IGZO, and the pixel electrode 5, the first electrode block 51, the second electrode block 52, the third electrode block 53 and the common electrode 60 are all ITO. ITO has good conductivity and light transmittance, and the pixel electrode 5, the first electrode block 51, the second electrode block 52 and the third electrode block 53 are all made of ITO, so the pixel electrode 5, the first electrode block 51, the second electrode block 52 and the third electrode block 53 can be formed in the same process, which can simplify the substrate structure and improve the production capacity.

[0116] The first metal layer also forms the second CK signal trace 32 and the fourth CK signal trace 34 which are spaced, and the potential of the second CK signal trace 32 is opposite to that of the fourth CK signal trace 34;

[0117] The first CK signal wire (CK1) is connected with the gate of the array substrate of the first row, the second CK signal wire (CK2) is connected with the gate of the array substrate of the second row, the third CK signal wire (CK3) is connected with the conductive layer of the array substrate of the third row, and the fourth CK signal wire (CK4) is connected with the conductive layer of the array substrate of the fourth row.

[0118] For the first row of the array substrate, the first hole 41 is opened at the position of the first row gate 2, the second hole 42 is opened at the position of the first CK signal wire 31, and the third hole 43 is opened at the position of the third CK signal wire 33, and the first row of the array substrate has the first signal connection line 91 and the second signal connection line 92; for the second row of the array substrate, the first hole 41 is opened at the position of the second row gate 2, the second hole 42 is opened at the position of the second CK signal wire 32, and the third hole 43 is opened at the position of the fourth CK signal wire 34, and the second row of the array substrate also has the first signal connection line 91 and the second signal connection line 92.

[0119] The signal timing phase of the first CK signal wire 31 is earlier than that of the second CK signal wire 32 by one quarter of a period, and the signal timing phase of the third CK signal wire 33 is earlier than that of the fourth CK signal wire 34 by one quarter of a period. When the first CK signal wire 31 drives the gate 2 of the first row TFT device to be high, the source 7 and the drain 8 of the first row TFT device are turned on, and the data voltage signal is written to the pixel electrode 5, and after one quarter of a period of time, the second CK signal wire 32 drives the gate 2 of the second row TFT device to be high, the source 7 and the drain 8 of the second row TFT device are turned on, and the data voltage signal is written to the pixel electrode 5. When the first CK signal wire 31 is high, the third CK signal wire 33 is low, and when the first CK signal wire 31 is low, the third CK signal wire 33 is high; similarly, the high and low potentials of the second CK signal wire 32 and the fourth CK signal wire 34 are opposite. Under the control of the first CK signal wire 31, the second CK signal wire 32, the third CK signal wire 33 and the fourth CK signal wire 34, the array substrate makes the display screen be sequentially lit from top to bottom or from bottom to top by one row of pixels. For example, when the first CK signal wire is 10V, the third CK signal wire is -15V; when the first CK signal wire is -15V, the third CK signal wire is 10V.

[0120] Also included is a driving IC connected to the first CK signal wire 31, the second CK signal wire 32, the third CK signal wire 33, and the fourth CK signal wire 34. The driving IC is used to give the first CK signal wire 31, the second CK signal wire 32, the third CK signal wire 33, and the fourth CK signal wire 34 different timing signals.

[0121] The working principle of the array substrate of the present application for reducing the influence of the parasitic capacitance couple:

[0122] The present embodiment is described by taking a single-side level transmission 4CK design as an example (note that the circuit design of the present application is not limited to single-side level transmission 4CK, but can also be double-side level transmission). The timing diagram is shown in Figure 5 Figure 4 is Figure 3 The circuit diagram of all pixels in the first row is shown inBriefly, the display of the picture is realized by sequentially lighting the pixels row by row from top to bottom or from bottom to top. The lighting of the pixels requires that the gate 2 of the TFT device corresponding to the pixels in the row is at a high potential, then the TFT device is turned on, and the data signal can be written into the pixel electrode 5, thereby controlling the twist of the liquid crystal and lighting the pixel. Taking the display of the pixels in the first row as an example, when the first CK signal wire 31 is at a high potential and the third CK signal wire 33 is at a low potential, the high potential of the first CK signal wire 31 is transmitted to the gate 2 of the first row, the TFT device of the first row is turned on, the signal of the pixel electrode 5 is written in, and the low potential of the third CK signal wire 33 is transmitted to the conductive layer 20 of the first row; when the first CK signal wire 31 is switched to a low potential, the third CK signal wire 33 is switched to a high potential, the gate 2 is switched from a high potential to a low potential, and the parasitic capacitance formed by the gate 2 and the drain 8 will have a coupling effect, thereby pulling down the voltage of the drain 8. However, since the third CK signal wire 33 is switched from a low potential to a high potential at this time, i.e., the conductive layer 20 of the first row is switched from a low potential to a high potential, the complementary capacitance formed by the conductive layer 20 and the drain 8 will also have a coupling effect, thereby pulling up the voltage of the drain, so the voltage of the drain will not change due to the jump of the gate, that is, the voltage of the pixel electrode will not change. Note that the design requires that the size of the C complementary and the Cgd be equal. The purpose of this design is to make the drain 8 have two Feedthrough voltages with equal size and opposite signs. In this way, the TFT device of each row can avoid the Feedthrough voltage caused by the jump of the gate 2.

[0123] Microcosmic level, actually is the charge migration between the drain 8 and the pixel electrode 5, cause the pixel electrode 5 on the storage charge amount change and cause the voltage change. Pixel electrode 5 after charging, the drain 8 and the pixel electrode 5 between the potential size is equal, they will not happen between the electron migration, but due to the gate 2 voltage will have a high potential switching for low potential moment, the amount of change will be coupled through the parasitic capacitance formed by the gate 2 and the drain 8 to the drain 8, the drain 8 and the pixel electrode 5 between will produce voltage difference, cause the charge migration between the drain 8 and the pixel electrode 5, thus causing the pixel electrode 5 change. The starting point of the invention to solve this problem is to add a conductive layer 20, the conductive layer 20 and the drain 8 form a complementary capacitor C complementary, then through the first CK signal line 31 and the third CK signal line 33 respectively give the gate 2 and the conductive layer 20 opposite potential signal, offset the coupling effect of parasitic capacitance and complementary capacitor, also improve the working performance of the device.

[0124] A manufacturing method of array substrate for reducing the influence of parasitic capacitance couple, comprising the following steps:

[0125] S1, refer to Figure 8 The first metal layer is plated on the upper surface of the glass substrate 1 to form the gate 2, the first CK signal line 31, the second CK signal line 32, the third CK signal line 33 and the fourth CK signal line 34, the potential of the first CK signal line is opposite to the potential of the third CK signal line, the potential of the second CK signal line 32 is opposite to the potential of the fourth CK signal line 34;

[0126] The gate 2 is used for turning on and off the TFT device, the first CK signal line 311 is used for transmitting the first row gate 2 signal, the second CK signal line 32 is used for transmitting the second row gate signal, the third CK signal line 33 is used for transmitting the first row conductive layer 20 signal, and the fourth CK signal line 34 is used for transmitting the second row conductive layer signal; the material of the first metal layer can be selected from MO / AL / MO stack, Ti / AL / Ti stack, AL / MO stack (MO as the top layer), AL / Ti stack (Ti as the top layer) and the like, and PVD film forming. AL has small resistance and is used for conduction (which can be replaced by Cu), which can reduce impedance and reduce power consumption; secondly, the expansion coefficients of MO or Ti are small, which can inhibit the deformation of AL in high temperature process and can prevent oxidation of AL.

[0127] S2, refer to Figure 9 The gate insulating layer 4 is plated on the upper surface of the glass substrate 1 and the first metal layer;

[0128] The gate 2 insulating layer functions as an insulating medium and a capacitive medium between the gate 2 and the active layer 6, and is made of a single layer of SiOx or a double layer of SiNx / SiOx, which is formed by CVD. Considering the current requirements for TFT devices, i.e. fast response and low power consumption, which are achieved by reducing the size of the TFT device, the gate insulating layer 4 needs to be made of a suitable high-K material (such as HfO2) to achieve the miniaturization of the device. However, considering the defects in the interface of HfO2, the stability of the device may be affected if the HfO2 is directly in contact with the active layer 6 or the gate 2 metal. Therefore, a contact surface made of SiOx or SiNx (SiNx can only be used as a contact film layer for the gate metal layer, and if used as a contact surface for IGZO, the H remaining in the SiNx film layer during the film formation process will damage the properties of IGZO) can be considered, such as a three-layer structure of SiOx / HfO2 / SiOx as the GI insulating layer. In order to ensure the advantages of high-K materials, the thickness of HfO2 in the three-layer structure needs to be relatively larger than that of SiOx.

[0129] S3、refer to Figure 10 The first hole 41, the second hole 42 and the third hole 43 are formed in the gate insulating layer 4, the gate 2 is exposed in the first hole 41, the first CK signal line 31 is exposed in the second hole 42, and the third CK signal line 33 is exposed in the third hole 43.

[0130] For the first row of the array substrate, the first hole is formed at the position of the first row of gates, the second hole 42 is formed at the position of the first CK signal line 31, and the third hole 43 is formed at the position of the third CK signal line 33. For the second row of the array substrate, the first hole is formed at the position of the second row of gates, the second hole 42 is formed at the position of the second CK signal line 32, and the third hole 43 is formed at the position of the fourth CK signal line 34. The first hole 41, the second hole 42 and the third hole 43 are outside the pixel display area 11.

[0131] The first hole 41, the second hole 42 and the third hole 43 are formed by dry etching. The first hole 41 and the second hole 42 provide the connection between the first CK signal line 31 (or the second CK signal line 32), the first signal connection line 91 and the gate 2. The third hole 43 provides the connection between the third CK signal line 33 (or the fourth CK signal line 34) and the second signal connection line 92.

[0132] S4、refer to Figure 11 The pixel electrode 5 is plated on the upper surface of the gate insulating layer 4, and the pixel electrode 5 is also located beside the gate 2.

[0133] The first electrode block 51, the second electrode block 52 and the third electrode block 53 are plated in the first hole 41, the second hole 42 and the third hole 43 respectively, the first electrode block 51 is connected with the gate 2, the second electrode block 52 is connected with the first CK signal wire 31, and the third electrode block 53 is connected with the third CK signal wire 33;

[0134] The first electrode block 51, the second electrode block 52 and the third electrode block 53 are made of the same material as the pixel electrode 5;

[0135] The materials of the pixel electrode 5, the first electrode block 51, the second electrode block 52 and the third electrode block 53 are all ITO, mainly because ITO has good conductivity and light transmittance, PVD film forming and acid liquid wet etching. By pre-opening the first hole 41, the second hole 42 and the third hole 43 in the gate insulation layer 4, and then filling the first electrode block 51, the second electrode block 52 and the third electrode block 53 respectively, the influence of subsequent process etching on the metal of the first metal layer is avoided.

[0136] S5, refer to Figure 12 The active layer 6 is plated on the upper surface of the gate insulation layer 4, and the active layer 6 is located directly above the gate 2; the active layer 6 is in the pixel display area 11.

[0137] The material of the active layer 6 is selected as metal oxide semiconductor such as IGZO, PVD film forming and wet etching.

[0138] S6, refer to Figure 13 The second metal layer is plated on the upper surface of the gate insulation layer 4 to form the source 7, the drain 8 and the first signal connection wire 91 which are distributed at intervals, the source 7 is connected with the left end of the active layer 6, the drain 8 is connected with the right end of the active layer 6, the drain 8 is also connected with the pixel electrode 5, the right end 911 of the first signal connection wire is connected with the first electrode block 51, and the left end 912 of the first signal connection wire is connected with the second electrode block 52; the source 7 and the drain 8 are both in the pixel display area 11.

[0139] The material of the second metal layer can be selected as MO / AL / MO three-layer structure or Ti / AL / Ti three-layer structure, PVD film forming and acid liquid wet etching. The resistance of AL is small and is used for conducting electricity (Cu can be used instead), which can reduce impedance and power consumption; secondly, the expansion coefficients of the outer metal MO or Ti are small, which can inhibit the deformation of AL in high temperature process and can also prevent the oxidation of AL.

[0140] S7, refer to Figure 14 The passivation layer 10 is plated on the upper surfaces of the gate insulation layer 4, the active layer 6, the second metal layer and the pixel electrode 5;

[0141] A fourth hole 101 is etched in the passivation layer 10, and the third electrode block 53 is exposed in the fourth hole 101. The fourth hole is outside the pixel display area.

[0142] The material of the passivation layer 10 is SiO2, and the fourth hole 101 is etched by CVD. The fourth hole 101 provides a connection between the third CK signal line 33 and the conductive layer 20. Since the gate insulating layer 4 below the fourth hole 101 has been etched to form the third hole 43 in step S3, and is covered by ITO with excellent conductivity, the etching of the fourth hole 101 stops after the third electrode block 53 is exposed, so that the third CK signal line 33 is not etched, and the problems of oxidation of the inner metal line (AL) due to the absence of the outer protective metal (MO or Ti) of the third CK signal line 33, and the increase of contact impedance are avoided.

[0143] S8、refer to Figure 15 The conductive layer 20, the second signal connection line 92, and the light shielding metal layer 30 are plated on the upper surface of the passivation layer 10. The conductive layer 20 is located directly above the drain 8. The conductive layer is connected to the right end of the second signal connection line 92. The left end of the second signal connection line 92 passes through the fourth hole 101 and is connected to the third electrode block 53. The light shielding metal layer 30 is located directly above the channel of the active layer 6. The light shielding metal layer 30 is spaced apart from the conductive layer 20 and the second signal connection line 92.

[0144] The material of the light shielding metal layer 30 and the conductive layer 20 is the same as that of the first metal layer.

[0145] The material of the conductive layer 20 and the light shielding metal layer 30 can be a three-layer structure of MO / AL / MO, a three-layer structure of Ti / AL / Ti, a double-layer structure of AL / MO (MO as the top layer), or a double-layer structure of AL / Ti (Ti as the top layer), which is formed by PVD. AL has small resistance and is used for conduction (which can be replaced by Cu), which can reduce impedance and power consumption. In addition, the expansion coefficients of MO and Ti are small, which can inhibit the deformation of AL during high-temperature processing and prevent oxidation of AL. The conductive layer 20 is designed to be located directly above the drain 8, so as to form a capacitor structure with the drain 8, i.e., to supplement the capacitance, and the capacitance of the supplemented capacitance is consistent with that of the parasitic capacitance formed by the gate 2 and the drain 8. This can be achieved by adjusting the facing area and film distance of the conductive layer 20. The light shielding metal layer 30 is located directly above the channel of the active layer 6 and is floating, without contact with the conductive layer 20 and the second signal connection line 92, which can play a role in light shielding and improve the stability of the TFT device.

[0146] AsFigure 7 As shown, the conductive layer 20 and the second signal connection line 92 do not cover the channel of the active layer 6; the voltage signal of the conductive layer 20 and the second signal connection line 92 does not interfere with the channel of the active layer 6, ensuring the stability of the active layer.

[0147] Further comprising: in the S6, the second metal layer also forms the TP trace 40 distributed at intervals;

[0148] S9, refer to Figure 16 The outer insulation layer 50 is plated on the upper surface of the conductive layer 20, the light shielding metal layer 30, and the passivation layer 10, the fifth hole 501 is etched on the outer insulation layer 50, the fifth hole 501 penetrates the passivation layer 10, and the TP trace 40 is exposed on the fifth hole;

[0149] The material of the outer insulation layer 50 can be SiOx, SiNO, SiNx, etc., and is formed by CVD. The fifth hole 501 is obtained by dry etching through the insulation layer and the passivation layer 10 until the TP trace 40 is exposed. The purpose of setting the fifth hole 501 is to provide the connection between the common electrode 60 and the TP trace 40.

[0150] S10, refer to Figure 17 The common electrode 60 is plated on the upper surface of the outer insulation layer 50, and the common electrode 60 is also connected with the TP trace 40 through the fifth hole 501.

[0151] The material of the common electrode 60 is ITO, mainly because ITO has good conductivity and light transmittance, and is formed by PVD and wet etched with acid solution.

[0152] Although the specific embodiments of the present application are described above, those skilled in the art should understand that the specific embodiments described are only illustrative, and are not intended to limit the scope of the present application. Equivalent modifications and variations made by those skilled in the art in accordance with the spirit of the present application should be covered within the scope of the claims of the present application.

Claims

1. An array substrate for reducing the influence of parasitic capacitance couple, characterized in that: include: glass substrate; a first metal layer, plated on the upper surface of the glass substrate, forming a gate, a first CK signal line, and a third CK signal line that are spaced apart, wherein the potential of the first CK signal line is opposite to that of the third CK signal line; a gate insulating layer, plated on the upper surface of the glass substrate and the first metal layer, the gate insulating layer being provided with a first hole, a second hole, and a third hole, the gate being exposed through the first hole, the first CK signal trace being exposed through the second hole, and the third CK signal trace being exposed through the third hole; a pixel electrode, plated on the upper surface of the gate insulating layer and located on the side of the gate; a first electrode block, plated on the first hole and connected to the grid; a second electrode block, plated on the second hole and connected to the first CK signal trace; a third electrode block, plated on the third hole and connected to the third CK signal trace; The first electrode block, the second electrode block, and the third electrode block are made of the same material as the pixel electrode; an active layer, plated on the upper surface of the gate insulating layer and also located directly above the gate; a second metal layer, plated on the upper surface of the gate insulating layer, forming a source electrode, a drain electrode, and a first signal connection line that are spaced apart, the source electrode being connected to the left end of the active layer, the drain electrode being connected to the right end of the active layer, and the drain electrode being further connected to the pixel electrode, the right end of the first signal connection line being connected to the first electrode block, and the left end of the first signal connection line being connected to the second electrode block; a passivation layer, plated on the upper surfaces of the gate insulating layer, the active layer, the second metal layer, and the pixel electrode, wherein the passivation layer is provided with a fourth hole, and the third electrode block is exposed through the fourth hole; a conductive layer, plated on the upper surface of the passivation layer and directly above the drain electrode; a second signal connection line is further plated on the upper surface of the passivation layer; the conductive layer is connected to the right end of the second signal connection line; and the left end of the second signal connection line passes through the fourth hole and is connected to the third electrode block; a light-shielding metal layer, plated on the upper surface of the passivation layer and located directly above the trench of the active layer, wherein the light-shielding metal layer is spaced apart from the conductive layer and the second signal connection line; The light-shielding metal layer, the conductive layer, the second signal connection line and the first metal layer are made of the same material.

2. The array substrate for reducing the influence of parasitic capacitance couple according to claim 1, characterized in that: Also includes: The second metal layer also forms TP traces distributed at intervals; an outer insulating layer, plated on the upper surfaces of the conductive layer, the light-shielding metal layer, and the passivation layer, wherein the outer insulating layer is provided with a fifth hole, the fifth hole penetrating the passivation layer, and the TP trace is exposed in the fifth hole; A common electrode is plated on the upper surface of the outer insulating layer, and the common electrode is further connected to the TP trace through the fifth hole.

3. The array substrate for reducing the influence of parasitic capacitance couple according to claim 2, characterized in that: The first metal layer, the second metal layer, the conductive layer, the second signal connection line, and the light-shielding metal layer are all Ti / AL / Ti three-layer structures or MO / AL / MO three-layer structures.

4. The array substrate for reducing the influence of parasitic capacitance couple according to claim 2, characterized in that: The gate insulating layer is a SiOx single-layer structure or a SiNx / SiOx double-layer structure, the passivation layer is made of SiO2, and the outer insulating layer is made of SiOx, SiNO or SiNx.

5. The array substrate for reducing the influence of parasitic capacitance couple according to claim 2, characterized in that: The active layer is made of IGZO material, and the pixel electrode, the first electrode block, the second electrode block, the third electrode block and the common electrode are all made of ITO material.

6. The array substrate for reducing the influence of parasitic capacitance couple according to claim 1, characterized in that: The first metal layer further forms a second CK signal line and a fourth CK signal line that are spaced apart from each other, and the potential of the second CK signal line is opposite to that of the fourth CK signal line; The first CK signal line is connected to the gate of the array substrate in the first row, the second CK signal line is connected to the gate of the array substrate in the second row, the third CK signal line is connected to the conductive layer of the array substrate in the first row, and the fourth CK signal line is connected to the conductive layer of the array substrate in the second row.

7. The array substrate for reducing the influence of parasitic capacitance couple according to claim 6, characterized in that: The signal timing phase of the first CK signal line is one quarter cycle earlier than the signal timing phase of the second CK signal line, and the signal timing phase of the third CK signal line is one quarter cycle earlier than the signal timing phase of the fourth CK signal line.

8. A method for manufacturing an array substrate for reducing the influence of parasitic capacitance couple, characterized in that: The following steps are involved: S1. Plate a first metal layer on the upper surface of a glass substrate to form a gate, a first CK signal line, and a third CK signal line that are spaced apart. The potential of the first CK signal line is opposite to that of the third CK signal line. S2, coating a gate insulating layer on the upper surface of the glass substrate and the first metal layer; S3, opening a first hole, a second hole, and a third hole in the gate insulating layer, wherein the gate is exposed through the first hole, the first CK signal trace is exposed through the second hole, and the third CK signal trace is exposed through the third hole; S4, plating a pixel electrode on the upper surface of the gate insulating layer, wherein the pixel electrode is also located on the side of the gate; Plating a first electrode block, a second electrode block, and a third electrode block on the first hole, the second hole, and the third hole, respectively, wherein the first electrode block is connected to the gate, the second electrode block is connected to the first CK signal trace, and the third electrode block is connected to the third CK signal trace; The first electrode block, the second electrode block, and the third electrode block are made of the same material as the pixel electrode; S5, depositing an active layer on the upper surface of the gate insulating layer, wherein the active layer is located directly above the gate; S6. Plate a second metal layer on the upper surface of the gate insulating layer to form a source electrode, a drain electrode, and a first signal connection line that are spaced apart. The source electrode is connected to the left end of the active layer, the drain electrode is connected to the right end of the active layer, and the drain electrode is also connected to the pixel electrode. The right end of the first signal connection line is connected to the first electrode block, and the left end of the first signal connection line is connected to the second electrode block. S7, coating a passivation layer on the upper surfaces of the gate insulating layer, the active layer, the second metal layer, and the pixel electrode; A fourth hole is formed in the passivation layer, wherein the third electrode block is exposed in the fourth hole; S8. Plate a conductive layer, a second signal connection line, and a light-shielding metal layer on the upper surface of the passivation layer, wherein the conductive layer is also located directly above the drain electrode, the conductive layer is connected to the right end of the second signal connection line, and the left end of the second signal connection line passes through the fourth hole and is connected to the third electrode block. The light-shielding metal layer is also located directly above the channel of the active layer, and the light-shielding metal layer is spaced apart from the conductive layer and the second signal connection line. The light-shielding metal layer and the conductive layer are made of the same material as the first metal layer.

9. The method for manufacturing an array substrate for reducing the influence of parasitic capacitance couple according to claim 8, characterized in that: Also includes: In the step S6, the second metal layer further forms TP traces distributed at intervals; S9, plating an outer insulating layer on the upper surfaces of the conductive layer, the light-shielding metal layer, and the passivation layer, and forming a fifth hole in the outer insulating layer, the fifth hole penetrating the passivation layer, and exposing the TP trace through the fifth hole; S10, plating a common electrode on the upper surface of the outer insulating layer, and connecting the lead of the common electrode through the fifth hole to the TP trace.

10. The method for manufacturing an array substrate for reducing the influence of parasitic capacitance couple according to claim 9, characterized in that: The first metal layer, the second metal layer, the conductive layer, the second signal connection line, and the light-shielding metal layer are all Ti / AL / Ti three-layer structures or MO / AL / MO three-layer structures.

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