A frequency hopping phase-continuous frequency synthesizer and a method of controlling the same

Abstract

The application discloses a frequency hopping phase continuous frequency synthesizer, which comprises a thermostat crystal oscillator, a power divider, a clock distributor, a comb spectrum generator, an FPGA, a diplexer, a first filter, a DDS, an M-path S-waveband switch filter group, a second filter, a first amplifier, a frequency mixer, an N-path S-waveband switch filter group, a second amplifier, a frequency doubler, a third filter and a third amplifier, and discloses a frequency hopping phase continuous frequency synthesizer control method. The frequency synthesizer adopts a brand-new frequency standard frequency, an intermediate frequency frequency and a control logic calculation method, realizes frequency hopping phase continuity of DDS output frequency, and solves the problem of phase continuity of small-step jumping of the frequency synthesizer. The frequency synthesizer has the advantages of low noise and large-step jumping of direct analog frequency synthesis technology, and has the characteristics of small-step jumping of direct digital type.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of radio frequency electronic technology, in particular to a frequency hopping phase continuous frequency synthesizer and a control method thereof. BACKGROUND

[0002] There are various frequency synthesis technologies, which can be divided into direct frequency synthesis and indirect frequency synthesis technologies. Direct frequency synthesis technologies include direct analog frequency synthesis and direct digital frequency synthesis. The frequency synthesizer realized by the indirect frequency synthesis mode such as phase-locked loop cannot realize high-speed frequency hopping, and cannot realize phase continuity after frequency hopping. The direct analog frequency synthesizer realized by the operation such as addition, subtraction and multiplication of reference frequency can realize phase continuity after frequency hopping, but the frequency hopping step frequency realized by this mode is generally an integer multiple of the reference frequency, which cannot realize small-step frequency hopping, and the product has large volume and high power consumption, which cannot meet the current demand for frequency synthesizers.

[0003] In view of the above problems, the present application provides a frequency hopping phase continuous frequency synthesizer with small-step frequency hopping phase continuity and a control method thereof. SUMMARY

[0004] The present application provides a frequency hopping phase continuous frequency synthesizer with small-step frequency hopping phase continuity and a control method thereof.

[0005] The application aims to provide a frequency hopping phase continuous frequency synthesizer, which comprises a thermostat crystal oscillator, a power divider, a clock distributor, a comb spectrum generator, an FPGA, a duplexer, a first filter, a DDS, an M-way S-band switch filter group, a second filter, a first amplifier, a mixer, an N-way S-band switch filter group, a second amplifier, a frequency doubler, a third filter and a third amplifier, the output port of the thermostat crystal oscillator is connected with the input port of the power divider, the two output ports of the power divider are respectively connected with the input ports of the comb spectrum generator and the clock distributor, the output port of the clock distributor is connected with the clock input port of the FPGA, the I / 0 ports of the FPGA are respectively connected with the D0-DN and I0 / UPDATA ports of the DDS, the output port of the comb spectrum generator is connected with the input common port of the duplexer, the output port H of the duplexer is connected with the input port of the first filter, the output port L of the duplexer is connected with the radio frequency input port of the M-way S-band switch filter group, the multiple I0 ports of the FPGA are connected with the logic control input ends of the M-way S-band switch filter group, the radio frequency output end of the M-way S-band switch filter group is connected with the first amplifier, the output port of the first amplifier is connected with the local oscillator input port of the mixer, the output port of the DDS is connected with the input port of the second filter, the output port of the second filter is connected with the intermediate frequency input port of the mixer, the radio frequency output port of the mixer is connected with the radio frequency input end of the N-way S-band switch filter group, the radio frequency output port of the N-way S-band switch filter group is connected with the input port of the second amplifier, the output port of the second amplifier is connected with the input port of the frequency doubler, the output port of the frequency doubler is connected with the input port of the third filter, and the output port of the third filter is connected with the input port of the third amplifier.

[0006] Further, the high-stable clock generated by the thermostat crystal oscillator provides the overall high-stable system clock f1.

[0007] Further, the comb spectrum generator generates the comb spectrum signal with the frequency interval f1, and the thermostat crystal oscillator provides the system running clock clk for the FPGA through the clock distributor.

[0008] Further, the FPGA controls the frequency, phase and amplitude of the DDS.

[0009] Further, the first filter extracts the reference clock REF-CLK required by the DDS from the comb spectrum generated signal, and provides the high-frequency clock reference signal for the DDS.

[0010] Further, the M-way S-band switch filter group generates M S-band frequency markers, and the FPGA selects and outputs the M S-band frequency marker signals.

[0011] Further, the first amplifier amplifies the M frequency marker signals generated by the filter, and provides the local oscillator driving signal for the mixer.

[0012] Further, the DDS generates an intermediate frequency signal with a step of Δf / 2MHz under the control of the FPGA, and the second filter filters out the out-of-band spurs of the intermediate frequency signal generated by the DDS, and the second filter provides the mixing with the intermediate frequency signal.

[0013] Further, the mixer mixes the input local oscillator signal with the intermediate frequency signal, and generates an S-band radio frequency signal with a step frequency of Δf / 2MHz, the N-path S-band switch filter bank filters out the non-required intermodulation signals under the control of the FPGA, the second amplifier amplifies the S-band signal generated by the segmented filtering, the frequency doubler doubles the input S-band signal fx with a step of Δf / 2MHz, the third filter filters out the fundamental frequency fx, 3fx and 4fx and the like output by the frequency doubler, and obtains a C-band signal with a step of ΔfMHz, and the third amplifier amplifies the required C-band signal to the required power.

[0014] A frequency hopping phase continuous frequency synthesizer control method applied to a frequency hopping phase continuous frequency synthesizer, and the control method is as follows:

[0015] The clock (clk) distributed by the clock distributor is used as the system clock of the FPGA. The clk is used as the detection control clock of the functions such as the DDS frequency control word and the phase control word (D0…DN) issued, and the frequency synthesizer health state detection. The clk clock is K-divided in the FPGA to obtain the SYCN_FPGA signal, and the frequency of the SYCN_FPGA signal is the greatest common divisor of the DDS output signal 2.5MHz, the intermediate frequency output frequency and the DDS system working clock.

[0016] F_EN is an external frequency control latch signal, and F0…FN is the frequency control signal of the frequency synthesizer. When the external control signal is issued to the frequency synthesizer, the F_EN instruction arrives, the frequency synthesizer latches and decodes the external frequency control instruction, and synchronously issues the frequency word and the phase control word of the DDS to the DDS under the clk, and synchronously issues the IO / UPDATA to the DDS and the switch driver under the SYCN_FPGA signal.

[0017] The frequency synthesizer of the application adopts a new logic control clock calculation method, realizes frequency hopping phase continuity of DDS output frequency, and solves the problem of phase continuity of small step hopping of the frequency synthesizer. The frequency synthesizer has the advantages of low noise and large step hopping of direct analog frequency synthesis technology, and the characteristics of small step hopping of direct digital synthesis. In addition, by modifying the number of frequency switching filters of the switch filter bank, a larger bandwidth frequency synthesis can be realized, and the expansibility is very strong. At the same time, in the frequency synthesizer provided by the patent, a large number of switch filter banks are replaced by DDS, which can greatly reduce the power consumption and volume of the product. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1 is a principle block diagram of the application;

[0019] Figure 2 is a control principle block diagram of the application.

[0020] In the figure: 1, constant temperature crystal oscillator; 2, power divider; 3, clock distributor; 4, comb spectrum generator; 5, FPGA; 6, duplexer; 7, first filter; 8, DDS; 9, M-way S-band switch filter bank; 10, first amplifier; 11, second filter; 12, frequency mixer; 13, N-way S-band switch filter bank; 14, second amplifier; 15, frequency doubler; 16, third filter; 17, third amplifier. DETAILED DESCRIPTION

[0021] The application provides a frequency hopping phase continuous frequency synthesizer, which comprises a thermostat crystal oscillator 1, a power divider 2, a clock distributor 3, a comb spectrum generator 4, an FPGA 5, a duplexer 6, a first filter 7, a DDS 8, an M-path S-band switch filter group 9, a second filter 11, a first amplifier 10, a mixer 12, an N-path S-band switch filter group 13, a second amplifier 14, a frequency doubler 15, a third filter 16 and a third amplifier 17.

[0022] In the embodiment, the high-stable clock generated by the thermostat crystal oscillator 1 provides the high-stable system clock f1 of the whole system.

[0023] In the embodiment, the comb spectrum generator generates the comb spectrum signal with the frequency interval f1, and the thermostat crystal oscillator 1 provides the system running clock clk for the FPGA through the clock distributor.

[0024] In the embodiment, the FPGA 5 controls the frequency, phase and amplitude of the DDS 8.

[0025] In the embodiment, the first filter 7 extracts the reference clock REF-CLK required by the DDS 8 from the comb spectrum signal and provides the high-frequency clock reference signal for the DDS 8.

[0026] In the embodiment, the M-path S-band switch filter group 9 generates M S-band frequency markers, and the FPGA 5 selects and outputs the M S-band frequency marker signals.

[0027] In the embodiment, the first amplifier 10 amplifies the M frequency marker signals generated by the filter, and provides a local oscillator driving signal for the frequency mixer 12.

[0028] In the embodiment, the DDS 8 generates an intermediate frequency signal with a step of Δf / 2 MHz under the control of the FPGA 5, and the second filter 11 filters out the out-of-band spurs of the intermediate frequency signal generated by the DDS 8, and provides the intermediate frequency signal for the frequency mixer.

[0029] In the embodiment, the frequency mixer 12 mixes the input local oscillator signal with the intermediate frequency signal, and generates an S-band radio frequency signal with a step frequency of Δf / 2 MHz, the N-path S-band switch filter group 13 filters out the non-required intermodulation signals under the control of the FPGA 5, the second amplifier 14 amplifies the S-band signals generated by the segmented filtering, the frequency doubler 15 doubles the input S-band signal fx with a step of Δf / 2 MHz, the third filter 16 filters out the fundamental frequency fx, 3fx and 4fx, etc. output by the frequency doubler 15, and obtains a C-band signal with a step of Δf MHz, and the third amplifier 17 amplifies the required C-band signal to the required power.

[0030] The application also provides a frequency hopping phase continuous frequency synthesizer control method, which is applied to a frequency hopping phase continuous frequency synthesizer, and the control method is as follows.

[0031] The clock (clk) distributed by the clock distributor is used as the system clock of the FPGA. The clk is used as the detection control clock of the functions of issuing the DDS frequency, phase and amplitude control word (D0…DN), frequency synthesizer health state detection, etc. The clk clock is K-divided in the FPGA to obtain the SYCN_FPGA signal, and the greatest common divisor of the frequency of the SYCN_FPGA signal, the intermediate frequency frequency output by the DDS and the system working clock of the DDS is taken as Δf / 2.

[0032] F_EN is an external frequency control latch signal, and F0…FN is an external frequency control signal of the frequency synthesizer. When the external control signal is issued to the frequency synthesizer, the frequency synthesizer decodes the external frequency control instruction, and issues the frequency, phase and amplitude control word of the DDS to the DDS synchronously with the clk. After the F_EN instruction arrives, the IO / UPDATA is issued to the DDS synchronously with the SYCN_FPGA signal, and the switch control signals of the N-path S-band switch filter group and the M-path S-band switch filter group are issued synchronously with the SYCN_FPGA to realize frequency selection.

[0033] Although the specific embodiments of the present application are described in detail with reference to the accompanying drawings, it is not understood as a limitation to the scope of protection of the present patent. Various modifications and changes made by those skilled in the art which come within the scope of the claims described below are intended to fall within the scope of the present patent.

Claims

1. A frequency hopping phase-continuous frequency synthesizer comprising a temperature-controlled crystal oscillator, a power divider, a clock distributor, a comb spectrum generator, an FPGA, a diplexer, a first filter, a DDS, an M-way S-band switch filter bank, a second filter, a first amplifier, a frequency mixer, an N-way S-band switch filter bank, a second amplifier, a frequency doubler, a third filter, a third amplifier, characterized in that: The output port of the constant temperature crystal oscillator is connected with the input port of the power divider, two output ports of the power divider are respectively connected with the input port of the comb spectrum generator and the clock distributor, the output port of the clock distributor is connected with the clock input port of the FPGA, the I / O port of the FPGA is respectively connected with the DO-DN and I0 / UPDATA port of the DDS, the output port of the comb spectrum generator is connected with the input common port of the duplexer, the output port H port of the duplexer is connected with the input port of the first filter, the output port L port of the duplexer is connected with the radio frequency input port of the M-way S-band switch filter group, the multi-way I0 port of the FPGA is connected with the logic control input end of the M-way S-band switch filter group, the radio frequency output end of the M-way S-band switch filter group is connected with the first amplifier, the output port of the first amplifier is connected with the local oscillator input port of the mixer, the output port of the DDS is connected with the input port of the second filter, the output port of the second filter is connected with the intermediate frequency input port of the mixer, the radio frequency output port of the mixer is connected with the radio frequency input end of the N-way S-band switch filter group, the radio frequency output port of the N-way S-band switch filter group is connected with the input port of the second amplifier, the input port of the second amplifier is connected with the input port of the frequency doubler, the output port of the frequency doubler is connected with the input port of the third filter, the output port of the third filter is connected with the input port of the third amplifier.

2. A frequency hopping phase-continuous frequency synthesizer as claimed in claim 1, characterized in that: The high-stability clock generated by the constant temperature crystal oscillator provides the overall high-stability system clock f1.

3. A frequency hopping phase-continuous frequency synthesizer as claimed in claim 1, characterized in that: The comb spectrum generator generates a comb spectrum signal with a frequency interval f1, and the constant temperature crystal oscillator provides a system running clock clk for the FPGA through the clock distributor.

4. A frequency hopping phase-continuous frequency synthesizer as claimed in claim 1, characterized in that: The FPGA controls the frequency, phase and amplitude of the DDS.

5. A frequency hopping phase-continuous frequency synthesizer as claimed in claim 1, characterized in that: The first filter extracts the reference clock REF-CLK required by the DDS from the comb spectrum signal and provides a high-frequency clock reference signal for the DDS.

6. A frequency hopping phase-continuous frequency synthesizer as claimed in claim 1, characterized in that: The M-way S-band switch filter group generates M S-band markers, and the FPGA selects and outputs the M S-band marker signals.

7. A frequency hopping phase-continuous frequency synthesizer as claimed in claim 1, characterized in that: The first amplifier amplifies the M marker signals generated by the filter and provides a local oscillator driving signal for the mixer.

8. A frequency hopping phase-continuous frequency synthesizer as claimed in claim 4, characterized in that: The DDS generates an intermediate frequency signal with a step of Δf / 2 MHz under the control of the FPGA, the second filter filters out the out-of-band spurs of the intermediate frequency signal generated by the DDS, and the second filter provides an intermediate frequency signal for the mixer.

9. A frequency hopping phase-continuous frequency synthesizer as claimed in claim 1, characterized in that: The mixer mixes the input local oscillator signal with the intermediate frequency signal and generates an S-band radio frequency signal with a step frequency of Δf / 2 MHz, the N-path S-band filter group filters out the non-required intermodulation signal under the control of the FPGA, the second amplifier amplifies the S-band signal generated by the segmented filtering, the frequency doubler doubles the input S-band signal fx with a step of Δf / 2 MHz, the third filter filters out the fundamental frequency fx, 3fx and 4fx output by the frequency doubler, and obtains a C-band signal with a step of Δf MHz, and the third amplifier amplifies the required C-band signal to the required power.

10. A frequency hopping phase continuous frequency synthesizer control method, applied to the frequency hopping phase continuous frequency synthesizer of claim 1, the control method being as follows: The clock (clk) distributed by the clock distributor is used as the system clock of the FPGA, clk is used as the detection control clock of the functions of issuing DDS frequency, phase and amplitude control word (D0…DN), frequency synthesizer health state detection, etc., the clk clock is K-divided in the FPGA to obtain the SYCN_FPGA signal, the greatest common divisor of the frequency of the SYCN_FPGA signal, the DDS output intermediate frequency frequency and the DDS system working clock is taken as Δf / 2; F_EN is an external frequency control latch signal, F0…FN is an external frequency control signal of the frequency synthesizer, when the external control signal is issued to the frequency synthesizer, the frequency synthesizer decodes the external frequency control instruction, issues the frequency, phase and amplitude control word of the DDS to the DDS synchronously with clk, waits for the F_EN instruction to arrive, and issues the IO / UPDATA to the DDS synchronously with the SYCN_FPGA signal, and issues the N-path S-band switch filter group and the M-path S-band switch filter group switch control signal synchronously with the SYCN_FPGA to realize frequency selection.

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