Clock filtering equipment, clock filters and pulse generators

Abstract

A clock filtering device, in calibration mode, uses a controller to find an optimal cutoff frequency for the clock filter to achieve effective clock filtering. Further, in calibration mode, a reference frequency that fails to pass the clock filter and a reference frequency that passes the clock filter are used to time a first counter and a second counter, respectively. When the first counter reaches a certain count value, the count value of the second counter is obtained, and the count values ​​of the first and second counters are compared to see if they are similar, thereby adjusting the cutoff frequency of the clock filter. When the count values ​​of the two counters are not similar, the previous clock filter cutoff frequency is taken as the aforementioned optimal cutoff frequency, allowing the clock filter to effectively filter out noise in operating mode using this optimal cutoff frequency.

Description

Technical Field

[0001] This invention relates to a filtering technique, and more particularly to a clock filtering device, clock filter, and pulse generator that can dynamically adjust the cutoff frequency to effectively filter out noise in a clock. Background Technology

[0002] To prevent the clock from generating glitch signals (which can be considered a type of noise in the clock) due to unexpected reasons, which could lead to system instability, a clock filter (usually a low-pass filter) is typically used to filter the clock signal before it is supplied to the system, preventing glitch signals from entering the system.

[0003] Please refer to the following at the same time Figure 1 and Figure 2 , Figure 1 It is a block diagram of a prior art clock filtering device, and Figure 2 yes Figure 1 The waveforms of various signals in the prior art clock filtering device are shown. The prior art clock filtering device 1 includes an inverting unit INV1, pulse generators 12 and 13, and a set-reset flip-flop 14, wherein the pulse generator 12 is electrically connected to the inverting unit INV1, and the set-reset flip-flop 14 is electrically connected to the pulse generators 12 and 13.

[0004] The inverting unit INV1 generates a clock CLK_INB' that is inverted from the clock CLK_IN'. Pulse generators 12 and 13 receive the clocks CLK_IN' and CLK_INB' respectively and generate pulse signals P_OUT1 and P_OUT2 accordingly. The setting and reset inputs of the set / reset flip-flop 14 receive the pulse signals P_OUT1 and P_OUT2 respectively, thereby generating the clock CLK_OUT' at its non-inverting output.

[0005] When the frequency of clock CLK_IN' is too high (greater than the cutoff frequency of the prior art clock filter device 1), pulse generators 12 and 13 will be unable to generate pulse signals P_OUT1 and P_OUT2. Therefore, the clock CLK_OUT' at the non-inverting output of the reset trigger 14 will not transition (i.e., clock CLK_OUT' remains at the same threshold). In other words, if there is a spurious signal (usually high frequency) in clock CLK_IN', this spurious signal will be filtered out by the prior art clock filter device 1; or, if a hacker deliberately increases the frequency of clock CLK_IN' to attack the chip, this increased frequency clock CLK_IN' will also be filtered out by the prior art clock filter device 1.

[0006] The cutoff frequency of the prior art clock filter device 1 must be able to allow the system operating clock CLK_IN' to pass through while filtering out noise (e.g., spurious signals) in the clock CLK_IN'. Therefore, the cutoff frequency must be designed to be close to but not less than the frequency of the system operating clock CLK_IN'. If the frequency of the system operating clock CLK_IN' is changed, the pulse width of the pulse signals P_OUT1 and P_OUT2 output by the pulse generators 12 and 13 must be adjusted to change the cutoff frequency of the prior art clock filter device 1.

[0007] Please refer to Figure 1 and Figure 3 , Figure 3 This is a block diagram of a pulse generator in a prior art clock filtering device. Figure 1 Pulse generators 12 and 13 in the middle can be transmitted through Figure 3 This is achieved using a pulse generator 3. The pulse generator 3 includes multiple delay chains DL1 to DL4 (each consisting of at least one delay unit connected in series), multiple gates AND1 to AND4, and a signal selector MUX1. The clock CLK, after being processed by delay chain DL1 and gate AND1, generates a first pulse signal. The first pulse signal, after being processed by delay chain DL2 and gate AND2, generates a second pulse signal. The second pulse signal, after being processed by delay chain DL3 and gate AND3, generates a third pulse signal. The third pulse signal, after being processed by delay chain DL4 and gate AND4, generates a fourth pulse signal.

[0008] The signal selector MUX1 selects the first pulse signal, the second pulse signal, the third pulse signal, and the fourth pulse signal as the pulse signal P_OUT output by the pulse generator 3 according to the selection signal SEL. The pulse width of the first pulse signal is greater than the pulse width of the second pulse signal, the pulse width of the second pulse signal is greater than the pulse width of the third pulse signal, and the pulse width of the third pulse signal is greater than the pulse width of the fourth pulse signal.

[0009] The number of delay chains DL1 to DL4 determines the number of pulse widths that can be selected, and the selected pulse widths also determine the cutoff frequency of the prior art clock filtering device 1. Therefore, for a specific frequency clock CLK, the number of delay units it passes through can be adjusted so that the pulse width of the output pulse signal P_OUT can just switch the clock CLK_OUT' at the output of the input reset flip-flop 14. However, if the frequency of this clock CLK increases above this cutoff frequency (the specific frequency), the clock CLK_OUT' at the output of the input reset flip-flop 14 will not be able to switch.

[0010] Simply put, Figure 3The approach is to increase the number of delay units in pulse generators 12 and 13 to increase the adjustable range of the cutoff frequency of the prior art clock filter device 1. However, a wider adjustable range means a larger number of delay units, and since power consumption is proportional to the number of delay units, the prior art clock filter device 1, if it uses... Figure 3 Using pulse generator 3 to adjust the cutoff frequency presents a technical problem of excessive power consumption.

[0011] Furthermore, when the adjustable range of the cutoff frequency is wide, a specific method is needed to select the optimal cutoff frequency to effectively filter out noise in the clock. On the other hand, the cutoff frequency of the prior art clock filter 1 is affected by process parameters, voltage, and temperature. Although the process error is fixed at the factory and can be adjusted and compensated for, in the event of a hacker attack, a hacker can still cause the cutoff frequency of the prior art clock filter 1 to drift by changing the voltage and temperature. Therefore, there is a need for a technical solution that can dynamically adjust the cutoff frequency to prevent cutoff frequency drift. Summary of the Invention

[0012] One object of the present invention is to provide a clock filtering device, comprising: a reference clock generator for generating a first clock when enabled; a clock filter electrically connected to the reference clock generator for receiving an input clock and a control signal, and filtering the input clock to generate a second clock, wherein the cutoff frequency of the clock filter is controlled by the control signal, and in a calibration mode, the input clock is the first clock; a first counter electrically connected to the reference clock generator for counting according to the first clock to generate a first count value; a second counter electrically connected to the clock filter for counting according to the second clock to generate a second count value; and a controller electrically connected to the reference clock generator, the first counter, the second counter, and the clock filter, wherein in the calibration mode, when the first count value reaches a first specific count value or the first count value reaches a second specific count value, the controller disables the reference clock generator, and then generates a control signal based on whether the absolute difference between the second count value and the first count value is less than or equal to a specific absolute difference value.

[0013] Correspondingly, embodiments of the present invention also provide a pulse generator that does not require the use of multiple delay chains, and a clock filter constructed using the above-described pulse generator.

[0014] In summary, the clock filtering device provided in this embodiment of the invention can dynamically adjust the cutoff frequency, thus avoiding the influence of process parameters, voltage, and temperature on its cutoff frequency. Furthermore, the clock filter and pulse generator provided in this embodiment of the invention have advantages such as low power consumption and high security.

[0015] To further understand the technology, means, and effects of the present invention, reference can be made to the following detailed description and accompanying drawings, which will provide a thorough and concrete understanding of the purpose, features, and concepts of the present invention. However, the following detailed description and accompanying drawings are for reference and illustration only and are not intended to limit the present invention. Attached Figure Description

[0016] The accompanying drawings are provided to enable those skilled in the art to further understand the invention, and are incorporated in and constitute a part of the specification of the invention. The drawings illustrate exemplary embodiments of the invention and are used together with the specification to explain the principles of the invention.

[0017] Figure 1 This is a block diagram of a prior art clock filtering device.

[0018] Figure 2 yes Figure 1 Waveform diagrams of various signals from prior art clock filtering devices.

[0019] Figure 3 This is a block diagram of a pulse generator in a prior art clock filtering device.

[0020] Figure 4 This is a block diagram of a clock filtering device according to an embodiment of the present invention.

[0021] Figure 5 This is a block diagram of the pulse generator in the clock filtering device of this invention.

[0022] Figure 6 This is a block diagram of the clock filter in the clock filtering device according to an embodiment of the present invention. Detailed Implementation

[0023] Reference will now be made in detail to exemplary embodiments of the invention, which are illustrated in the accompanying drawings. Where possible, the same element symbols are used in the drawings and description to refer to the same or similar parts. Furthermore, the exemplary embodiments are merely one way of implementing the design concept of the invention, and the various examples described below are not intended to limit the invention.

[0024] This invention provides a technical solution for dynamically adjusting the cutoff frequency of a clock filter to prevent hackers from attacking the system by adjusting temperature and voltage to raise the cutoff frequency. In this technical solution, the clock filtering device, in calibration mode, uses a controller to find the optimal cutoff frequency of the clock filter to achieve effective clock filtering. Further, in calibration mode, a reference clock that does not pass through the clock filter (note: the reference clock is generated by the internal resistor-capacitor circuit of the clock filtering device and thus serves as a reference basis for clock adjustment) and a reference clock that passes through the clock filter will respectively trigger a first counter and a second counter. When the first counter counts to a first specific count value, the count value of the second counter is obtained, and the count values ​​of the first and second counters are compared to see if they are similar, thereby adjusting the cutoff frequency of the clock filter. When the count values ​​of the two counters are not similar, the previous cutoff frequency of the clock filter is taken as the aforementioned optimal cutoff frequency, allowing the clock filter to use this optimal cutoff frequency in operating mode to effectively filter out noise. In another configuration, the clock filter can be designed such that when the second counter reaches a second specific count value, the count value of the first counter is obtained, and the count values ​​of the first and second counters are compared to see if they are similar, thereby adjusting the cutoff frequency of the clock filter. In one embodiment, the first specific count value may be the same as or different from the second specific count value.

[0025] Specifically, clock filters are often used in the input path of external crystal oscillators to prevent the generation of spurious signals due to noise from the external crystal. The clock filter can filter out these spurious signals, preventing the system from being affected by them. External crystal oscillators have pins exposed outside the chip, making them frequent targets for hacker attacks. However, through the above-mentioned technical solution, since the reference clock is generated by the internal resistor-capacitor circuit of the clock filter, the cutoff frequency of the corrected clock filter is unaffected by changes in the external environment. Furthermore, this invention also proposes a technical solution that can adjust the cutoff frequency of the clock filter without increasing or decreasing the number of delay units, allowing the clock filter to achieve lower power consumption than previous techniques.

[0026] First, please refer to Figure 4 , Figure 4This is a block diagram of a clock filtering device according to an embodiment of the present invention. The clock filtering device 4 can be implemented as a single chip, comprising a reference clock generator (composed of the internal resistor-capacitor circuit 41 and the AND gate AND5 of the clock filtering device 4 chip), a clock filter 42, a signal selector MUX2, counters 43 and 44, and a controller 45. The clock filter 42 is electrically connected to the reference clock generator through the signal selector 42. The counter 43 is electrically connected to the reference clock generator. The counter 44 is electrically connected to the clock filter 42. The controller 45 is electrically connected to the reference clock generator, counters 43 and 44, and the clock filter 42.

[0027] In operating mode, the controller 42 controls the signal selector MUX2 via the selection signal SEL to select either the external clock EX_CLK or the first clock provided by the reference clock generator (i.e., the reference clock generated by the internal resistor-capacitor circuit 41) as the input clock CLK_IN of the clock filter 42. In other words, in operating mode, the clock filter 42 of the clock filtering device 4 filters out the external clock EX_CLK or the first clock provided by the reference clock generator selected according to system usage requirements. The signal selector MUX2 can be implemented, for example, through a multiplexer, and the invention is not limited thereto.

[0028] The clock filtering device 4 can enter the calibration mode periodically, or it can only enter the calibration mode when triggered by a specific event (e.g., an increase in ambient temperature, or other hacking events). In calibration mode, the controller 45 enables the reference clock generator to generate a first clock through the enable signal CLK_EN. The internal resistor-capacitor circuit 41 of the reference clock generator is electrically connected to the AND gate 5 of the reference clock generator. The two input terminals of the AND gate receive the enable signal CLK_EN and the reference clock generated by the internal resistor-capacitor circuit 41, respectively. Therefore, when the enable signal CLK_EN is at a logic high level, the AND gate will input the reference clock as the first clock to the counter 43 and the signal selector MUX2. The AND gate is actually used as a switching circuit. In other embodiments, it can also be a simple switching transistor, and the present invention is not limited thereto.

[0029] Clock filter 42 receives the input clock CLK_IN and the control signal ADJ, and filters the input clock CLK_IN to generate the second clock CLK_OUT. The cutoff frequency of clock filter 42 is controlled by the control signal ADJ. When adjusting the cutoff frequency of clock filter 42 in calibration mode, since only the reference clock generated by the internal resistor-capacitor circuit 41 can be trusted, the input clock CLK_IN of clock filter 42 must be the first clock from the reference clock generator. In operating mode, the input clock CLK_IN of clock filter 42 can be either the first clock selected by the selection signal SEL (related to system requirements) or the external clock EX_CLK. Preferably, the internal resistor-capacitor circuit 41 is designed to be temperature-insensitive to avoid significant frequency drift due to temperature effects.

[0030] When counters 43 and 44 enter calibration mode, they are first reset by the reset signal RST, and clock filter 42 also receives the control signal ADJ from controller 45. The value of control signal ADJ at this time is its initial value, typically corresponding to the highest cutoff frequency of clock filter 42. Then, after counter 43 counts to a first specific count value and controller 45 generates the control signal ADJ to adjust the cutoff frequency of clock filter 42 (i.e., after completing one calibration comparison), it is also reset by the reset signal RST. Counter 43 counts according to the first clock to generate a first count value. Counter 44 counts according to the second clock CLK_OUT to generate a second count value.

[0031] The controller 45 can be used to generate an enable signal CLK_EN, a control signal ADJ, a selection signal SEL, and a reset signal RST. The controller 45 determines whether the first count value of the counter 43 has reached a first specific count value. If the first count value has reached the first specific count value, the controller 45 pulls the enable signal CLK_EN low to disable the reference clock generator from generating a reference clock as the first clock. Next, the controller 45 retrieves the second count value of the counter 44 and calculates whether the absolute difference between the second count value and the first count value is less than or equal to a specific absolute difference value, and generates the control signal ADJ accordingly.

[0032] Specifically, considering that the reference clock of the internal resistor-capacitor circuit 41 is used as the input clock CLK_IN of the clock filter 42, and after being filtered by the clock filter 42, it has become a clock of a different domain, in order to solve the problem of cross-clock domain delay, the controller 45 obtains the second count value and calculates the absolute difference value only after disabling the reference clock generator for a first specific time. The first specific time can be one or two clock cycles, and this invention is not limited to this. In other embodiments, the cross-clock domain delay problem can be disregarded, and the controller 45 can directly obtain the second count value and calculate the absolute difference value without waiting.

[0033] In the calibration mode, when the absolute difference value is less than or equal to a specific absolute difference value, it indicates that the clock filter 42 has not completely filtered out the reference clock generated by the internal resistor-capacitor circuit 41. Therefore, the controller 45 generates a control signal ADJ to reduce the cutoff frequency of the clock filter, generates a reset signal RST to reset the counters 43 and 44, and re-enables the reference clock generator and makes the clock filtering device 4 continue to operate in the calibration mode.

[0034] After performing the above multiple correction comparisons, when the absolute difference value is greater than a specific absolute difference value, it indicates that the clock filter 42 has completely filtered out the reference clock generated by the internal resistor-capacitor circuit 41. Therefore, the controller 45 uses the previous control signal ADJ to set the cutoff frequency of the clock filter 42 and controls the clock filtering device 4 to end the correction mode and enter the working mode.

[0035] In operating mode, the input clock CLK_IN is usually selected from the external clock EX_CLK. Therefore, the frequency of the reference clock generated by the internal resistor-capacitor circuit 41 is usually designed to be approximately the same as the frequency of the external clock EX_CLK to simplify the design. Thus, the clock filter 42 uses the cutoff frequency corresponding to the control signal ADJ of the penultimate correction operation in the correction mode to filter out the input clock CLK_IN. However, this invention is not limited to this. If the cutoff frequency of the clock filter 42 can be adjusted linearly, then when the frequency of the reference clock generated by the internal resistor-capacitor circuit 41 is different from the frequency of the external clock EX_CLK, the control signal ADJ of the penultimate correction operation in the correction mode can be converted according to the multiple relationship between the frequency of the external clock EX_CLK and the reference clock generated by the internal resistor-capacitor circuit 41 to set the cutoff frequency of the clock filter 42 suitable for the frequency of the external clock EX_CLK.

[0036] Incidentally, the bit widths of counters 43 and 44 need to be designed with the following considerations in mind: for example, whether the cutoff frequency adjustment value will fall exactly on the threshold between filtering and not filtering, or whether the clock filter 42 might incorrectly filter the input clock CLK_IN at least once during multiple filtering operations. Since these situations can lead to degraded system performance, or even cause the second count value output by counter 44 to be incorrect due to the disappearance of the input clock CLK_IN, counters 43 and 44 with larger bit widths are typically used to observe the filtering process multiple times. This ensures that consecutively inputting input clocks CLK_IN successfully pass through the clock filter 42 before the cutoff frequency reaches the filtering frequency.

[0037] In this embodiment of the invention, the clock filter 42 described above can be adopted. Figure 3 The clock filter implemented by the pulse generator 3 architecture can also be other types of clock filters, and the present invention is not limited thereto. In one embodiment, the control signal ADJ is used to control the delay time of the clock filter 42 relative to the input clock CLK_IN, so as to determine the cutoff frequency of the clock filter 42. In other embodiments, the above-mentioned delay time may be related to the operating voltage of the clock filter 42, and the control signal ADJ can be used to control the aforementioned operating voltage.

[0038] Note that in another embodiment, counter 44 can be designed to count to a second specific count value. Controller 45 pulls the enable signal CLK_EN low to disable the reference clock generator from generating a reference clock as the first clock. Next, controller 45 retrieves the first count value from counter 43 and calculates whether the absolute difference between the second count value and the first count value is less than or equal to a specific absolute difference value, generating a control signal ADJ accordingly. Furthermore, controller 45 retrieves the first count value and calculates the absolute difference value only after disabling the reference clock generator for a second specific time period, where the second specific time period can be one or two clock cycles, and this invention is not limited thereto. The aforementioned first specific count value can be the same as or different from the second specific count value, and the first specific time period can be the same as or different from the second specific time period; the design depends on the user's needs, as long as it ensures that the count values ​​of counters 43 and 44 do not overflow before being retrieved by controller 45.

[0039] Please refer to Figure 5 , Figure 5 This is a block diagram of the pulse generator in the clock filtering device of this embodiment of the invention. The clock filter 42 described above can be adopted... Figure 5The clock filter is implemented using a pulse generator 5 architecture. The pulse generator 5 includes a voltage-adjustable regulator REG, a delay chain DL5 formed by multiple delay units DLU connected in series, and logic circuitry (implemented with an AND gate AND6, but this invention is not limited thereto). The delay chain DL5 is electrically connected to the voltage-adjustable regulator REG, and the logic circuitry is electrically connected to the delay chain DL5.

[0040] The voltage-adjustable regulator REG receives the control signal ADJ and generates an operating voltage VDD for the delay unit DLU and logic circuit based on ADJ. The delay chain DL5 delays the clock CLK by a specified time, generating a delayed clock. The logic circuit generates a pulse P_OUT based on the clock CLK and the delayed clock. The individual delay time of each of the delay units DLU and logic circuit is controlled by the operating voltage VDD. Therefore, the delay time of the clock CLK through the delay chain DL5 is related to the operating voltage VDD determined by the control signal ADJ, and the delay time of the clock CLK through the delay chain DL5 affects the operating voltage VDD. Figure 5 The cutoff frequency of the clock filter implemented by the pulse generator 5 architecture.

[0041] Unlike previous techniques, Figure 5 The pulse generator 5 eliminates the need for a large number of delay chains, significantly reducing the number of delay units (DLUs) and consequently decreasing power consumption and chip area. Furthermore, the voltage-adjustable regulator (REG) can utilize a high-efficiency, low-power regulator to further enhance the circuit's power efficiency. Because the REG has low power consumption and only supplies power to a small number of digital circuits (DLUs and AND6), no external capacitors are needed for voltage regulation, resulting in no exposed capacitor pins on the chip. Consequently, hackers cannot alter the cutoff frequency by applying voltage to the exposed capacitor pins, improving security compared to traditional methods.

[0042] Next, please refer to Figure 6 , Figure 6 This is a block diagram of the clock filter in the clock filtering device according to an embodiment of the present invention. Figure 5 The clock filter implemented by the pulse generator 5 architecture can be like Figure 6 Clock filter 6. Clock filter 6 includes an inverting unit INV2, level shifters LS1-LS4, pulse generators 61 and 62, and a flip-flop (implemented with a set-reset flip-flop 63, but this invention is not limited thereto), wherein pulse generators 61 and 62 and Figure 5The architecture of pulse generator 5 is the same, so the details already described will be omitted as appropriate. Level shifter LS1 is located between inverting unit INV2 and pulse generator 61. Level shifter LS2 is located between input clock CLK_IN and pulse generator 62. Level shifter LS3 is located between the first input terminal of the flip-flop (the setting input terminal of the reset flip-flop 63) and pulse generator 63. Level shifter LS4 is located between the second input terminal of the flip-flop (the reset input terminal of the reset flip-flop 63) and pulse generator 62.

[0043] The inverting unit INV2 generates the inverted input clock CLK_IN. The voltage-adjustable regulator REG1 of pulse generator 61 generates a first operating voltage VDD1 based on the first control signal ADJ1 of control signal ADJ, which is supplied to the delay chain DLU6 and the gate AND7. Gate AND7 is used to generate the pulse signal P_OUT1 based on the inverted input clock and the delayed inverted input clock. The voltage-adjustable regulator REG2 of pulse generator 62 generates a second operating voltage VDD2 based on the second control signal ADJ2 of control signal ADJ, which is supplied to the delay chain DLU7 and the gate AND8. Gate AND8 is used to generate the pulse signal P_OUT2 based on the input clock and the delayed input clock. The setting and reset input terminals of the set / reset trigger 63 receive the pulse signals P_OUT1 and P_OUT2 respectively to generate the second clock CLK_OUT at its non-inverting input terminal.

[0044] Although this embodiment uses two voltage-adjustable regulators REG1 and REG2 to provide the first operating voltages VDD1 and VDD2, the present invention is not limited thereto. The above approach takes into account process errors, hence the use of two voltage-adjustable regulators REG1 and REG2. If the process error is small, it can be designed to share a single voltage-adjustable regulator, that is, the two voltage-adjustable regulators REG1 and REG2 are the same voltage-adjustable regulator, and the first control signal ADJ1 and the second control signal ADJ2 are identical to each other.

[0045] In summary, the clock filtering device provided in this embodiment of the invention can dynamically adjust its cutoff frequency, thus preventing its cutoff frequency from being affected by process parameters, voltage, and temperature. In particular, this clock filtering device can prevent attacks by hackers who can cause the cutoff frequency to drift by changing voltage and temperature. Furthermore, the clock filter of the clock filtering device can be designed so that its cutoff frequency is related to the operating voltage, and only a small amount of digital circuitry is supplied with the operating voltage by an adjustable voltage regulator, thereby forming a capacitor-free circuit architecture. In this way, the clock filter does not need to have exposed capacitor pins, thus avoiding providing a path for input attack voltage to hackers, thereby increasing system security.

[0046] It should be understood that the examples and embodiments described herein are for illustrative purposes only, and that various modifications or alterations thereof will be suggested to those skilled in the art and will be included within the spirit and scope of the invention and within the scope of the appended claims.

Claims

1. A clock filtering device, characterized by The application relates to a clock filter device, comprising: a reference clock generator for generating a first clock when enabled; a clock filter electrically connected to the reference clock generator for receiving an input clock and a control signal and filtering the input clock to generate a second clock, wherein a cutoff frequency of the clock filter is controlled by the control signal, and in a calibration mode, the input clock is the first clock; a first counter electrically connected to the reference clock generator for counting according to the first clock to generate a first count value; a second counter electrically connected to the clock filter for counting according to the second clock to generate a second count value; and a controller electrically connected to the reference clock generator, the first counter, the second counter and the clock filter, in the calibration mode, when the first count value reaches a first specific count value or the second count value reaches a second specific count value, the controller disables the reference clock generator, and then generates the control signal according to whether an absolute difference value between the second count value and the first count value is less than or equal to a specific absolute difference value; wherein the control signal controls a delay time of the input clock of the clock filter to determine the cutoff frequency of the clock filter. In the calibration mode:

2. A clock filtering device as claimed in claim 1, characterized in that when the absolute difference value is less than or equal to the specific absolute difference value, the controller generates the control signal to reduce the cutoff frequency of the clock filter, resets the first counter and the second counter, and re-enables the reference clock generator and controls the clock filter device to continue operating in the calibration mode; and when the absolute difference value is not less than or equal to the specific absolute difference value, the controller uses the control signal of the last time to set the cutoff frequency of the clock filter, and controls the clock filter device to end the calibration mode and enter an operation mode. In the operation mode, the input clock is an external clock or the first clock. The controller acquires the second count value and calculates the absolute difference value only after a first specific time when the first count value reaches the first specific count value, or acquires the first count value and calculates the absolute difference value only after a second specific time when the second count value reaches the second specific count value.

3. A clock filtering device as claimed in claim 2, characterized in that The reference clock generator comprises:

4. A clock filtering device as claimed in claim 1, characterized in that an internal resistance-capacitance circuit for generating a reference clock; and 5. A clock filtering device as claimed in claim 1, characterized in that a switch circuit electrically connected to the internal resistance-capacitance circuit, the controller and the first counter for receiving the reference clock and an enable signal generated by the controller to provide the reference clock as the first clock when the reference clock generator is enabled. Further comprising: a signal selector electrically connected to the reference clock generator, the controller and the clock filter for selecting an external clock or the first clock as the input clock of the clock filter according to a selection signal generated by the controller in an operation mode.

6. A clock filtering device as claimed in claim 1, characterized in that ​ ​ 7. A clock filtering device as claimed in claim 1, characterized in that The delay time is associated with an operating voltage of the clock filter, and the control signal is used to control the operating voltage.

8. A clock filtering device as claimed in claim 1, characterized in that The clock filter comprises: a phase inversion unit for generating an inverted input clock of the input clock; a first pulse generator electrically connected to the phase inversion unit for delaying the inverted input clock by a first delay time to generate a delayed inverted input clock, and generating a first pulse signal according to the inverted input clock and the delayed inverted input clock, wherein a first operating voltage of the first pulse generator is associated with a first control signal of the control signal of the controller, and the first delay time is controlled by the first operating voltage; a second pulse generator for delaying the input clock by a second delay time to generate a delayed input clock, and generating a second pulse signal according to the input clock and the delayed input clock, wherein a second operating voltage of the second pulse generator is associated with a second control signal of the control signal of the controller, and the second delay time is controlled by the second operating voltage; and a flip-flop electrically connected to the first pulse generator and the second pulse generator, having a first input end receiving the first pulse signal, a second input end receiving the second pulse signal, and generating the second clock at an output end according to the first pulse signal and the second pulse signal.

9. A clock filtering device as claimed in claim 8, characterized in that The first pulse generator comprises: a first voltage adjustable regulator receiving the first control signal to generate the first operating voltage; a first delay chain electrically connected to the first voltage adjustable regulator, comprising at least one first delay unit for delaying the inverted input clock by the first delay time to generate the delayed inverted input clock; and a first logic circuit electrically connected to the first delay chain for generating the first pulse signal according to the inverted input clock and the delayed inverted input clock; wherein the first delay unit and the first logic circuit receive the first operating voltage, and an individual delay time of each of the first delay unit and the first logic circuit is controlled by the first operating voltage.

10. A clock filtering device as claimed in claim 9, characterized in that, The second pulse generator comprises: a second voltage adjustable regulator receiving the second control signal to generate the second operating voltage; a second delay chain electrically connected to the second voltage adjustable regulator, comprising at least one second delay unit for delaying the input clock by the second delay time to generate the delayed input clock; and a second logic circuit electrically connected to the second delay chain for generating the second pulse signal according to the input clock and the delayed input clock; wherein the second delay unit and the second logic circuit receive the second operating voltage, and an individual delay time of each of the second delay unit and the second logic circuit is controlled by the second operating voltage.

11. A clock filtering device as claimed in claim 10, characterized in that, The second operating voltage is the first operating voltage, and the second control signal is the first control signal.

12. A clock filtering device as claimed in claim 11, characterized in that, The second voltage adjustable regulator is the first voltage adjustable regulator.

13. A clock filtering device as claimed in claim 8, characterized in that Further comprising: a first level shifter disposed between the inverter and a first pulse generator; a second level shifter disposed between the input clock and the second pulse generator; a third level shifter disposed between the first input of the flip-flop and the first pulse generator; and a fourth level shifter disposed between the second input of the flip-flop and the second pulse generator. ​

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