A 2-7 prescaler with 50% duty cycle

Abstract

The present application relates to the technical field of frequency divider integrated circuit, in particular to a 2-7 prescaler with 50% duty cycle, which comprises a 2 / 3 frequency division unit with frequency division ratio expansion bit, an additional 2 frequency division logic module, an additional expansion transmission path module and an odd integer duty cycle correction logic module. The present application firstly performs 2 / 3 operation in the 2 / 3 frequency division unit according to the frequency division ratio, and then inputs the output signal into the additional 2 frequency division logic. When the frequency division ratio is greater than 3, the additional expansion transmission path module works. When the frequency division ratio is odd, the duty cycle correction module corrects the duty cycle of the input signal. Compared with the prior art, the present application has the advantages of simple circuit structure, wide frequency division ratio coverage, low noise contribution and output duty cycle close to 50%, and can be applied to multi-mode programmable frequency divider.

Description

Technical Field

[0001] This invention relates to the field of frequency divider integrated circuit technology, and more particularly to the design of high-speed wide-range multi-mode programmable frequency dividers, specifically a 2-7 prescaler with a 50% duty cycle. Background Technology

[0002] In modern radio frequency (RF) transceiver systems, the frequency synthesizer provides a high-quality local oscillator signal to the RF transceiver, and the quality of this signal directly determines the final performance of the transceiver system. The frequency divider, as a key module in the frequency synthesizer, operates at the highest frequency within the phase-locked loop (PLL) frequency synthesizer. It not only receives the high-frequency signal input from the previous stage but also outputs a high-quality low-frequency signal. Therefore, the performance of the frequency divider directly determines the overall performance of the PLL, and its circuit optimization is of great significance for improving system performance.

[0003] To maximize the application range of a frequency divider, it is required to cover the widest possible frequency band, have the largest possible division ratio, and the lowest possible noise contribution. The output signal of a programmable frequency divider is typically used as a clock signal, and a 50% duty cycle is one of the main standards for clock signals, making a 50% output duty cycle essential for the divider. However, achieving a 50% output duty cycle for odd-number divisions is very challenging. Programmable frequency dividers come in several architectures, but not all of them can achieve a 50% duty cycle.

[0004] like Figure 2 As shown, Figure 2 This is a diagram of a traditional cascaded 2 / 3 divider programmable frequency divider. This structure consists of several cascaded 2 / 3 divider units. The output of each 2 / 3 divider unit serves as the input to the next stage. The mod control signal output from each stage (except the first stage) is fed back to the previous stage. The mod control signal of the last stage is connected to a high level. The mod control signal output from each 2 / 3 divider unit is passed to the next stage and back along the divider link, synchronized with the operating clock of the previous stage during transmission.

[0005] The frequency division ratio D achieved by this structure X For: D X =P0+2.P1+2 2 .P2+…+2 n-1 .P n-1 +2 n The frequency division ratio range is (2 n ,2 n+1-1). Existing programmable frequency dividers with cascaded 2 / 3 divider units can cover small division ratios, and each divider unit is identical and independent, with a high degree of modularity. However, the division ratio range that this type of frequency divider can achieve is narrow, with the maximum division ratio being about twice the minimum division ratio. Furthermore, the duty cycle of the output signal cannot be adjusted, thus limiting the frequency divider's driving capability. Summary of the Invention

[0006] In view of the above-mentioned problems or shortcomings, and to solve the problems of the existing cascaded 2 / 3 divider programmable dividers having a narrow division ratio range, inability to adjust the duty cycle of the output signal, and limited drive capability, the present invention aims to provide a 2-7 prescaler with a 50% duty cycle.

[0007] A 2-7 prescaler with a 50% duty cycle includes four modules: a 2 / 3 divider unit DIV 2 / 3 with a division ratio extension bit, an additional 2-divide logic module AD2, an additional extended transmission path module APE, and an odd integer duty cycle correction logic module DCC.

[0008] The output of the 2 / 3 divider unit DIV 2 / 3 with frequency division ratio extension bits is connected to the additional 2 divider logic module AD2 and the additional extended transmission path module APE. The output of the additional 2 divider logic module AD2 is connected to the additional extended transmission path module APE and the odd integer duty cycle correction logic module DCC. The output of the additional extended transmission path module APE is connected to the input of the 2 / 3 divider unit DIV 2 / 3 with frequency division ratio extension bits.

[0009] clkin is the external input clock signal, providing clock signals for the D flip-flops in the four modules: the 2 / 3 divider unit DIV 2 / 3 with divider ratio extension bits, the additional 2 divider logic module AD2, the additional extended transmission path module APE, and the odd integer duty cycle correction logic module DCC; mod1 is the mod signal for mode selection, and mod1 is always 1; the programmable logic signals (P2, P1, P0) are derived from the divider ratio Dx through binary conversion, where mod_shift = P2; clkout is the output clock signal of the 2-7 prescaler.

[0010] The 2 / 3 divider unit DIV 2 / 3 with frequency division ratio extension bit (see details below) Figure 3 It includes two D flip-flops D1 and D2, a two-input selector MUX1, a two-input AND gate, two two-input NAND gates NAND1 and NAND2, a three-input XOR gate, and two inverters; as the core module of the 2-7 prescaler, it performs division by 2 / division by 3 operations.

[0011] P0, P1, and mod_shift are programmable logic signals determined by the division ratio. P0 and P1 are connected to the input ports of selector MUX1, and mod_shift is the control signal of selector MUX1.

[0012] The output signal of selector MUX1 is ANDed with the output signal of D flip-flop D2 and then enters a three-input XOR gate.

[0013] APEout is the clock signal output by the additional extended transmission path module APE, which is used as the input signal feedback input into the three-input XOR gate and inverter.

[0014] The output signal of D flip-flop D1 is used as a feedback signal input to the three-input XOR gate, and the output signal of the three-input XOR gate is the input of D flip-flop D1.

[0015] mod1 is the input signal of the two-input NAND gate NAND1. This signal and the output signal of the D flip-flop D1 are NAND-NOTed and then enter the input port of the two-input NAND gate NAND2. The output signal of the two-input NAND gate NAND1 is inverted to obtain modout0, which serves as the mod signal output of the entire 2 / 3 divider unit with frequency division ratio extension bits.

[0016] The additional 2-division logic module AD2 (such as...) Figure 4 As shown, it includes a D flip-flop D3, an inverter, and a three-input selector MUX2 controlled by two control bits. clkout_pre is the output clock signal of the additional divide-by-2 logic module AD2.

[0017] When the frequency division ratio is less than 4, that is, Dx = 2 or 3, mod_shift is 0. At this time, selector MUX2 is controlled by the control signal mod_shift to select the modout0 signal input to port I2. Flip-flop D3 generates the signal clkout_pre after a delay of one clock cycle.

[0018] When the division ratio is greater than 4, mod_shift is 1, and selector MUX2 selects the input signal according to the high and low changes of modout0 level: when the division ratio is even, that is, Dx = 4, 6 division, AD2 performs a division by 2 operation; when the division ratio is odd, that is, Dx = 5, 7 division, clkout_pre signal is used as feedback to enter the additional extended transmission path module APE for odd division.

[0019] The additional extended transmission path module (APE) (such as Figure 5As shown, it includes a D flip-flop D4 with a reset function and a three-input AND gate. The modout0, clkout_pre, and mod_shift signals are the input signals of the three-input AND gate, and the output signal of the three-input AND gate is the input signal of the D flip-flop D4. The additional extended transmission path module APE is enabled when the frequency division ratio Dx = 5 or 7. At this time, mod_shift is 1. The modout0 signal output from the 2 / 3 divider unit is ANDed with the clkout_pre signal output from the additional 2 divider logic module AD2, so that the modout0 signal switches between 2 divider and 3 divider and then feeds back to AD2, thereby realizing additional signal extension.

[0020] The odd integer duty cycle correction logic module DCC (such as Figure 6 As shown, it includes a D latch D5 with a reset function and a two-input AND gate. P0 serves as the reset signal for the D latch D5, controlling the operating state of the odd integer duty cycle correction logic module DCC. The odd integer duty cycle correction logic module DCC is enabled when the frequency division ratio is odd (P0 = 1). At this time, the D latch D5 delays the clkout_pre signal by half a cycle. The output signal of the D latch D5 is ANDed with the original clkout_pre signal to obtain the output clock signal clkout with a duty cycle of 50%.

[0021] Furthermore, the 50% duty cycle 2-7 prescaler is applied in a programmable frequency divider cascaded with 2 / 3 divider units, serving as a prescaler to replace the first-stage 2 / 3 divider unit, achieving 2-7 integer prescaler, and providing a 50% output duty cycle for each division ratio.

[0022] The D flip-flop in this invention primarily employs a current-mode controlled logic (CML) structure. Its fully differential structure provides differential output, which suppresses common-mode noise to some extent. Its current source uses a transistor-resistor series structure, further reducing phase noise. The output voltage swing is determined by the bias current and resistance, resulting in a smaller voltage swing and faster operating speed. Compared to existing technologies, this invention can provide a wider frequency range, achieve odd-integer duty cycle correction, and control the output signal duty cycle at 50%, effectively improving the drive capability of the frequency divider. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the structure of the present invention;

[0024] Figure 2 This is a schematic diagram of an existing programmable frequency divider based on cascaded 2 / 3 frequency divider units;

[0025] Figure 3This is a structural diagram of the 2 / 3 frequency divider unit DIV 2 / 3 with frequency division ratio extension bit of the present invention;

[0026] Figure 4 This is a diagram of the additional 2-division logic AD2 structure of the present invention;

[0027] Figure 5 This is a structural diagram of the additional extended transmission path APE of the present invention;

[0028] Figure 6 This is a structural diagram of the DCC (Duty Cycle Adjustment Module) of the present invention;

[0029] Figure 7 This is a diagram illustrating the operation of the embodiment with a 7-frequency division. Detailed Implementation

[0030] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments.

[0031] A 2-7 prescaler with a 50% duty cycle (e.g.) Figure 1 As shown, it includes a 2 / 3 divider unit (DIV 2 / 3) with a prescaler extension bit, an additional 2 divider logic module (AD2), an additional extended transmission path module (APE), and an odd integer duty cycle correction logic module (DCC). The output of the 2 / 3 divider unit DIV 2 / 3 with a prescaler extension bit is connected to the additional 2 divider logic module AD2 and the additional extended transmission path module APE. The output of the additional 2 divider logic module AD2 is connected to the additional extended transmission path module APE and the odd integer duty cycle correction logic module DCC. The output of the additional extended transmission path module APE is connected to the input of the 2 / 3 divider unit DIV 2 / 3 with a prescaler extension bit.

[0032] Four of the modules have their clock inputs connected to the external clock signal clkin; mod1 is the mod signal output from the 2 / 3 divider unit cascaded after the prescaler in the programmable divider. When the division ratio is less than 7, mod1 is always 1; the programmable logic signals (Pn-1, Pn-2, ..., P1, P0) are derived from the division ratio Dx through binary conversion, where mod_shift = P2∪(P3+P4+...+P...). n-1 clkout is the output clock signal of the 2-7 prescaler. The basic working principle of this example is as follows:

[0033] When the division ratio Dx = 2, the entire circuit is simplified to a standard 2 / 3 prescaler logic. D1 becomes a T flip-flop and performs a division by 2 operation. The output modout0 passes through MUX2 and enters D3. After a one-clock-cycle delay, the signal clkout_pre is generated. Since the even-number division duty cycle adjustment module does not work, the divided-by-two signal clkout is directly output.

[0034] When the division ratio Dx = 3, the 2 / 3 prescaler unit performs a division by 3 operation. The output signal of D2 overwrites the output signal of D1 and adds an extra input signal cycle to it. modout0 outputs a high-level divided-by-3 signal. Because P0 is 1 during the division by 3, the clkout_pre signal is input to latch D5 and ANDed with clkout_pre after a half-cycle delay, ultimately outputting a divided-by-3 clock signal clkout with a 50% duty cycle.

[0035] When the division ratio Dx = 4, the DCC and APE modules do not work, the 2 / 3 prescaler unit performs a division by 2 operation, and since mod_shift is 1, D3 performs a division by 2 operation, outputting a 4-division signal clkout.

[0036] When the division ratio Dx = 5, the APE and AD2 modules are enabled. Since P1 = 0, the MUX1 output is 0 at this time. Therefore, within two input clock cycles, modout0 is divided by 2 and generates the clkout_pre signal. The clkout_pre signal enters the three-input AND gate of the APE module. When modout0 is high, the D4 output is 1, causing the modout0 signal to extend by one clkin clock cycle. In this way, modout0 switches between division by 2 and division by 3 for 5 clock cycles, making clkout_pre a clkin divided by 5. Because P0 is 1 when divided by 5, the DCC module is enabled, outputting a 50% duty cycle divided-by-5 ​​clock signal clkout.

[0037] When the frequency division ratio Dx = 6, the DCC and APE modules do not work. The 2 / 3 frequency division unit performs a 3-fold division and outputs the modout0 signal to the AD2 module for a division by 2 operation to obtain the 6-fold output signal clkout.

[0038] When the division ratio Dx = 7, the APE module switches the modout0 signal output from the 2 / 3 divider unit between a 2-fold and a 3-fold division, and then passes it to the AD2 module, so that one half of the clkout_pre cycle contains 4 clkin cycles and the other half contains 3 clkin cycles. After the clkout_pre signal enters the DCC module, it finally outputs a 7-fold clock signal clkout with a 50% duty cycle.

[0039] When the 2-7 prescaler module is applied to a programmable frequency divider cascaded with 2 / 3 divider units, its working principle is as described above when the division ratio Dx ≤ 7. When the division ratio Dx > 7, the mod1 signal is no longer constantly 1 due to the influence of the subsequent cascaded 2 / 3 divider units. When the mod signal moves from right to left in the 2 / 3 prescaler chain, the frequency of modout is clkin / (Dx-7). The remaining 7 cycles of clkin are added by the 2-7 prescaler, and its duty cycle is corrected by the DCC module of the 2-7 prescaler to produce clkout with a duty cycle of 50%.

[0040] The timing sequence for this embodiment with a 7-fold frequency division is as follows: Figure 7 As shown in the figure, this embodiment successfully divides the external input clock signal clkin by 7 and outputs an output signal with a 50% duty cycle.

[0041] In summary, this invention primarily employs commonly used D flip-flops, D latches, basic logic gate structures, and selectors. First, a division-by-2 / division-by-3 operation is performed in the 2 / 3 divider unit based on the division ratio. Then, the output signal is input into the additional 2-division logic. When the division ratio is greater than 3, the additional extended transmission path module operates. When the division ratio is odd, the duty cycle correction module corrects the duty cycle of the input signal. Compared to existing technologies, this invention features simpler inter-module relationships, ensuring circuit flexibility. It allows the circuit to be applied to programmable frequency divider circuits with cascaded 2 / 3 divider units. Furthermore, it offers wide division ratio coverage, low noise contribution, and can achieve odd-integer duty cycle correction, controlling the output signal duty cycle to 50%, effectively improving the divider's driving capability. It can be applied to multi-mode programmable frequency dividers.

Claims

1. A 2-7 prescaler with 50% duty cycle, characterized by: The 2 / 3 division unit with division ratio extension bit DIV 2 / 3, an additional 2 division logic module AD2, an additional extended transmission path module APE and an odd integer duty cycle correction logic module DCC are included. The output of the 2 / 3 division unit with division ratio extension bit DIV 2 / 3 is connected with the additional 2 division logic module AD2 and the additional extended transmission path module APE, the output of the additional 2 division logic module AD2 is connected with the additional extended transmission path module APE and the odd integer duty cycle correction logic module DCC, and the output of the additional extended transmission path module APE is connected with the input of the 2 / 3 division unit with division ratio extension bit DIV 2 / 3. Clkin is an external input clock signal, which provides a clock signal for D flip-flops in the 2 / 3 division unit with division ratio extension bit DIV 2 / 3, the additional 2 division logic module AD2, the additional extended transmission path module APE and the odd integer duty cycle correction logic module DCC; mod1 is a mod signal for mode selection, and mod1 is always 1. P2, P1 and P0 are programmable logic signals converted from the division ratio Dx, wherein mod_shift=P2; clkout is an output clock signal of the 2-7 prescaler; The 2 / 3 division unit with division ratio extension bit DIV 2 / 3 includes two D flip-flops D1 and D2, a two-input selector MUX1, a two-input AND gate, two two-input NAND gates NAND1 and NAND2, a three-input XOR gate and two inverters; and performs 2 / 3 division operation. P0, P1 and mod_shift are programmable logic signals determined by the division ratio, P0 and P1 are connected with the input ports of the selector MUX1, and mod_shift is a control signal of the selector MUX1. The output signal of the selector MUX1 and the output signal of the D flip-flop D2 are input into the three-input XOR gate after being ANDed; APEout is a clock signal output by the additional extended transmission path module APE, which is input into the three-input XOR gate as an input signal and is input into the NAND gate NAND2 after being inverted by the inverter; The output signal of the D flip-flop D1 is input into the three-input XOR gate as a feedback signal, and the output signal of the three-input XOR gate is the input of the D flip-flop D1; mod1 is an input signal of the two-input NAND gate NAND1, which is input into the input port of the two-input NAND gate NAND2 after being ANDed with the output signal of the D flip-flop D1; modout0 is obtained by inverting the output signal of the two-input NAND gate NAND1, and is the mod signal output by the 2 / 3 division unit with division ratio extension bit DIV 2 / 3; the output of the NAND gate NAND2 is input into the D flip-flop D2; The additional 2 division logic module AD2 includes a D flip-flop D3, an inverter and a three-input selector MUX2 controlled by two control bits, and clkout_pre is the output clock signal of the additional 2 division logic module AD2. The two output terminals of the D flip-flop D3 are connected to the selection input ports I0 and I1 of the three-input selector MUX2 respectively, and modout0 is connected to the selection input port I2 and the control bit S1 of the three-input selector MUX2; the control signal mod_shift is connected to the control bit S0 of the three-input selector MUX2 after being inverted by an inverter; When the division ratio is less than 4, i.e. Dx=2, 3 division, mod_shift is 0, at this time, the selector MUX2 selects the modout0 signal input from the I2 port under the control of the control signal mod_shift, and the flip-flop D3 generates the signal clkout_pre after a delay of one clock cycle; When the division ratio is greater than 4, mod_shift is 1, and the selector MUX2 selects the input signal according to the high and low changes of the modout0 level: when the division ratio is even, i.e. Dx=4, 6 division, AD2 performs a division by 2 operation; when the division ratio is odd, i.e. Dx=5, 7 division, the clkout_pre signal is fed back into the additional extended transmission path module APE to perform odd division; The additional extended transmission path module APE comprises a D flip-flop D4 with a reset function and a three-input AND gate; modout0, clkout_pre and mod_shift signals are input signals of the three-input AND gate, and the output signal of the three-input AND gate is an input signal of the D flip-flop D4; the additional extended transmission path module APE is enabled when the division ratio Dx=5, 7, at this time, mod_shift is 1, and the modout0 signal and the clkout_pre signal are ANDed, so that the modout0 signal is switched between 2 division and 3 division and then fed back to AD2, thereby realizing additional expansion of the signal; The odd integer duty cycle correction logic module DCC comprises a D latch D5 with a reset function and a two-input AND gate; P0 is a reset signal of the D latch D5 and controls the working state of the odd integer duty cycle correction logic module DCC; the odd integer duty cycle correction logic module DCC is enabled when the division ratio is odd, at this time, the D latch D5 delays the clkout_pre signal by half a cycle, the output signal of the D latch D5 and the original clkout_pre signal are ANDed, and an output clock signal clkout with a duty cycle of 50% is obtained.

2. The 2-7 pre-divider for 50% duty cycle as claimed in claim 1 characterized by: The programmable frequency divider is applied to a 2 / 3 division unit cascade, and when the division ratio Dx≤7, it replaces the first-stage 2 / 3 division unit as a pre-divisor to realize 2-7 integer pre-division and provide an output duty cycle of 50% for each division ratio.

3. The 2-7 pre-divider for 50% duty cycle as defined in claim 1 wherein: When the frequency division ratio Dx>7, the mod1 signal is affected by the 2 / 3 frequency division unit of the next stage, and is no longer constant as 1. When the mod signal moves from right to left in the 2 / 3 pre-division chain, the frequency of modout is clkin / (Dx-7); the remaining 7 periods of clkin are added by the 2-7 pre-division, and the duty cycle is corrected by the DCC module of the 2-7 pre-division to generate clkout with a duty cycle of 50%.

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